Abstract: Various embodiments provide for determining clock gates for decloning based on simulation and a satisfiability solver, which can be part of electronic design automation (EDA). In particular, some embodiments use a simulation process to quickly determine whether enable signals associated with two clock gates are logically equivalent using a random input vector to a circuit design and, if logically equivalent by the simulation process, use a satisfiability solver to determine a variable assignment (e.g., at least one vector) such that the enable signals are found to be non-equivalent.

Abstract: A system for performing operations including accessing an integrated circuit design that includes a clock tree interconnecting a clock source to a plurality of clock sinks. The operations include receiving a request to adjust a current timing offset of the clock tree to a target timing offset. The clock tree is modified by moving a terminal of the group from a first location in the clock tree to a second location in the clock tree to generate an updated clock tree. During modification, the first and second locations are analyzed to determine a load reduction and increase at the respective terminals. One or more neighboring clock tree instances are adjusted to compensate for the load reduction and increase. The operations include providing an indication that the clock tree has been updated and complies with the target timing offset.

Abstract: An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Abstract: Aspects of the present disclosure address systems and methods for clock tree synthesis (CTS). A first iteration of CTS is performed to generate an intermediate clock tree for an integrated circuit (IC) design that includes one or more macros. Target pin insertion delays (PIDs) for the one or more macros are computed based on the intermediate clock tree using a linear program. A second iteration of CTS is performed using the target PIDs for the one or more macros to generate an optimized clock tree for the IC design.

Abstract: Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Abstract: Aspects of the present disclosure address systems and methods for local cluster refinement for integrated circuit (IC) designs using a dynamic weighting scheme. Initial cluster definitions are accessed. The initial cluster definitions define a plurality of clusters where each cluster includes a plurality of pins. Each cluster is evaluated with respect to one or more design rule constraints. Based on the evaluation, clusters are identified from the plurality of clusters. A set of refinement candidates are generated based on the one or more clusters. A scoring function that employs a dynamic weighting scheme is used to determine a refinement quality score for each refinement candidate in the set of candidates and one or more refinement candidates are selected from among the set of refinement candidates based on respective refinement quality scores. A refined clustering solution is generated based on the selected refinement candidates.

Abstract: The present disclosure provides a bandpass filter based on effective localized surface plasmons (ELSPs) and an operation method thereof. The bandpass filter includes a metal ground plane on a lower portion and a dielectric substrate in a middle as well as microstrips and dielectric resonators on an upper portion, where the microstrips at two terminals are symmetric with each other; each dielectric resonator includes a cuboid dielectric body and two metal strips, where the two metal strips each the same as the cuboid dielectric body in length are respectively located in a middle of an upper surface and lower surface of the dielectric body; and two microstrips are respectively connected to the metal strips on lower surfaces of two dielectric resonators, so as to be used as ports for feeding.

Abstract: Various embodiments provide for clock network generation for a circuit design using an inverting integrated clock gate (ICG). According to some embodiments, a clock network with one or more inverting ICGs is generated, after a topology of the clock network is defined, by applying a non-inverting ICG-to-inverting ICG transform to one or more nodes of the clock network that comprise a non-inverting ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more inverting ICGs.

Abstract: Various embodiments provide for clock network generation for a circuit design using a negative-edge integrated clock gate (ICG). According to some embodiments, a clock network with one or more negative-edge ICGs is generated, after a topology of the clock network is defined, by applying a positive-edge ICG-to-negative-edge ICG transform to one or more nodes of the clock network that comprise a positive-edge ICG. Additionally, according to some embodiments, a clock network is generated bottom-up (from the clock sinks to the root clock signal source) using one or more negative-edge ICGs.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Abstract: The invention discloses a pixel structure and a pixel unit. The pixel structure includes a main electrode; and a plurality of branch electrodes connected to the main electrode; wherein the branch electrode includes a first branch electrode and a second branch electrode, an acute intersecting angle between the first branch electrode and the main electrode is a first angle, and an acute intersecting angle between the second branch electrode and the main electrode is a second angle. The invention solves the whitening phenomenon which occurs in the side view by designing the acute intersecting angle between the branch electrode and the main electrode as the first angle and the second angle.

Abstract: A pixel unit, a display panel and a display device are provided. The pixel unit includes: a first sub-pixel, comprising a first sub-region and a second sub-region; and a second sub-pixel, disposed adjacent to the first sub-pixel and comprising a third sub-region and a fourth sub-region; wherein the first sub-region is disposed adjacent to the third sub-region, and the second sub-region is disposed adjacent to the fourth sub-region; wherein a divided voltage of the first sub-region is same as a divided voltage of the third sub-region; the divided voltage of the first sub-region, a divided voltage of the second sub-region and a divided voltage of the fourth sub-region are different from one another. The pixel unit of the embodiment is advantageous for improving the washout and color shift problem of a larger side view angle and improving the optical characteristics of the viewing angle.

Abstract: Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: A method and apparatus for processing sparse points. The method includes determining spatial hierarchical point data based on a key point set and a local point set of a sparse point set, determining relationship feature data by encoding a spatial hierarchical relationship between points of the spatial hierarchical point data, generating a global feature and a local feature of the sparse point set through a conversion operation associated with the relationship feature data, and generating a processing result for the sparse point set based on the global feature and the local feature.

Abstract: The present disclosure provides a bandpass filter based on effective localized surface plasmons (ELSPs) and an operation method thereof. The bandpass filter includes a metal ground plane on a lower portion and a dielectric substrate in a middle as well as microstrips and dielectric resonators on an upper portion, where the microstrips at two terminals are symmetric with each other; each dielectric resonator includes a cuboid dielectric body and two metal strips, where the two metal strips each the same as the cuboid dielectric body in length are respectively located in a middle of an upper surface and lower surface of the dielectric body; and two microstrips are respectively connected to the metal strips on lower surfaces of two dielectric resonators, so as to be used as ports for feeding.

Abstract: Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Abstract: A data processing method and device, and a computer readable storage medium, the data processing method, applied to a node in an Information-Centric Network (ICN), includes: acquiring a first offset address corresponding to a first ICN packet; querying a record pointed to by the first offset address and performing data processing according to a query result; the record pointed to by the first offset address is used to store a storage address of a second ICN packet or forwarding information of the second ICN packet in response to the second ICN packet corresponding to the first ICN packet being stored locally.

Abstract: A pixel unit, a display panel and a display device are provided. The pixel unit includes: a first sub-pixel, comprising a first sub-region and a second sub-region; and a second sub-pixel, disposed adjacent to the first sub-pixel and comprising a third sub-region and a fourth sub-region; wherein the first sub-region is disposed adjacent to the third sub-region, and the second sub-region is disposed adjacent to the fourth sub-region; wherein a divided voltage of the first sub-region is same as a divided voltage of the third sub-region; the divided voltage of the first sub-region, a divided voltage of the second sub-region and a divided voltage of the fourth sub-region are different from one another. The pixel unit of the embodiment is advantageous for improving the washout and color shift problem of a larger side view angle and improving the optical characteristics of the viewing angle.