Abstract: The present invention discloses a method for driving a pixel matrix, the pixel matrix includes a plurality of sub-pixels arranged in a matrix, the method including: receiving an image data, and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix in a data line direction within one frame. The invention avoids crosstalk, bright and dark lines, and improves the display effect.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: The invention discloses a pixel structure including: a main electrode, and a plurality of branch electrodes connected to the main electrode; wherein closed areas and open areas are formed among the plurality of the branch electrodes. The invention solves the problem that the liquid crystal at the edge position of the peripheral closed design scheme is easily affected by the electric field and the alignment disorder occurs by designing the branch electrode in the ITO electrode as the closed area and the open area, so that the display is uniform and the display effect is improved. Further, with respect to the design of the peripheral opening, the invention reduces the number of black streaks and increases the light transmittance due to the closed areas and the open areas of the interval distribution.

Abstract: Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock-tree wirelength based on target offsets in connected routes. A clock tree comprising routes that interconnect a plurality of clock-tree instances is accessed from memory. A clock-tree instance is selected for evaluation. A baseline power consumption measurement corresponding to a sub-tree of the clock-tree instance with the clock-tree instance at a first size is determined. An alternative power consumption measurement corresponding to the sub-tree of the clock-tree instance with the clock-tree instance at a second size is determined. Based on determining that the baseline power consumption measurement is less than the alternative power consumption measurement, the clock-tree instance is resized according to the second size.

Abstract: An array substrate, a liquid crystal display panel and a display device are provided. The array substrate includes: a substrate; a common electrode and a gate electrode, both disposed on the substrate; and a shielding electrode, disposed on the common electrode and the gate electrode, wherein an orthographic projection of the shielding electrode on the substrate is overlapped with an orthographic projection of the gate electrode on the substrate as well as an orthographic projection of the common electrode on the substrate, and the shielding electrode is electrically connected to the common electrode. In the embodiment of the disclosure, the shielding electrode is disposed on the common electrode and the gate electrode, so that the influence of the voltage difference formed by the gate electrode and the common electrode can be effectively shielded, thereby eliminating the phenomenon of push mura.

Abstract: Aspects of the present disclosure address improved systems and methods for core-route-based clock tree wirelength reduction. A method may include accessing an integrated circuit design comprising a clock tree comprising routes that interconnect terminals of a plurality of clock tree instances. The method further includes identifying a core route in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and the core route and determining a second offset based on a distance from the second terminal to the core route. The method further includes determining a target offset based on a combination of the first and second offsets and moving the clock tree instance toward the core route by the target offset.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

Abstract: Aspects of the present disclosure address systems and methods for shortening clock tree wirelength based on target offsets in connected routes. A method may include accessing a clock tree comprising routes that interconnect a plurality of pins. Each pin corresponds to a terminal of a clock tree instance. The method further includes identifying a first and second terminal of a clock tree instance in the clock tree. The method further includes determining a first offset based on a distance between the first terminal and a branch in a first route connected to the first terminal and determining a second offset based on a distance between the second terminal and a branch in a second route connected to the second terminal. The method further includes moving the clock tree instance from a first location to a second location based on a target offset determined by comparing the first and second offsets.

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design with a source and a plurality of sinks, and then using a first bottom-up wavefront analysis to select branch point candidates for the sinks. A branch point cost function is used to select among the branch point candidates. This process may be repeated until a final tier of analysis results in a final wavefront that is within a threshold distance of the source. The selected branch points are then used in generating a routing tree between the source and the sinks. In various different embodiments, different cost point functions may be used, and different operations used to manage obstructions or other specific routing considerations.

Abstract: Various embodiments provide for circuit design routing based on parallel run length (PRL) rules. In particular, a plurality of PRL rules is accessed and used to generate a set of additional routing blockages around an existing routing blockage of the circuit design. The additional routing blockages can be positioned relative to the existing routing blockage. During routing, the set of additional routing blockages can be modeled into a capacity map, which is then used by global to generate routing guide(s) between at least two nodes of the circuit design. In doing so, the various embodiments can assist in routing a wire while avoiding violation of the plurality of PRL rules with respect to the existing blockage, can speed up performance of global routing, can make it easier for detailed routing to honor routing guides produced by global routing, and can speed up performance of detailed routing in resolving DRC violations.

Abstract: The present invention provides a self-positioning system of a deepwater underwater robot of an irregular dam surface of a reservoir, including cross reflection metal plates arranged on the irregular dam surface, and an underwater robot provided with a control motherboard, a water level indicator and a sonar system, wherein the water level indicator and the sonar system are respectively connected with the control motherboard, and the control motherboard is connected with a computer via a cable. The cross reflection metal plate has known coordinates and has four quadrants. A sonar signal emitted by the sonar system is reflected by the cross reflection metal plate to generate sonar reflection signals of four quadrants, and the sonar signals in the effective quadrants correspond to known coordinate parameters of the cross reflection metal plate so as to obtain the horizontal distance between the underwater robot and the irregular dam surface.

Abstract: Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

Abstract: Electronic design automation systems, methods, and media are presented for view pruning to increase the efficiency of computing operations for analyzing and updating a circuit design for an integrated circuit. One embodiment involves accessing a circuit design stored in memory that is associated with a plurality of views, selecting a first view of the plurality of view for view pruning analysis, and identifying a plurality of input values for the first view of the plurality of views. Random nets are generated based on the views, view inputs, and pruning thresholds. Certain views are then selected as dominant based on a comparison of the output slews different nets and views. Subsequent analysis is then performed and used to update the design without using the pruned views (e.g., using the selected dominant views).

Abstract: Systems, methods, media, and other such embodiments described herein relate to generation of routing trees. One embodiment involves accessing a circuit design comprising an irregular sink arrangement. Different grid templates may be identified for assisting with balanced routings at different levels of a routing tree to connect the sinks of the circuit design. As part of such operations, costs for different routings using the different grid templates are calculated and compared. A lowest cost routing for each grid template are identified. These costs are normalized across different grid templates, and a lowest cost routing across all grid templates is selected. In various embodiments, various costs values based on sink pairing, isolated sinks, and node position for a next level of a routing tree are considered.

Abstract: Aspects of the present disclosure address systems and methods for dynamically adjusting skew windows during clock tree synthesis (CTS). A method may include identifying a pin insertion delay (PID) assigned to a clock sink in a set of clock sinks of a buffer tree in an integrated circuit design. The method further includes determining a skew window for the clock sink based on a skew target and adjusting the skew window based on identifying the PID assigned to the clock sink. The skew window is adjusted based on a skew adjustment parameter. The method further includes building a clock tree based on the buffer tree and the adjusted skew window. The building of the clock tree comprises tuning a clock path delay of the clock sink according to the adjusted skew window. A layout instance may be generated for the IC design based in part on the clock tree.

Abstract: The invention discloses a pixel structure and a pixel unit. The pixel structure includes a main electrode; and a plurality of branch electrodes connected to the main electrode; wherein the branch electrode includes a first branch electrode and a second branch electrode, an acute intersecting angle between the first branch electrode and the main electrode is a first angle, and an acute intersecting angle between the second branch electrode and the main electrode is a second angle. The invention solves the whitening phenomenon which occurs in the side view by designing the acute intersecting angle between the branch electrode and the main electrode as the first angle and the second angle.

Abstract: Various embodiments provide for routing a net of a circuit design using multiple layer ranges. In particular, some embodiments route a net of a circuit design using multiple layer ranges by performing routing of the net over multiple iterations such that at each iteration, a layer bound of a layer range is gradually adjusted (e.g., relaxed) based on wirelength, wire detour, or congestion of a routing result of a prior iteration. For instance, some embodiments may gradually relax a layer bound of the layer range by increasing a layer upper bound or decreasing a layer lower bound.

Abstract: The invention discloses a pixel structure including: a main electrode, and a plurality of branch electrodes connected to the main electrode; wherein closed areas and open areas are formed among the plurality of the branch electrodes. The invention solves the problem that the liquid crystal at the edge position of the peripheral closed design scheme is easily affected by the electric field and the alignment disorder occurs by designing the branch electrode in the ITO electrode as the closed area and the open area, so that the display is uniform and the display effect is improved. Further, with respect to the design of the peripheral opening, the invention reduces the number of black streaks and increases the light transmittance due to the closed areas and the open areas of the interval distribution.