Abstract: A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.

Abstract: The present disclosure, in various embodiments, describes three-dimensional (3D) vertical resistive random access memory (ReRAM) structures. In one embodiment, a memory device includes a resistive memory element and a selector coupled in series with the resistive memory element. A turn-on voltage of the selector is greater than a bias voltage of the memory device in an unselected state such that the selector remains in a turn-off state when the memory device is unselected, and the selector is configured to have substantially the same resistance in both a forward bias direction and a reverse bias direction in a turn-on state.

Abstract: Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Abstract: A first write operation is received. The first write operation includes a SET operation. The SET operation is configured to place a cell of the non-volatile memory (NVM) device in a relatively low-resistance state. A second write operation is received. A first electrical pulse is applied to a first cell of the NVM device. The first electrical pulse is applied to place the first cell in the relatively low-resistance state. A second electrical pulse is applied to a second cell of the NVM device. The second electrical pulse is applied before the first electrical pulse has concluded. The second cell and the first cell are both within a single tile of the NVM device.

Abstract: Aspects of the disclosure provide a method and a data storage apparatus for storing fractional bits per cell with low-latency read per page. In various embodiments, the memory cells are configured to store a fractional number of bits per cell using a multi-page construction with reduced number of read per page as compared to a single page construction. The data storage apparatus store data in a plurality of non-volatile memory (NVM) cells configured to store information in a plurality of pages, wherein each of the NVM cells is programmable to one of L program states for representing a fractional number of bits. The data storage apparatus reads a first part of the data from a first page of the plurality of pages by applying M number of read voltages to the plurality of NVM cells, wherein the M number of read voltages is less than L?1 program states.

Abstract: The present disclosure generally relates to methods of reading data from a memory device using non-binary ECCs. The memory device includes multiple memory cells where each memory cell has multiple pages that are arranged in distinct layouts for physical addresses thereof. When a read request is received from a host device to obtain data from a specific page of a specific memory cell of a memory device, rather than reading the data from all pages of the memory cell, the data can be read from just the desired page and then decoded. Following decoding, the data can be delivered to the host device. Because only the data from a specific page of a memory cell is read, rather than the entire memory cell, the read latency is reduced when compared to reading the entire memory cell.

Abstract: The present disclosure generally relate to a device and method for ensuring error-free memory. Synchronized read and write flags generated by a memory portion are used to make a memory controller of a host portion free from error correction, read/write disturbance, wear leveling and any systematic read/write issues that may occur.

Abstract: In this disclosure, data mapping based on three dimensional lattices that have an improved sum rate (i.e., lifetime capacity) with low read latency is disclosed. During the write, a memory location is written to multiple times prior to erasure. Specifically, for the first write, there are 4/3 bits per cell available for writing, which is about 10.67 kB per cell are used for data storage. Then, for the second write, there is one bit per cell, which is 8 kB per cell for data storage. If considering a block with 128 different cells and writing 32 kB of data, the first write results in 42.66 data writes while the second write results in 32 writes for a total of 74.66 writes. Previously, the number of writes for 32 kB would be 64 writes. Thus, by writing twice prior to erasure, more data can be stored.

Abstract: The present disclosure generally relates to a flash storage system, and more particularly to a scheduler in the flash storage system. The flash storage system includes a device queue, a scheduler coupled to the device queue, and a plurality of dies. In one embodiment, the scheduler pushes commands from the device queue into one or more dies of the plurality of dies for processing in read command phase and write command phase. By separately pushing read commands and write commands into dies for processing, latency is decreased and TOPS is increased.

Abstract: The present disclosure generally relates to a method of burning a file in a memory device after the file has been read. Once a file has been read, an algorithm uses the memory device to create errors that the error correction code (ECC) cannot decode the error. In creating the error, the entire word line is destroyed physically rather than logically so that retrieving information from that particular word line is no longer possible. In creating the error, adjacent word lines are not affected. The error renders the file burned.

Abstract: The present disclosure generally relates to a method for reading and writing data for archival applications in a multiple-level cell memory device. In one embodiment, a method includes operating the multiple-level cell memory device in a single-level cell mode until all blocks are written, changing the single-level cell mode to a first multiple-level cell mode to generate additional space in each block, and operating the multiple-level cell device in the first multiple-level cell mode until all additional space in each block is written. Since the read and write speeds are faster in the single-level cell mode, read and write performances of the multiple-level cell memory device are improved.

Abstract: In general, a controller may perform a self-virtualization technique. The storage device may include storage access comprising multiple cells, and a controller. The controller may determine a maximum amount of storage access for a virtual machine workload when each cell is configured in a first level mode having a maximum allowable number of bits per cell. The controller may configure each cell to be in a second level mode having a number of bits per cell less than the maximum. The controller may determine a total number of bits in use in each cell and compare this total to a threshold number of bits in use in each cell. Based on the comparison, the controller may reconfigure one or more cells to be in a third level mode having a number of bits per cell greater than the number for the second level mode.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Abstract: A storage device includes a cross-point non-volatile memory (NVM) device that includes a first subset of cells. Cells of the first subset of cells may share either a bitline or a wordline. There may be at least one buffer cell on a respective bitline or wordline between each adjacent pair of cells from the first subset of cells. The storage device includes a control module. The control module is configured to receive a set of I/O operations. The control module is configured to execute a first subset of the set of I/O operations in parallel across the first subset of cells of the cross-point memory component. The control module may execute the first subset of the set of I/O operations such that I/O operations are not executed at the respective buffer cells.

Abstract: NAND cell error remediation technologies are disclosed. The remediation technologies are applicable to 3D NAND. In one example, a storage device may include a processor and a memory device comprising NAND flash memory. The processor is configured to detect an error condition associated with a first page of the NAND flash memory, and determine whether the error condition is associated with a read disturbance or with a retention error. The processor is configured to initiate, if the error condition is associated with the read disturbance, a refresh operation with respect to the page to write data stored at the first page to a second page of the NAND flash memory, and initiate, if the error condition is associated with the retention error, a reprogramming operation with respect to the page to rewrite the data stored at the first page to the first page of the NAND flash memory.

Abstract: A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second write operation. The first write operation comprises a SET operation configured to place a cell of the NVM device in a relatively low-resistance state. The control module may be further configured to execute the first write operation by causing an electrical pulse to be applied to a first cell of the NVM device to place the first cell in the relatively low-resistance state. The control module may be further configured to execute the second write operation by causing an electrical pulse to be applied to a second cell of the NVM device before the first electrical pulse has concluded. A single tile of the NVM device includes the first cell and the second cell.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a phase change memory (PCM). The PCM including, first and second phase change memory cells. The PCM including a bitline coupled to the first and the second phase change memory cells. The PCM including a memory controller configured to simultaneously write to the first and the second phase change memory cells by applying designated pulse waveforms to the bitline and wordlines.

Abstract: A storage device may include a data storage portion including a set of blocks designated to store metadata and a controller. The controller may be configured to write first metadata at a first location designated by a first pointer. The first location may reference a block that does not contain any valid metadata. The controller may be configured to determine a number of valid blocks of previously written metadata in a subset of the set of blocks. A first block of the subset may be at a second location designated by a second pointer. The controller may be configured to, if the number of valid blocks is greater than zero, rewrite the valid previously written metadata to a group of one or more sequential blocks.

Abstract: A system includes a bus, at least one processor coupled to the bus, and a storage device coupled to the bus. The storage device includes storage class memory, a buffer; and a controller. The controller is configured to receive an instruction to provide data to the bus. Responsive to receiving the instruction to provide data to the bus, the controller is configured to retrieve data from the storage class memory, update the buffer to represent the data retrieved from the storage class memory, and output, at the bus, an indication that data responsive to the instruction to provide data to the bus is available at the buffer. The at least one processor is configured to refrain from modifying local data corresponding to the instruction to provide data to the bus after the controller receives the instruction to provide data to the bus and before the controller outputs the indication.

Abstract: Embodiments disclosed herein generally relate to an error correction method for non-volatile memory. The error correction method writes data to a first location from a block of user data stored in DRAM. The data written to the first location is verified and errors are identified. Upon determining the number of identified errors exceed a threshold, the block of user data is re-writing to a second location. The data written to the second location is verified and errors are identified. The data written to the first location and the data written to the second location are compared and all discrepancy bits are erased in the comparison. A joint parity check matrix is built with the data written to the first location and the data written to the second location. A code word matrix is built with the comparison. A resultant of the joint parity check matrix and the code word matrix is determined if it is invertible.