Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position.

Abstract: Systems and methods for designating a storage processing unit as a communication hub(s) in a SSD storage system are provided. The storage system can include a host, storage processing units (SPUs), and a host interface to enable communications between host and SPUs. One such method involves receiving a processing task including multiple threads to be performed, determining a baseline configuration for scheduling execution of threads on SPUs and a baseline cost function, marking one SPU as a communication hub, rescheduling, if a thread scheduled for execution on any of the other SPUs is decomposable to multiple sub-threads, a first sub-thread for execution on marked SPU, evaluating a second cost function for performing the processing task, including first sub-thread rescheduled on marked SPU, based on same factors as the baseline cost function, and unmarking, if baseline cost function is less than second cost function, the marked SPU.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: A data storage device may include a non-volatile memory array and a controller. The non-volatile memory array may include a plurality of dies. Each die of the plurality of data dies may include a plurality of words, where a word is an access unit of a die. The controller may be configured to store user data to a respective first word of at least a first die and a second die of the plurality of data dies. A page of user data may include the user data stored at the respective first words of the at least first die and second die. The controller may also be configured to store parity data to a first portion of a first word of a third die. The controller may be further configured to store metadata to a second portion of the first word of the third die.

Abstract: Methods and systems for suppressing the latency in a non-volatile memory are provided. The non-volatile memory can include a flash memory and a storage class memory. The storage class memory can be divided in a first region and a second region. A method for suppressing the latency in the non-volatile memory can determine whether a received host command requires access to the flash memory. When the host command does not require access to the flash memory, the method can further determine whether the host command requires access to the first region or the second region of the storage class memory. The method can suppress the latency in the non-volatile memory by copying valid pages of flash memory blocks into the storage class memory.

Abstract: The present disclosure relates to apparatus, systems, and methods that address the migration of least significant in memory cells due to inter-cell interference (ICI). The disclosed embodiments include a control unit that is configured to characterize the vulnerability of memory cells to ICI, and appropriately encode data stored in the vulnerable memory cells to address ICI. This encoding scheme, referred to as “stuck-at” encoding scheme, can be separate from the generic error correcting code encoding. The stuck-at encoding scheme can decrease the bit error rate of flash memory devices.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.

Abstract: A method and system for accessing a driverless storage device via a byte-addressable protocol. Properly leveraging real-time queue polling between a CPU and Non-Volatile Memory (“NVM”) requires significant, complex, customized software and elaborate device drivers that consume operating systems. The present system maximizes existing host operating systems and memory management hardware and makes the NVM appear as simple memory to a CPU, reducing submission and completion latency and increasing effective bandwidth utilization. In one embodiment, a fast serial protocol translates storage in a target into a byte-addressable memory aperture. The fast serial protocol exposes byte-addressable memory aperture to a memory address range in a host. The host, in communication with a controller, sends a single request for data and receives, from the controller in communication with the storage medium, the data.

Abstract: Methods and systems for performing operations in a communications protocol are provided. A memory controller can retrieve data packets from the memory and send each retrieved data packet to a host, as each data packet is retrieved. The memory controller can retrieve an error correcting code (ECC) packet corresponding to the retrieved data packets and execute an ECC algorithm to identify and correct potential errors in the retrieved plurality of data packets. The memory controller can send any corrected data packets to the host if any of the retrieved data packets had errors and send a completion packet to the host.

Abstract: The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Abstract: Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

Abstract: Embodiments of the present disclosure generally relate to an improved method and system for error correction in non-volatile memory cells. The method includes writing data to a first location in non-volatile memory from a block of user data stored in DRAM and verifying the written data matches the block of user data. If the written data fails verification, the method further includes writing an error location pointer indicative of one or more error locations in the first location to a second location in non-volatile memory. Writing the one or more error locations to the error location pointer includes verifying the written error location pointer matches an address of the one or more error locations in the first location to ensure integrity of the error location pointer. Use of the error location pointer results in non-volatile memory with increased data rate, decreased read latency and a low probability of data loss.

Abstract: Embodiments described herein generally relate to the use of three-dimensional solid state memory structures, both volatile and non-volatile, utilizing a Network-on-Chip routing protocol which provide for the access of memory storage via a router. As such, data may be sent to and/or from memory storage as data packets on the chip. The Network-on-Chip routing protocol may be utilized to interconnect unlimited numbers of three-dimensional memory cell matrices, spread on a die, or multiple dies, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits include a reduction in total density as compared to two-dimensional solid state memory structures utilizing a Network-on-Chip routing protocol, improved signal integrity, larger die areas, improved bandwidths and higher frequencies of operation.

Abstract: Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including determining whether the memory includes a defective memory cell, receiving a message to be written to the memory, sub-dividing the message into a plurality of sub-messages, generating a first error correction code for the sub-messages, the first error correction code being a first type, generating a plurality of second error correction codes for the sub-messages, the second error correction codes being a second type different from the first type, generating a combined message comprising the sub-messages, the first error correction code, and the plurality of second error correction codes, and writing the combined message to the memory, at least a portion of the combined message being written to the defective memory cell.

Abstract: Embodiments disclosed herein generally relate to an error correction method for non-volatile memory. The error correction method writes data to a first location from a block of user data stored in DRAM. The data written to the first location is verified and errors are identified. Upon determining the number of identified errors exceed a threshold, the block of user data is re-writing to a second location. The data written to the second location is verified and errors are identified. The data written to the first location and the data written to the second location are compared and all discrepancy bits are erased in the comparison. A joint parity check matrix is built with the data written to the first location and the data written to the second location. A code word matrix is built with the comparison. A resultant of the joint parity check matrix and the code word matrix is determined if it is invertible.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.