Memory device and method for forming thereof
A semiconductor device includes a plurality of first memory cells in a memory region and a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region. Each of the plurality of the first memory cells includes a static random access memory (SRAM) cell. The static random access memory cell includes a first pull-down transistor and a second pull-down transistor. The plurality of the first memory cells includes a first memory cell. A first source/drain region of the first pull-down transistor in the first memory cell is electrically coupled to a first source/drain region of the first cut-off transistor and a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.
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Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature sizes, which allow more components to be integrated into a given area. However, as the minimum feature sizes are reduced, additional problems arise that should be addressed.
Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. With the increasing speed requirements of integrated circuits, the read speed and write speed of SRAM cells also become more important.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Static random access memory (SRAM) cells are provided in accordance with various embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements formed using like processes. Furthermore, although various embodiments are described in a particular context of SRAM layouts, other embodiments may also be applied to other memory cell configurations, such as read only memory (ROM) cells, dynamic random access memory (DRAM) cells, magnetic random access memory (MRAM) cells, phase change random access memory (PRAM) cells, and resistive random access memory (RRAM) cells.
Embodiments disclosed below may reduce the standby leakage from SRAM circuits. Generally, as the size of SRAM circuit designs continues to shrink, the issue of standby leakage out of SRAM circuits may increase in salience. The majority of the standby leakage out of SRAM circuits comes from subthreshold channel current. For SRAM circuit designs with smaller transistor sizes and lower threshold voltages, it may be difficult to reduce the standby leakage from subthreshold channel current. In order to reduce standby leakage, embodiments may include a switchable high resistance path between the SRAM cell and the power supply voltage Vss. The high resistance path may be one or more transistors formed in dummy regions on the edges of the SRAM arrays electrically interposed between the SRAM cells and the power supply voltage Vss (which may be electrical ground). The transistors in the dummy regions may function as resistors when in standby mode, thereby limiting or reducing the leakage current, and pass current in a low resistance state when in an active mode. In some embodiments, standby current can be reduced by, for example, about 70% in comparison to a design without transistors in the dummy regions connecting to Vss. Embodiments of SRAM array designs with transistors in the dummy regions may achieve better results without impacting read/write ability due to shorter bit-line loading from a smaller array size achieved by taking advantage of the dummy regions.
The SRAM array 1000 is formed on a substrate which may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate may be a wafer, such as a silicon wafer or a single die (e.g., processed in a wafer and then removed from other devices of the wafer using a singulation process).
Referring now to
The sources of PU transistors T3 and T4 are connected to CVdd node 302 and CVdd node 304, respectively, which are further connected to power supply voltage (and line) Vdd. The sources of PD transistors T1 and T2 are connected to CVss node 306 and CVss node 308, respectively, which are further connected to power supply voltage/line Vss. The gates of transistors T3 and T1 are connected to the drains of transistors T4 and T2, which form a connection node that is referred to as SD node 310. The gates of transistors T4 and T2 are connected to the drains of transistors T3 and T1, which connection node is referred to as SD node 312. A source/drain region of PG transistor T5 is connected to bit line BLB 316 at a BLB node 320. A source/drain region of PG transistor T6 is connected to bit line BL 314 at a BL node 318.
Referring now to
Referring now to
Referring now to
Referring first to
Still referring to
Further referring to
As further illustrated by
In the dummy region 150, gate electrode 56b forms the cut-off transistor T7 with the active region 62b, which may be two or more fins such as fins 62b. Because the cut-off transistor T7 is located in the dummy region 150 of the SRAM array 1000, the cut-off transistor T7 may not need additional process steps to create or area to occupy in comparison with a design not including the cut-off transistor T7.
In accordance with some embodiments of the present disclosure, PD transistors T1 and T2, PU transistors T3 and T4, PG transistors T5 and T6, and cut-off transistor T7 are Fin Field-Effect Transistors (FinFETs) as described above where active regions 64 and 66a are single fins and active regions 62b and 62c comprise multiple fins. Active regions 62b, 62c, 64, and 66a provide source/drains of various transistors on opposing sides of a respective gate electrode.
SD node 312 includes source/drain contact 70B and gate contact 72B. Gate contact 72B has a portion overlapping source/drain contact 70B. Since SD node 310 may be symmetric to SD node 312, the details of gate contact 72B and source/drain contact 70B may be similar to gate contact 72A and source/drain contact 70A, respectively, and are not repeated herein for simplicity.
Furthermore, elongated contacts 70C are used to connect to the source regions of PD transistors T1 and T2 to a CVss line (e.g., an electrical ground line) through cut-off transistor T7. Elongated contacts 70C have lengthwise directions parallel to the X direction, and may be formed to overlap the edges of SRAM cell 20. Furthermore, elongated contacts 70C may further extend into neighboring SRAM cells in a different column that abut SRAM cell 20. Elongated contacts 70C may further be shared between two neighboring SRAM cells in different rows that abut each other. Additionally, contacts 70D are used to connect to the source regions of PU transistors T3 and T4 to CVdd lines (e.g., supply voltage lines). Contacts 70D are parts of the CVdd nodes 302 and 304 (see also
As further illustrated by
As shown in
Additionally, vias 76C are connected to contacts 70D (e.g., source contacts of PU transistors T3 and T4). Vias 76C will subsequently be connected to a CVdd line, which electrically connects sources of PU transistors T3 and T4 to CVdd, as illustrated below in
As further illustrated by
Still referring to
As shown in
As further shown in
In some embodiments, vias 94 are connected to multiple conductive lines 98 that are connected to each other through higher vias and conductive lines in, for example, the via_3 and M4 levels (see
Referring first to
In the dummy region 150, gate electrode 56b forms the additional cut-off transistor T7 with the active region 62b, which may be two or more fins such as fins 62b, and gate electrode 58c forms the additional cut-off transistor T8 with the active region 62c, which may be two or more fins such as fins 62c. Because the additional cut-off transistors T7 and T8 are located in the dummy region 150 of the SRAM array 1000, the additional cut-off transistors T7 and T8 may not need additional process steps to create or area to occupy in comparison with a design not including the additional cut-off transistors T7 and T8.
In accordance with some embodiments of the present disclosure, PD transistors T1 and T2, PU transistors T3 and T4, PG transistors T5 and T6, and additional transistors T7 and T8 are Fin Field-Effect Transistors (FinFETs) as described above where active regions 64 and 66a are single fins and active regions 62b and 62c comprise multiple fins. Active regions 62b, 62c, 64, and 66a provide source/drains of various transistors on opposing sides of a respective gate electrode.
SD node 312 includes source/drain contact 70B and gate contact 72B. Gate contact 72B has a portion overlapping source/drain contact 70B. Since SD node 310 may be symmetric to SD node 312, the details of gate contact 72B and source/drain contact 70B may be similar to gate contact 72A and source/drain contact 70A, respectively, and are not repeated herein for simplicity.
Furthermore, the elongated contact 70C is used to connect the source region of PD transistor T1 to a CVss line (e.g., an electrical ground line) through transistor T7. The leakage path of the source region of the transistor T1 to Vss through the transistor T1 may reduce the standby leakage of the SRAM cell 30 when the transistor T1 is in standby mode and functioning as a resistance. The elongated contact 70C has a lengthwise direction parallel to the X direction, and may be formed to overlap the edges of SRAM cell 30. Furthermore, the elongated contact 70C may further extend into a neighboring SRAM cell in a different column that abuts SRAM cell 30. The elongated contact 70C may further be shared between two neighboring SRAM cells in different rows that abut each other. Additionally, contacts 70D are used to connect to the source regions of PU transistors T3 and T4 to CVdd lines (e.g., supply voltage lines). Contacts 70D are parts of the CVdd nodes 302 and 304 (see also
As further illustrated by
Still referring to
As shown in
Additionally, vias 76C are connected to contacts 70D (e.g., source contacts of PU transistors T3 and T4). Vias 76C will subsequently be connected to a CVdd line, which electrically connects sources of PU transistors T3 and T4 to CVdd, as illustrated below in
As further illustrated by
Still referring to
As shown in
As further shown in
In some embodiments, vias 94 are connected to multiple conductive lines 98 that are connected to each other through higher vias and conductive lines in the via_3 and M4 levels (see
Embodiments of the memory circuits disclosed above may achieve advantages, including reducing the standby leakage from SRAM circuits. Transistors may be formed in dummy regions on the edges of SRAM arrays and used to SRAM cells to power supply voltages Vss (which may be electrical grounds), which may reduce standby leakage efficiently without using additional chip area or process steps. The transistors in the dummy regions may be seen as resistances when cut off by the controlling word lines. Standby leakage of SRAM circuits in the interior of the SRAM array to Vss through the transistors in the dummy regions may be reduced by about 70% in comparison to a design without transistors in the dummy regions connecting to Vss. Embodiments of SRAM array designs with transistors in the dummy regions may achieve better results without impacting read/write ability due to shorter bit-line loading.
In accordance with an embodiment, a semiconductor device includes: a plurality of first memory cells in a memory region, each of the plurality of the first memory cells including a static random access memory (SRAM) cell, the static random access memory cell including a first pull-down transistor and a second pull-down transistor, the plurality of the first memory cells including a first memory cell; and a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region, a first source/drain region of the first pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the first cut-off transistor, wherein a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage. In an embodiment, the power supply voltage is ground. In an embodiment, a first source/drain region of the second pull-down transistor is electrically coupled to the first source/drain region of the cut-off transistor. In an embodiment, a gate electrode of the first cut-off transistor is electrically coupled to a word line. In an embodiment, the semiconductor device further includes: a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage. In an embodiment, a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line. In an embodiment, the plurality of first memory cells includes a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, wherein the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor. In an embodiment, the plurality of first memory cells includes a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, further including: a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the second memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage. In an embodiment, a gate electrode of the first cut-off transistor and the second cut-off transistor are coupled to a same control line.
In accordance with another embodiment, a semiconductor device includes: a first memory cell in a memory array, the first memory cell including a static random access memory (SRAM) cell having a first pull-down transistor and a second pull-down transistor; a dummy region along a boundary of the memory array; a first cut-off transistor in the dummy region, the first cut-off transistor having a first source/drain electrically coupled to a first source/drain of the first pull-down transistor and a second source/drain electrically coupled to ground; and a well pick-up region adjacent the dummy region, wherein the dummy region is interposed between the well pick-up region and the memory array. In an embodiment, the first memory cell is a closest memory cell of memory cells connected to a same bit line to the dummy region. In an embodiment, the semiconductor device further includes: a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein the first cut-off transistor is not electrically interposed between the second memory cell and ground. In an embodiment, the semiconductor device of further includes: a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first cut-off transistor. In an embodiment, a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line. In an embodiment, the semiconductor device further includes: a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor and having a second source/drain electrically coupled to ground. In an embodiment, a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line. In an embodiment, the semiconductor further includes: a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor; and a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor of the first memory cell and to a first source/drain of the second pull-down transistor of the second memory cell, the second cut-off transistor having a second source/drain electrically coupled to ground. In an embodiment, a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line.
In accordance with yet another embodiment, a method of forming a semiconductor device includes forming a memory cell in a memory array, including: forming a first pull-down transistor and a second pull-down transistor in a memory region of the memory array; forming a first cut-off transistor in a dummy region of the memory array; electrically connecting a first source/drain of the first cut-off transistor to a source/drain of the first pull-down transistor; and electrically connecting a second source/drain of the first cut-off transistor to a power supply voltage. In an embodiment, the method further includes: forming a second cut-off transistor in the dummy region of the memory array; electrically connecting a first source/drain of the second cut-off transistor to a source/drain of the second pull-down transistor; and electrically connecting a second source/drain of the second cut-off transistor to the power supply voltage.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A semiconductor device comprising:
- a plurality of first memory cells in a memory region, each of the plurality of the first memory cells comprising a static random access memory (SRAM) cell, the static random access memory cell comprising a first pull-down transistor and a second pull-down transistor, the plurality of the first memory cells comprising a first memory cell; and
- a first cut-off transistor in a dummy region, the dummy region being adjacent to the memory region, a first source/drain region of the first pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the first cut-off transistor, wherein a second source/drain region of the first cut-off transistor is electrically coupled to a power supply voltage.
2. The semiconductor device of claim 1, wherein the power supply voltage is ground.
3. The semiconductor device of claim 1, wherein a first source/drain region of the second pull-down transistor is electrically coupled to the first source/drain region of the first cut-off transistor.
4. The semiconductor device of claim 1, wherein a gate electrode of the first cut-off transistor is electrically coupled to a word line.
5. The semiconductor device of claim 1 further comprising:
- a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the first memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage.
6. The semiconductor device of claim 5, wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line.
7. The semiconductor device of claim 1, wherein the plurality of first memory cells comprises a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, wherein the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor.
8. The semiconductor device of claim 1, wherein the plurality of first memory cells comprises a second memory cell, the first memory cell and the second memory cell being electrically coupled to a same bit line, further comprising:
- a second cut-off transistor in the dummy region, a first source/drain region of the second pull-down transistor in the second memory cell being electrically coupled to a first source/drain region of the second cut-off transistor, wherein a second source/drain region of the second cut-off transistor is electrically coupled to the power supply voltage.
9. The semiconductor device of claim 8, wherein a gate electrode of the first cut-off transistor and the second cut-off transistor are coupled to a same control line.
10. A semiconductor device comprising:
- a first memory cell in a memory array, the first memory cell comprising a static random access memory (SRAM) cell having a first pull-down transistor and a second pull-down transistor;
- a dummy region along a boundary of the memory array;
- a first cut-off transistor in the dummy region, the first cut-off transistor having a first source/drain electrically coupled to a first source/drain of the first pull-down transistor and a second source/drain electrically coupled to ground; and
- a well pick-up region adjacent the dummy region, wherein the dummy region is interposed between the well pick-up region and the memory array.
11. The semiconductor device of claim 10, wherein the first memory cell is a closest memory cell of memory cells connected to a same bit line to the dummy region.
12. The semiconductor device of claim 10 further comprising:
- a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein the first cut-off transistor is not electrically interposed between the second memory cell and ground.
13. The semiconductor device of claim 10 further comprising:
- a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first cut-off transistor.
14. The semiconductor device of claim 13, wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line.
15. The semiconductor device of claim 10 further comprising:
- a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor and having a second source/drain electrically coupled to ground.
16. The semiconductor device of claim 15, wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a word line.
17. The semiconductor device of claim 10 further comprising:
- a second memory cell in the memory array, wherein the first memory cell and the second memory cell are electrically coupled to a same bit line, wherein a first source/drain of the first pull-down transistor of the second memory cell is electrically coupled to the first source/drain of the first cut-off transistor; and
- a second cut-off transistor, the second cut-off transistor having a first source/drain electrically coupled to a first source/drain of the second pull-down transistor of the first memory cell and to a first source/drain of the second pull-down transistor of the second memory cell, the second cut-off transistor having a second source/drain electrically coupled to ground.
18. The semiconductor device of claim 17, wherein a gate electrode of the first cut-off transistor and a gate electrode of the second cut-off transistor are electrically coupled to a control line different than a word line.
19. A method of forming a semiconductor device, the method comprising:
- forming a memory cell in a memory array, comprising: forming a first pull-down transistor and a second pull-down transistor in a memory region of the memory array; forming a first cut-off transistor in a dummy region of the memory array; electrically connecting a first source/drain of the first cut-off transistor to a source/drain of the first pull-down transistor; and electrically connecting a second source/drain of the first cut-off transistor to a power supply voltage.
20. The method of claim 19 further comprising:
- forming a second cut-off transistor in the dummy region of the memory array;
- electrically connecting a first source/drain of the second cut-off transistor to a source/drain of the second pull-down transistor; and
- electrically connecting a second source/drain of the second cut-off transistor to the power supply voltage.
8605523 | December 10, 2013 | Tao et al. |
8630132 | January 14, 2014 | Cheng et al. |
8760948 | June 24, 2014 | Tao et al. |
9455028 | September 27, 2016 | Sahu |
10468418 | November 5, 2019 | Chen |
20090067220 | March 12, 2009 | Asayama |
20140032871 | January 30, 2014 | Hsu et al. |
20140153321 | June 5, 2014 | Liaw |
20140153345 | June 5, 2014 | Kim et al. |
20140177352 | June 26, 2014 | Lum |
20140233330 | August 21, 2014 | Ko et al. |
20140241077 | August 28, 2014 | Katoch et al. |
20140269114 | September 18, 2014 | Yang et al. |
20160306910 | October 20, 2016 | Tseng |
20170110182 | April 20, 2017 | Liaw |
20170221552 | August 3, 2017 | Liaw |
20180151553 | May 31, 2018 | Liaw |
20180175046 | June 21, 2018 | Chiou |
20190066773 | February 28, 2019 | Park |
20200027869 | January 23, 2020 | Yeh |
Type: Grant
Filed: Jul 29, 2020
Date of Patent: Feb 22, 2022
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd. (Hsinchu)
Inventor: Chih-Chuan Yang (Hsinchu)
Primary Examiner: Karen Kusumakar
Assistant Examiner: Adam S Bowen
Application Number: 16/941,784
International Classification: H01L 27/11 (20060101); H01L 27/092 (20060101); H01L 23/528 (20060101);