Buffer circuit with adaptive repair capability
A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
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This application is a Continuation application of U.S. application Ser. No. 16/537,021, filed Aug. 9, 2019, titled “BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY”, now U.S. Pat. No. 11,069,423, which issued on Jul. 20, 2021, which is a Continuation application of U.S. application Ser. No. 15/506,621, filed Feb. 24, 2017, titled “BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY”, now U.S. Pat. No. 10,388,396, which issued on Aug. 19, 2019, which is a national stage application of international application number PCT/US2015/045495, filed Aug. 17, 2015, which claims the benefit of U.S. Provisional Application No. 62/041,489, filed Aug. 25, 2014, all of which are incorporated by reference herein in their entireties.
TECHNICAL FIELDThe disclosure herein relates to memory systems, and more specifically to on-module memory repair apparatus and methods.
BACKGROUNDMemory modules come in a variety of configurations depending on a given application and desired storage capacity. For high-capacity memory modules that employ significant numbers of memory devices, a buffered architecture is often employed. The buffered approach buffers data transferred between the memory devices and a memory controller, thus reducing loading of a data bus to the relatively few buffer devices, rather than the high number of memory devices. Address and control busses are also typically buffered in these systems.
Employing increasing numbers of memory devices on conventional high-capacity memory modules exposes the overall memory to a cumulative yield problem. A significant percentage of conventional memory modules may develop permanent failures at the memory device level after operating in the field for a relatively short duration. Replacing individual devices on a module is generally impractical, resulting in an entire module replacement if the number of failures significantly impact the performance or capacity of the overall memory.
Embodiments of the disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
Embodiments of integrated circuits, memory modules and associated methods are disclosed herein. One embodiment of a buffer circuit for a memory includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. The ACT command includes incoming row address information for a given data transfer involving the memory and the CAS command includes incoming column address information for the data transfer. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic. Employing multiple match circuits in this manner enables an efficient way to search incoming address information against known defective storage locations with minimal storage resources in the match circuits. This allows redirecting data associated with a defective storage location to a repair resource in the buffer circuit. The buffer circuit thus provides repair capability while operating in the field, thereby minimizing wholesale memory module replacements for failures at the memory device level.
In a further embodiment, a method of operation in a buffer circuit is disclosed. The method includes receiving an incoming activate (ACT) command and an incoming column address strobe (CAS) command. The ACT command includes incoming row address information for a given data transfer involving the memory and the CAS command includes incoming column address information for the data transfer. Failure row address information associated with the memory is stored in a first match circuit. The incoming row address information is compared to the stored failure row address information in response to the ACT command, to generate row match information. Failure column address information associated with the memory is stored in a second match circuit. The incoming column address information is compared to the stored failure column address information in response to the CAS command. A state of a matching row address identified in the generated row match information is maintained during the second comparing.
In yet another embodiment, a memory module is disclosed. The memory module includes a substrate, and multiple memory devices disposed on the substrate. Buffer circuitry is disposed on the substrate and is coupled to the memory devices. The buffer circuitry includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. The ACT command includes incoming row address information for a given data transfer involving the memory and the CAS command includes incoming column address information for the data transfer. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
Referring to
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With continued reference to
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For one specific embodiment, the first CAM 402 may be organized to receive DRAM Activate (ACT) commands that include DRAM rank, bank and row address information. Entries in the first CAM (here, 64 entries are shown, but the number may be more or less depending on available storage resources) may store DRAM rank, bank and row addresses of known memory device failure locations at respective fields 404, 406, and 408. A index field, at 410, for each entry indicates the CAM's output address information when an input matches one or more of the stored CAM entries (e.g., if an input matches the value stored at index=3, then the 3rd output signal will be asserted). For some embodiments, a first-in-first-out (FIFO) circuit may receive multiple ACT commands in sequence, thus delaying the ACT command processing by a programmable period before receipt by the first CAM 402.
Further referring to
With continued reference to
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With continued reference to
To tolerate the highly variable latency interval between receipt of the ACT command and the time associated with the propagation and matching of the CAS column information, at step 510, the states of the first matching circuit's comparison output are maintained in the latch. Upon receipt of a rank/bank signals that accompany the CAS command, the appropriate bitmask of rank/bank/row information is read from the latch and fed to the AND logic. At the same time, the bitmask of column information is also fed to the AND logic. In the event the bitmasks reflect failure information, the two bitmasks are then gated, combined, and encoded, at step 512, to generate a substitute address location. Substitute storage at the generated address may then be accessed to carry out the given data transfer, at step 514.
Further referring to
An additional embodiment of the C/A buffer circuit is shown in
Further referring to
A further variation of the C/A buffer circuit 1100 may employ logic, similar to that shown in
Those skilled in the art will appreciate that the embodiments described above provide adaptive in situ repair capabilities for buffered memory systems. Utilizing multiple match circuits in the C/A buffer circuit provides an efficient repair search capability for incoming addresses that minimizes the amount of CAM/tag storage in the C/A buffer circuit. Additionally, by repairing failed storage locations at the nibble level, on-die SRAM in the data buffer circuits may be minimized while still providing sufficient repair capabilities.
When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.
In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘
While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims
1. A data buffer integrated circuit (IC) chip, comprising:
- a primary data interface for coupling to a memory controller, the primary data interface to transfer data with the memory controller for a given data transfer operation;
- a secondary interface for coupling to at least one memory device;
- on-chip memory having substitute storage locations to store data for known failure locations of the at least one memory device; and
- match circuitry to access the substitute storage locations based on a match of incoming failure address information to the known failure locations.
2. The data buffer IC chip according to claim 1, wherein ones of the substitute storage locations are configured to store a sub-burst of data bits.
3. The data buffer IC chip according to claim 2, wherein the sub-burst of data bits comprises a nibble of data bits.
4. The data buffer IC chip according to claim 2, wherein the on-chip memory is further configured to store a state bit for each of the substitute storage locations, the state bit indicating whether or not a corresponding substitute storage location has been accessed by a prior write operation; and
- wherein a read access to a given substitute storage location is constrained based on the value of a given state bit corresponding to the given substitute storage location.
5. The data buffer IC chip according to claim 1, wherein the on-chip memory comprises static random access memory (SRAM) memory.
6. The data buffer IC chip according to claim 5, further comprising:
- a broadcast communications (BCOM) interface to receive the incoming failure address information from a command/address (C/A) buffer integrated circuit chip.
7. The data buffer IC chip according to claim 6, wherein the match circuitry comprises:
- a content-addressable memory (CAM) to compare the incoming failure address information from the C/A buffer IC chip to known failure addresses stored in respective CAM entries, wherein a match condition for a given one of the respective CAM entries generates a signal to access a storage location of the on-chip memory corresponding to the matching failure address entry of the CAM.
8. A buffer chipset for a memory module, comprising:
- a command/address (C/A) buffer integrated circuit (IC) chip having a primary C/A interface for coupling to a memory controller, and a secondary C/A interface for coupling to at least one memory device, the C/A buffer IC chip to generate failure address locations in the at least one memory device;
- at least one data buffer IC chip to receive the failure address locations from the C/A buffer IC chip, wherein the at least one data buffer IC chip comprises a primary data interface for coupling to a memory controller, the primary data interface to transfer data with the memory controller for a given data transfer operation; a secondary interface for coupling to the at least one memory device; on-chip memory having substitute storage locations to store data for the failure address locations of the at least one memory device; and match circuitry to access the substitute storage locations for data transfers associated with the failure address locations.
9. The buffer chipset of claim 8, wherein ones of the substitute storage locations are configured to store a sub-burst of data bits.
10. The buffer chipset of claim 9, wherein the sub-burst of data bits comprises a nibble of data bits.
11. The buffer chipset of claim 9, wherein the on-chip memory is further configured to store a state bit for each of the substitute storage locations, the state bit indicating whether or not a corresponding substitute storage location has been accessed by a prior write operation; and
- wherein a read access to a given substitute storage location is constrained based on the value of a given state bit corresponding to the given substitute storage location.
12. The buffer chipset of claim 8, wherein the on-chip memory comprises static random access memory (SRAM) memory.
13. The buffer chipset of claim 12, further comprising:
- a broadcast communications (BCOM) interface to receive failure address information from a command/address (C/A) buffer integrated circuit chip.
14. The buffer chipset of claim 13, wherein the match circuitry comprises:
- a content-addressable memory (CAM) to compare the received failure address information from the C/A buffer IC chip to known failure addresses stored in respective CAM entries, wherein a match condition for a given one of the respective CAM entries generates a signal to access a storage location of the on-chip memory corresponding to the matching failure address entry of the CAM.
15. A memory module comprising:
- a substrate;
- multiple memory devices disposed on the substrate; and
- buffer circuitry disposed on the substrate and coupled to the memory devices, the buffer circuitry comprising a primary data interface for coupling to a memory controller, the primary data interface to transfer data with the memory controller for a given data transfer operation; a secondary interface for coupling to the multiple memory devices; on-chip memory having substitute storage locations to store data for failure address locations of at least one of the multiple memory devices; and match circuitry to access the substitute storage locations for data transfers associated with the failure address locations.
16. The memory module according to claim 15, wherein the buffer circuitry comprises:
- at least one data buffer integrated circuit (IC) chip.
17. The memory module according to claim 15, further comprising:
- a command/address (C/A) buffer IC chip coupled to the at least one data buffer IC chip via a broadcast communications (BCOM) bus, the command/address (C/A) buffer integrated circuit (IC) chip having a primary C/A interface for coupling to a memory controller, and a secondary C/A interface for coupling to at least one memory device, the C/A buffer IC chip to generate failure address locations in the at least one memory device.
18. The memory module according to claim 15, wherein ones of the substitute storage locations are configured to store a sub-burst of data bits.
19. The memory module according to claim 18, wherein the sub-burst of data bits comprises a nibble of data bits.
20. The memory module according to claim 18, wherein the on-chip memory is further configured to store a state bit for each of the substitute storage locations, the state bit indicating whether or not a corresponding substitute storage location has been accessed by a prior write operation; and
- wherein a read access to a given substitute storage location is constrained based on the value of a given state bit corresponding to the given substitute storage location.
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Type: Grant
Filed: Jul 6, 2021
Date of Patent: Dec 13, 2022
Patent Publication Number: 20220005542
Assignee: Rambus Inc. (San jose, CA)
Inventors: Scott C. Best (Palo Alto, CA), John Eric Linstadt (Palo Alto, CA), Paul William Roukema (Waterloo)
Primary Examiner: Esaw T Abraham
Application Number: 17/368,018
International Classification: G11C 29/00 (20060101); G11C 29/44 (20060101); G11C 5/04 (20060101); G11C 11/401 (20060101); G11C 29/02 (20060101); G11C 29/52 (20060101);