Abstract: The present application provides a method for process a substrate. The method includes steps of providing a substrate having a sacrificial layer and an insulative layer, forming a polysilicon hardmask on the insulative layer, etching the insulative and sacrificial layers through multiple openings in the polysilicon hardmask to thus form multiple channels, depositing a metal film and a passivation film on the polysilicon hardmask and in the channels, performing a first removal process to remove portions of the passivation film and the metal film above the polysilicon hardmask, performing a second removal process to remove portions of the polysilicon hardmask exposed through the passivation film and the metal film, and performing a third removal process to remove the polysilicon hardmask and portions of the passivation film and the metal film surrounding the polysilicon is hardmask.

Abstract: A substrate processing system includes a hinge assembly configured to allow a substrate support and an RF bias assembly to slide, from a docked position to an undocked position, relative to other components of a processing chamber. A make-break connector is configured to supply fluid to at least one of the substrate support and the RF bias assembly. The make-break connector includes a first portion including a first fluid passage connected to a first conduit. A second portion includes a second fluid passage connected to a second conduit. The first fluid passage in the first portion fluidly communicates with the second fluid passage in the second portion. The first portion is configured to slide with the substrate support and the RF bias assembly relative to the second portion and the other portions of the processing chamber. The first portion is located inwardly relative to the second portion.

Abstract: Exemplary semiconductor processing systems may include a pumping system, a chamber body that defines a processing region, and a pumping liner disposed within the processing region. The pumping liner may define an annular member characterized by a wall that defines an exhaust aperture coupled to the pumping system. The annular member may be characterized by an inner wall that defines a plurality of apertures distributed circumferentially along the inner wall. A plenum may be defined in the annular member between interior surfaces of the walls. A divider may be disposed within the plenum, where the divider separates the plenum into a first plenum chamber and a second plenum chamber, wherein the first plenum chamber is fluidly accessible from the apertures defined through the inner wall, and wherein the divider defines at least one aperture providing fluid access between the first plenum chamber and the second plenum chamber.

Abstract: A baffle unit includes an inner ring, an outer ring disposed outside the inner ring, and a connecting portion connecting the inner ring with the outer ring. The connecting portion includes multiple openings arranged in a radial direction of the baffle unit and in a circumferential direction of the baffle unit, each of the multiple openings being arcuate and extending in the circumferential direction; multiple rigid portions each being disposed between the adjacent openings of the multiple openings that are adjacent to each other on a same concentric circle of the baffle unit; and multiple walls each being formed between the adjacent openings of the multiple openings that are adjacent to each other in the radial direction. Each of the multiple walls connects a rigid portion of the multiple rigid portions with another rigid portion of the multiple rigid portions.

Abstract: A stage apparatus including: an object table configured to hold an object; a positioning device configured to position the object table and the object held by the object table; and a remote temperature sensor configured to measure a temperature of the object table and/or the object, wherein the remote temperature sensor comprises a passive temperature sensing element.

Abstract: A physical vapor deposition (PVD) chamber and a method of operation thereof are disclosed. Chambers and methods are described that provide a chamber comprising a deposition ring assembly comprising an inner and outer deposition ring which reduces particle defects.

Abstract: A substrate support assembly suitable for use in a reactor including a common processing and substrate transfer region is disclosed. The substrate support assembly includes a susceptor and one or more lift pins that can be used to lower a substrate onto a surface of the susceptor and raise the substrate from the surface, to allow transfer of the substrate from the processing region, without raising or lowering the susceptor.

Abstract: A semiconductor-manufacturing apparatus member includes a ceramic plate having an upper surface serving as a wafer placement surface, a plug disposed in an undersurface of the ceramic plate and including a dense body and a gas flow channel that extends through the body in a thickness direction of the body while winding, a gas outlet port that extends through the ceramic plate in a thickness direction of the ceramic plate to be connected to an upper portion of the gas flow channel, and a metal cooling plate joined to the undersurface of the ceramic plate, and including a gas supply channel through which gas is supplied from a lower portion of the gas flow channel. In the plug, at least a portion in length of the gas flow channel is formed from a porous member.

Abstract: Semiconductor substrate support assemblies may include an electrostatic chuck body having a substrate support surface. The electrostatic chuck body may define a plurality of protrusions extending from the substrate support surface. The assemblies may include an electrode embedded within the electrostatic chuck body. The electrode may define apertures through the electrode in line with the plurality of protrusions extending from the substrate support surface.

Abstract: An edge ring arrangement for a processing chamber includes a first ring configured to surround and overlap a radially outer edge of an upper plate of a pedestal arranged in the processing chamber, a second ring arranged below the first moveable ring, wherein a portion of the first ring overlaps the second ring, a first actuator configured to actuate a first pillar to selectively move the first ring to a raised position and a lowered position relative to the pedestal, and a second actuator configured to actuate a second pillar to selectively move the second ring to a raised position and a lowered position relative to the pedestal.

Abstract: A temperature regulator includes a first member, a channel, and a cavity. The first member has a first surface that is subjected to temperature control. The channel is along the first surface in the first member, and refrigerant flows in the channel. The cavity is provided in the first member adjacently to a flow rate change region of the channel. A flow rate of refrigerant in the flow rate change region is higher than a flow rate of refrigerant in another region of the channel.

Abstract: To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Abstract: A lift pin assembly for a lift pin of a plasma processing apparatus is provided. The lift pin assembly includes a pin housing defining an opening into which a lift pin extends. The pin housing is positioned such that the opening is aligned with an opening defined by an electrostatic chuck. The assembly includes a pin height adjustment member partially positioned within the opening defined by the pin housing. The pin height adjustment member is movable along an axis in a first direction and a second direction to move the lift pin into and out of the opening defined by the electrostatic chuck. The assembly includes a pin holder assembly at least partially positioned within an opening defined by the pin height adjustment member. The pin holder assembly is configured to hold the lift pin such that the lift pin is aligned with the opening defined by the electrostatic chuck.

Abstract: A vapor phase epitaxial growth device comprises a reactor vessel and a wafer holder arranged within the reactor vessel. The wafer holder includes a wafer holding surface configured to hold a wafer with a wafer surface oriented substantially vertically downward. The device comprises a first material gas supply pipe configured to supply a first material gas and arranged below the wafer holding surface. The device comprises a second material gas supply pipe configured to supply a second material gas and arranged below the wafer holding surface. The device comprises a gas exhaust pipe configured to exhaust gases and arranged below the wafer holding surface. A distance between the gas exhaust pipe and an axis line passing through a center of the wafer holding surface is greater than distances between the axis line and each of the first material gas supply pipe and the second material gas supply pipe.

Abstract: The present application relates to a semiconductor equipment regulation method, including: providing a simulated wafer; placing the simulated wafer in an etching chamber, and conditioning a temperature in the chamber by using a temperature control device while the simulated wafer is etched by using an etching gas; during the etching process, forming a polymer layer on a surface of each etch hole; acquiring a thickness distribution map of the polymer layer in the entire simulated wafer; comparing the acquired thickness distribution map with a target thickness distribution map; and adjusting a temperature control effect through using the temperature control device on each region of the simulated wafer according to a result of the comparison, so as to adjust thickness uniformity of the polymer layer in the entire wafer.

Abstract: Provided is a cooling device capable of controlling the temperature of an upper portion of a reactor, or more particularly, a gas supply device, for example, a shower head. The cooling device includes a separator configured to uniformly and efficiently cool the gas supply device.

Abstract: Various embodiments include an apparatus to retrofit into an electrostatic chuck (ESC) of an existing plasma-based processing system. The apparatus includes a tube adapter portion having a dielectric coating formed on an inner surface of the tube adapter portion to prevent arcing between high voltage electrodes within the tube adapter portion and a main body of the tube adapter portion during an operation of the plasma-based processing system, a number of insulative tubes with the high voltage electrodes to be enclosed therein, and an enlarged gap portion of the tube adapter portion proximate outboard ones of the plurality of insulative tubes to prevent arcing. Other methods of forming the ESC, and related devices, apparatuses, and systems are disclosed.

Abstract: The present disclosure is related to a substrate processing apparatus. The substrate processing apparatus may include a chuck including a plurality of pin holes and a plurality of lift pins positioned to rise and fall through the plurality of pin holes. The substrate processing apparatus may include a lift plate configured to raise and lower the lift pins. The plurality of lift pins may include a lift pin having a rod shape configured to move up and down in a pin hole of the plurality of pin holes, a flexure coupled to a lower portion of the lift pin, a weight body positioned underneath the lift plate, and a weight string connecting the flexure and the weight body. The lift plate may include a string hole through which the weight string passes through.

Abstract: Embodiments of the disclosure generally relate to a semiconductor processing chamber. In one embodiment, semiconductor processing chamber is disclosed and includes a chamber body having a bottom and a sidewall defining an interior volume, the sidewall having a substrate transfer port formed therein, and one or more absorber bodies positioned in the interior volume in a position opposite of the substrate transfer port.

Abstract: Embodiments of the disclosure include methods and apparatus for electrostatically coupling a mask to a substrate support in a deposition chamber. In one embodiment, a substrate support is disclosed that includes a substrate receiving surface, a recessed portion disposed about a periphery of the substrate receiving surface, an electrostatic chuck disposed below the substrate receiving surface, and a plurality of compressible buttons disposed within a respective opening formed in the recessed portion that form an electrical circuit with the electrostatic chuck.

Abstract: Embodiments of a process kit are provided herein. In some embodiments, a process kit includes a deposition ring configured to be disposed on a substrate support, the deposition ring including an annular band configured to rest on a lower ledge of the substrate support, the annular band having an upper surface and a lower surface, the lower surface including a step between a radially inner portion and a radially outer portion; an inner lip extending upwards from the upper surface of the annular band and adjacent an inner surface of the annular band, wherein a depth between an upper surface of the annular band and a horizontal portion of the upper surface of the inner lip is between about 6.0 mm and about 12.0 mm; a channel disposed radially outward of and beneath the annular band; and an outer lip extending upwardly and disposed radially outward of the channel.

Abstract: The present disclosure relates to a ceramic susceptor. The ceramic susceptor of the present disclosure includes: an insulating plate on which a high-frequency electrode is disposed; a shaft connected to the insulating plate; a connection mount connected to a longitudinal end of the shaft; a first rod and a second rod, which are connected to the high-frequency electrode, pass through the longitudinal end of the shaft, and extend to the connection mount; and a connection member disposed in the connection mount, wherein the connection member connects the first rod to the second rod.

Abstract: A plasma processing chamber for depositing a film on an underside surface of a wafer, includes showerhead pedestal. The showerhead pedestal includes a first zone and a second zone. An upper separator fin is disposed over a top surface of the showerhead pedestal and a lower separator fin is disposed under the top surface of the showerhead pedestal and aligned with the upper separator fin. The first zone is configured for depositing a first film to the underside surface of the wafer and the second zone is configured for depositing a second film to the underside surface of the wafer. In another embodiment, a top surface of the showerhead pedestal may be configured to receive a masking plate instead of the upper separator fin. The masking plate is configured with a first area that has openings and a second area that is masked. The first areas is used to provide the process gas to a portion of the underside surface of the wafer for depositing a film.

Abstract: Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.

Abstract: A physical vapor deposition processing chamber is described. The processing chamber includes a target backing plate in a top portion of the processing chamber, a substrate support in a bottom portion of the processing chamber, a deposition ring positioned at an outer periphery of the substrate support and a shield. The substrate support has a support surface spaced a distance from the target backing plate to form a process cavity. The shield forms an outer bound of the process cavity. In-chamber cleaning methods are also described. In an embodiment, the method includes closing a bottom gas flow path of a processing chamber to a process cavity, flowing an inert gas from the bottom gas flow path, flowing a reactant into the process cavity through an opening in the shield, and evacuating the reaction gas from the process cavity.

Abstract: The present disclosure relates to a ceramic susceptor. The ceramic susceptor of the present disclosure includes: an insulating plate on which a high-frequency electrode is disposed; a shaft connected to the insulating plate; a connection mount connected to a longitudinal end of the shaft; a first rod and a second rod, which are connected to the high-frequency electrode, pass through the longitudinal end of the shaft, and extend to the connection mount; and a connection member disposed in the connection mount, wherein the connection member connects the first rod to the second rod.

Abstract: A semiconductor laser device is provided. The semiconductor laser device includes: a substrate having a first facet; a guiding layer having a second facet through which an output light is configured to be emitted; a bottom dielectric layer between the substrate and the guiding layer; and a top dielectric layer on the guiding layer. The second facet is at an angle relative to the first facet.

Abstract: A film may be formed on a surface of a substrate by chemical vapor deposition in a reaction container provided with at least a first holding member that is capable of holding the substrate and a second holding member that is capable of holding the substrate independently from the first holding member, by: (a) forming a film on the surface of the substrate by chemical vapor deposition while holding the substrate by the first holding member; (b) moving at least one holding member among the first holding member and the second holding member in at least one direction of the upward direction and the downward direction to hold the substrate by the second holding member instead of the first holding member; and (c) forming a film on the surface of the substrate held by the second holding member by chemical vapor deposition.

Abstract: Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.

Abstract: A substrate processing system includes: a substrate transfer device; processing units each having a substrate holding mechanism for rotatably holding a substrate received from the substrate transfer device and a processing fluid supply part for supplying a processing fluid to the substrate; and a controller for controlling the substrate transfer device and the processing units according to processing recipe information so as to execute the substrate processing process. When an abnormality in a certain unit of the processing units occurs in the substrate processing process for the substrate to be processed, the controller controls the substrate transfer device and a relief processing unit according to complementary recipe information so that the complementary processing process for a relief substrate is executed in the relief processing unit by transferring the relief substrate to the relief processing unit different from the certain processing unit.

Abstract: A method for forming a silicon film includes supplying a first processing gas including a silicon-containing gas to a substrate to deposit a first silicon film under a first processing condition; and supplying a second processing gas including the silicon-containing gas to the substrate to deposit a second silicon film under a second processing condition. A second in-plane distribution of film characteristic when the second silicon film is deposited under the second processing condition is different from a first in-plane distribution of the film characteristic when the first silicon film is deposited under the first processing condition.

Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.

Abstract: Quality of a crystalline film is improved. In a method for manufacturing a panel, a polysilicon film is formed by emission of laser light to an amorphous silicon film 3A through a light-transmittable member 4 that can transmit the laser light.

Abstract: A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices.

Abstract: The present disclosure pertains to embodiments of a semiconductor deposition reactor manifold and methods of using the semiconductor deposition reactor manifold which can be used to deposit semiconductor layers using processes such as atomic layer deposition (ALD). The semiconductor deposition reactor manifold has a bore, a first supply channel, and a second supply channel. Advantageously, the first supply channel and the second supply channel merge with the bore in an offset fashion which leads to reduced cross-contamination within the supply channels.

Abstract: A calibration object is retrieved, by a first robot arm of a transfer chamber, from a processing chamber connected to the transfer chamber and placed in a load lock connected to the transfer chamber. The calibration object is retrieved from the load lock by a second robot arm of a factory interface connected to the load lock and placed at an aligner station housed in or connected to the factory interface. The calibration object has a first orientation at the aligner station. A difference is determined between the first orientation and an initial target orientation at the aligner station. A first characteristic error value associated with the processing chamber is determined based on the determined difference. The first characteristic error value is recorded in a storage medium. The aligner station is to use the first characteristic error value for alignment of objects to be placed in the processing chamber.

Abstract: A method of fabricating cooling features on a CMC component may comprise compressing a fabric preform within tooling including holes and/or recesses facing the fabric preform. During the compression, portions of the fabric preform are pushed into the holes and/or recesses. Gases are delivered through the tooling to deposit a matrix material on exposed surfaces of the fabric preform while the fabric preform is being compressed. The matrix material builds up on the portions of the fabric preform pushed into the holes and/or recesses, and a rigidized preform with surface protrusions is formed. The tooling is removed, and the rigidized preform is densified, thereby forming a CMC component including raised surface features.

Abstract: A heater assembly having a backside purge gap formed between a top plate and a heater of the heater assembly, the top plate having a top plate wall. The top plate wall having an upper portion, a middle portion and a lower portion, the middle portion forming an incline relative to the top portion.

Abstract: A wafer placement device includes a wafer placement stage including a wafer electrostatic chuck and a wafer cooling plate, a focus-ring placement stage including a focus-ring electrostatic chuck and a focus-ring cooling plate, and a clamping member arranged around the focus-ring placement stage. The wafer placement stage, the focus-ring placement stage, and the clamping member are separate from one another. A pressing portion of the focus-ring cooling plate presses a wafer cooling plate flange against a mounting plate. The clamping member is fastened to the mounting plate with bolts in a state of pressing a flange against the mounting plate at its flange, thus fixing the wafer placement stage and the focus-ring placement stage to the mounting plate without directly fastening them to the mounting plate.

Abstract: Provided is plasma processing equipment comprising a substrate support, a focus ring disposed along an edge of the upper surface of the substrate support and including a fluid hole passing through a main body, an insulating ring surrounding an outer sidewall of the substrate support and including an inner side surface facing the outer sidewall of the substrate support, an outer side surface, and an upper surface connecting the inner and outer side surfaces, and including upper and lower end portions having different heights, and a connection end portion connecting the upper and lower end portions, a liner surrounding the outer side surface of the insulating ring and a baffle disposed on an upper surface of the liner, wherein a fluid passing through the fluid hole flows along the upper surface, and the baffle generates a pressure difference of the fluid between the upper and lower end portions.

Abstract: A cassette which receives a substrate, and a substrate receiving system including a chamber which receives a cassette in which a substrate is loaded are provided. The cassette which receives a substrate includes: a plurality of slot supports stacked in a first direction; and a frame connected to the plurality of slot supports and extending in the first direction, wherein the plurality of slot supports and the frame are opened in an outward direction to receive the substrate, and are closed in an inward direction after the substrate is received.

Abstract: Substrate supports comprising a plurality of bonded plates forming a single component support body and methods of forming the substrate supports are described. The single component support body has an outer peripheral edge, a top surface and a bottom surface. A pocket is formed in the top surface and has a bottom surface, a depth and an outer peripheral edge. A purge ring is spaced a distance from the outer peripheral edge and comprises at least one opening in the top surface in fluid communication with a purge gas line within the body thickness.

Abstract: A substrate treatment apparatus is provided. The substrate treatment apparatus includes a substrate support part provided with a seating surface and configured to support a substrate, a guide ring annularly disposed along an edge of the substrate support part to surround the substrate, and a centering part provided inside the guide ring and configured to center the substrate by moving in a direction parallel to the seating surface to pressurize the edge of the substrate.

Abstract: A wafer support includes an RF electrode and a heater electrode that are embedded inside a disk-shaped ceramic base having a wafer placement surface. The RF electrode is constituted by a plurality of RF zone electrodes that are individually disposed for each of a plurality of divided zones of the wafer placement surface. The plurality of RF zone electrodes are separately disposed in at least two stages that are positioned at different distances from the wafer placement surface. The heater electrode is constituted by a plurality of heater zone electrodes that are individually disposed for each of a plurality of divided zones of the wafer placement surface, the zones being divided in a similar or different way to or from the RF zone electrodes.

Abstract: A plurality of substrate support pins are provided upright on a holding plate so as to contact a position on which no stress is exerted in a lower surface of a semiconductor wafer when an upper surface of the semiconductor wafer is irradiated with flash light emitted from a flash lamp and thus reaches a maximum temperature. When the application of the flash light causes the upper surface of the semiconductor wafer to warp such that the upper surface becomes raised, stress concentration does not occur in the contact position of the lower surface of the semiconductor wafer that contacts the plurality of substrate support pins. The semiconductor wafer can be prevented from breaking during the application of the flash light.

Abstract: A plasma processing method according to an exemplary embodiment includes preparing a substrate in a chamber of a plasma processing apparatus. The substrate is disposed on a substrate support in the chamber. The substrate support includes a lower electrode and an electrostatic chuck. The electrostatic chuck is provided on the lower electrode. The plasma processing method further includes applying a positive voltage to a conductive member when plasma is being generated in the chamber for plasma processing on the substrate. The conductive member extends closer to a grounded side wall of the chamber than the substrate.

Abstract: An electrostatic chuck solves the problem of wafer sticking by providing conductive paths on raised embossments that are bridged together and are connected to ground that support the wafer substrate above the surface of the electrostatic chuck. Further, laterally spaced electrode patterns and electrode elements which are spaced laterally and longitudinally away from the raised embossments reduce or eliminate electrical coupling during wafer clamping between conductively coated embossments and the electrode elements, thereby creating a low resistance path for charges remaining on the wafer after declamping to promptly travel to ground. The conductive bridge and electrode pattern configuration also substantially reduces or eliminates any charge build up on the conductive bridge(s) during clamping in order that charge build up in “islands” (worn portions of the insulator layer of the main field area) do not affect the charge dissipation from the wafer substrate through the conductive bridges to ground.

Abstract: A heat shield structure for a substrate support in a substrate processing system includes an outer shield configured to surround a stem of the substrate support. The outer shield is further configured to define an inner volume between the outer shield and an upper portion of the stem and a lower surface of the substrate support and a vertical channel between the outer shield and a lower portion of the stem of the substrate support. The outer shield includes a cylindrical portion, a first lateral portion extending radially outward from the cylindrical portion, an angled portion extending radially outward and upward from the first lateral portion, and a second lateral portion extending radially outward from the angled portion.

Abstract: A stage includes: a pin insertion passage penetrating the stage on which a substrate is mounted, and configured to allow a lifter pin to be inserted into and penetrate the pin insertion passage, a heat transfer gas passage penetrating the stage, and configured to introduce a heat transfer gas onto a mounting surface of the stage; a common gas passage in communication with the pin insertion passage and the heat transfer gas passage, and configured to allow the heat transfer gas to flow through the common gas passage; and a first member disposed to face the common gas passage at a location at which the pin insertion passage and the common gas passage intersect each other, and configured to adjust a flow rate of the heat transfer gas introduced onto the mounting surface of the stage from the pin insertion passage.