CONFORMAL COLOR FILTER LAYER ABOVE MICROLENS STRUCTURES IN AN IMAGE SENSOR DIE

Abstract

An embodiment of the invention is a semiconductor die having a number of photodetecting sites that are part of a color image sensor. A number of microlens structures are provided, each positioned above a respective one of the photodetecting sites. A color filter layer is formed above the microlens structures. No passivation layer is formed between the microlens structures and a top metal layer of the die. The die may be used as the eye of an electronic system such as a digital camera.

Description

FIELD OF THE INVENTION

[0001] This invention is generally related to semiconductor image sensor dies and related wafer/die fabrication techniques, and more particularly to image sensor dies having color filter layers and microlens structures.

BACKGROUND

[0002] Image sensor dies that can electronically capture a scene in color are at the hearts of a wide range of consumer products such as digital still cameras and video cameras. FIG. 1 shows a cross-section of a conventional color image sensor die. The die is one of many identical dies that are manufactured simultaneously in a semiconductor wafer. The dies are formed layer by layer, normally beginning with an array of photodetecting sites 104 (photosites). Other integrated circuit elements, such as transistors, which cooperate with the photodetecting sites 104 to provide an image signal are not shown. The photosites 104 and the other circuit elements are interconnected using one or more metal layers 112. Only the top most such layer is shown in FIG. 1. The top most metal layer 112 typically forms a grid above the array of photosites to roughly define a well above each site 104. A color filter material is then deposited into the wells across the entire wafer, usually above a passivation layer 116. This material is repeatedly deposited and patterned so that each photosite 104 will have one of several different color filters 120 directly above it. Each photosite will thus respond only to light of a specific color which can pass through its corresponding filter. To improve the efficiency with which a photosite 104 responds to incident light, a microlens structure 128 that focuses the incident light is formed over each photosite. This combination of photosite 104, color filter 120, and microlens structure 128 will be referred to here as a color photocell.

[0003] One of the problems with a sensor die built using the above described color photocell is the presence of small differences in the image signals obtained from theoretically identical photocells that are subjected to the same incident light. These differences are sometimes referred to as photo response non uniformity (PRNU) noise and can significantly, and adversely, affect the accuracy or sharpness of the electronic image captured by the sensor die. The non-uniform thickness of the microlens structure 128 and the underlying color filter 120 across many thousands of photocells in the sensor array may be the cause of such a noise problem.

[0004] A limited solution that helps alleviate the PRNU noise is to place a planarization layer 124 between the color filters 120 and the microlens structures 128, as shown in FIG. 1. This makes the total thickness of the optical structure that includes the microlens, the planarization layer, and the color filter more controllable and hence more uniform across the sensor die. However, such a solution requires the additional process step of depositing and finishing the planarization layer 124. Such an additional process step contributes significantly to the overall cost of the sensor die.

SUMMARY

[0005] An embodiment of the invention is a semiconductor die having a number of photodetecting sites. A microlens structure is positioned above each one of the photodetecting sites with a color filter above the microlens structure.

[0006] Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which:

[0008] FIG. 1 shows a cross-sectional view of a portion of a conventional color sensor die.

[0009] FIG. 2 illustrates a color sensor die according to an embodiment of the invention.

[0010] FIG. 3 shows a color sensor die according to another embodiment of the invention.

[0011] FIG. 4 shows a portion of a process flow for manufacturing a color sensor die according to an embodiment of the invention.

[0012] FIG. 5 depicts an electronic imaging system that features a color sensor die.

DETAILED DESCRIPTION

[0013] An embodiment of the invention is directed to a method of manufacturing a color image sensor die without making a planarization layer, and by forming the color filter layer above the microlens structure rather than below it as done conventionally. Experiments have shown that the color filter layer of such a structure conforms to the shape of the underlying microlens and maintains a substantially uniform thickness throughout the wafer. The microlens structures also maintain a substantially uniform shape throughout the wafer, even in the absence of a planarization layer underneath. This combination may help reduce PRNU noise from the color sensor die while at the same time reduce the overall cost of the die by eliminating the planarization layer.

[0014] FIG. 2 shows a cross-sectional view of a portion of a color image sensor die according to an embodiment of the invention. The die may be formed according to conventional metal oxide semiconductor (MOS) integrated circuit fabrication processes, including those which are specifically optimized for implementing complex logic integrated circuits. The photosites 204 can be either photodiodes or photogates. These may be built at approximately the same level as or below a field oxide layer 208. Each photosite 204 is normally part of a respective one of a number of photocells arranged as an array. Each photocell in this sensor array may include reset circuitry and readout circuitry, collectively being reference 304 in FIG. 3, that provide a pixel signal in response to reset and select signals.

[0015] One or more layers of metal interconnect and interlayer dielectric (not shown) may be present between the photosite 204 and a passivation layer 216. In this case, only the top metal layer obtained by a non-planar fabrication process is shown. The lines of the top metal layer that traverse the sensor array portion of the die may be used primarily for supplying power to the photocells. These lines in part define a well region over each photosite, as shown in the embodiment of FIG. 2.

[0016] A number of microlens structures each having a convex external surface and positioned inside a respective one of the wells above the passivation layer 216 are formed. A color filter layer is formed above the microlens and is in direct contact with the microlens structures and conforms to the convex external surface of the microlens. The entire optical structure that includes the color filter layer 234, the microlens 228, the passivation layer 216, and any lower layers, including oxides, spacers and interlayer dielectrics, above each photosite 204 is sufficiently transparent to allow incident light to pass through and be detected by the photosite.

[0017] FIG. 3 illustrates another embodiment of the image sensor die in which the metal lines that are part of the top metal layer, and which form the wells in the sensor array portion shown in FIG. 2, are absent. In other embodiments, the die may be manufactured by a planar fabrication process in which there is no top metal layer and in which a dielectric layer on top of the die is ground to a smooth flat finish before forming the microlens structures. In such alternative embodiments, the top dielectric layer is not a separate planarization layer.

[0018] Returning to the embodiment in FIG. 3, the lines in the top metal layer have been routed outside the sensor array portion, and power to the sensor array is supplied through the lower set of layers (not shown.) The sensor die also includes row driver circuitry 310 and column driver circuitry 318 that drive a select signal into each photocell to enable readout from a selected one or more of the photocells. Timing signal generation circuitry 322 controls the timing of the select signal for sequentially accessing rows of the photocells. Analog to digital conversion circuitry 314 is also included aboard the die, in this embodiment only, to digitize the analog pixel signals. This integrated configuration in FIG. 3 that includes both the sensor array and analog/digital control and processing circuitry may be built using advanced MOS logic IC fabrication processes having four metal layers.

[0019] FIG. 4 shows a portion of a process flow for manufacturing a color sensor die according to an embodiment of the invention. More specifically, the process flow in FIG. 4 describes only the microlens and color filter formation steps applied to the semiconductor wafer following the passivation step. The fabrication steps for building and interconnecting the photocells, and depositing and forming the passivation layer are not described in any detail because such steps are well known to those of ordinary skill in the art. Also, the description below may include specific steps and measurements that are only given as examples and should not be used to limit the scope of the invention.

[0020] The process control variables for fabricating the microlens structures include the initial thickness of the microlens material (in step 412), the separation distance between photosites (in step 420), and the reflow temperature and baking time (in step 452). The flow in FIG. 4 begins with step 404 in which the passivation layer on the wafer is primed. This may be done according to a vapor prime procedure by placing the wafer in a heated atmosphere with an adhesion promoter. The wafer is then brought back to room temperature in step 408, and spin-coated with a microlens material, according to step 412, to a thickness of several microns. The microlens material is placed directly in contact with the passivation layer, without a planarization layer therebetween. The microlens material in general includes an acrylate polymer such as the commercially available TMR-P7 from Tokyo Ohka Kogyo (TOK) Company of Japan. The wafer is then soft baked as in step 416 to drive off the solvent in the coated microlens material to yield a substantially transparent polymer film.

[0021] The TMR-P7 material includes a photoactive compound (PAC) which is positive photoactive, such that the exposed areas of the microlens material become soluble and can then be removed from the wafer. Thus, in the mask and exposure step 420, the microlens areas above each photosite are masked off before exposing the wafer. The photoactive material is then developed in step 424 to remove the exposed areas of the microlens material, leaving substantially rectangular microlens “stumps” above each photosite. The expose and develop steps should be adjusted to yield a stump with essentially vertical sides, as opposed to sides that are slanted inwards or outwards. The vertical sides help yield a more circular microlens structure.

[0022] Following the develop step 424, the microlens stumps are bleached by, for instance, exposing the wafer to deep ultra violet light for several seconds, as in step 428. This may be needed to yield a more transparent microlens, because the remaining photoactive compound in the unexposed material should be converted. An additional soft bake step 432 helps complete the bleach reaction, leaving the microlens stumps ready for receiving the color filter layer.

[0023] The formation of the color filter layer begins with step 436 in which a layer of color filter material for a first color (e.g., red) is spin coated onto the microlens stumps. The color filter materials used should have the appropriate viscosity and polarity of solvent so as to keep the color particles in suspension in the color filter material. This means that different spin coating procedures will be followed depending on the color being coated. The color material may include color filter materials by FUJI FILM-OLIN of Japan and by TOK of Japan. The thickness of the color material is a function of the required color point for each color, given by the industry standard CIE parameters X and Y. The thickness of the material also determines the color saturation level. This is followed with a soft bake procedure in step 440, and then with step 444 in which the regions of the wafer corresponding to photocells of the first color (red) are exposed through a mask and are therefore cross-linked. The color filter material is then developed in step 448, where its exposed portions corresponding to the first color are insoluble and therefore remain on the wafer. The steps 436-448 may be repeated several times to create additional color filter regions (e.g., blue and green) over the remaining microlens stumps. For instance, a red, blue, and green Bayer pattern may be created on each sensor array.

[0024] Once the different color filters have been created, the wafer is subjected to a reflow procedure in step 452, by, for instance, exposing it to UV light at high temperatures to cross-link the microlens material. The microlens stumps begin to melt and flow to form a convex external surface of the microlens structures as shown in FIG. 2. The color filter on top of each of the microlens stumps bends without changing state (because the Tg, glass transition temperature, of the color filter is higher than that of the microlens material), and conforms to the convex external surface beneath itself, to yield the color filter layer. To chemically set the microlens structures and complete the cross-linking of the microlens structures and the color filter layer, a hardbake procedure may be performed as in step 456. This makes the sensor array resistant to chemical and physical attack without requiring any further passivation layer. The sensor array, as well as the rest of the image sensor die, may now be tested while still part of the wafer.

[0025] As an alternative to the above described sequence, the reflow procedure in step 452 may be performed simultaneously with the bleach step 428 and/or the soft bake in step 432, rather than after the color filter developing step 448. In that case, the color filter materials are coated onto microlens structures having the convex external surface rather than the microlens stumps.

[0026] The manufactured sensor array 306 and its alternatives described above may be used as part of a digital imaging system 500 shown in functional block diagram form in FIG. 5. The imaging system 500 has an optical system 530 that channels incident energy, being visible light in one case, to create an optical image on an image sensor array 306. Control signal generation circuitry 518 is provided to generate electronic shutter control signals and row/column select lines needed to control the photocells of the image sensor. Sensor signals are then further processed by an A/D conversion unit 510 which digitizes the sensor signals and feeds a digital processing block 514. The bitlines from the sensor array 306 may be multiplexed to a single A/D converter or they may each have a dedicated respective A/D converter. The A/D unit 510 and portions of the digital processing block 514 may be located on the same die as the image sensor 306 as shown in FIG. 3. The digital processing may be done by hardwired logic and/or a programmed processor that performs a variety of digital image processing functions, including perhaps preparing compressed digital image data based on the sensor signals for more efficient storage or transmission.

[0027] Transmission of the image data to an external processing system such as a stand alone personal computer may be accomplished using the communication interface 524. For instance, as a digital camera, the communication interface implements a computer peripheral bus standard such as universal serial bus (USB) or a high speed serial bus protocol. The imaging system 500 as a digital camera may also contain a local storage 528 of the non-volatile variety, for instance including a solid state memory such as a removable memory card, a rotating magnetic disk device, or other suitable memory device for permanent storage of digital image data. The operation of the system 700 may be orchestrated by a system controller 522 which may include a conventional microcontroller responding to instructions stored as firmware.

[0028] To summarize, various embodiments of the invention directed to a method of manufacturing a color image sensor die without making a planarization layer, and by forming the color filter layer above the microlens structure rather than below it as done conventionally, have been described. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather that a restrictive sense.

Claims

1. A semiconductor die, comprising:

a plurality of photodetecting sites;

a plurality of microlens structures each positioned above a respective one of the photodetecting sites; and

a color filter layer disposed above the microlens structures.

2. A semiconductor die as in

claim 1, wherein the microlens structures have a convex external surface, and the color filter layer conforms to the external surface.

3. A semiconductor die as in

claim 1, further comprising:

a passivation layer disposed above the photodetecting sites, the microlens structures being positioned above the passivation layer.

4. A semiconductor die as in

claim 2 wherein the color filter layer is in contact with the microlens structures.

5. A semiconductor die as in

claim 1 wherein the color filter layer has substantially uniform thickness across the die.

6. A semiconductor die as in

claim 1, further comprising:

a field oxide layer disposed below the microlens structures; and

a metal layer disposed above the field oxide layer and defining metal lines that cross a region of the die containing the photodetecting sites in a grid pattern, the metal lines defining a plurality of wells each positioned above a respective one of the photodetecting sites, and each of the microlens structures being positioned inside a respective one of the wells.

7. A semiconductor as in

claim 6, further comprising:

a passivation layer that covers said metal layer and the photodetecting sites, the microlens structures disposed on top of the passivation layer.

8. A semiconductor die as in

claim 6, further comprising:

a plurality of lower metal layers below said metal layer.

9. A semiconductor die as in

claim 7, wherein said metal layer is a top metal layer and defines metal lines that provide power to the photodetecting sites.

10. A semiconductor die as in

claim 1 wherein the photodetecting sites include photodiodes.

11. A semiconductor die as in

claim 10 further comprising a field oxide layer disposed below the microlens structures, a photosensitive region of each of the photodiodes being positioned entirely underneath the field oxide layer.

12. A semiconductor die as in

claim 1 wherein each photodetecting site is part of a respective one of a plurality of photocells arranged as an array, each photocell having readout circuitry that provides a pixel signal in response to a select signal, the semiconductor die further comprising:

row driver circuitry that drives the select signal to enable readout from a selected one or more of the photocells; and

timing signal generation circuitry that controls a timing of the select signal for sequentially accessing rows of the photocells.

13. A semiconductor die as in

claim 12 wherein the pixel signal is an analog signal, and wherein the die further comprises:

analog to digital conversion circuitry that digitizes the analog pixel signal.

14. A semiconductor die as in

claim 12 further comprising:

a metal layer above the photocells defining metal lines that cross the array, the metal lines in part defining a plurality of wells each positioned above a respective one of the photodetecting sites, and each of the microlens structures being positioned inside a respective one of the wells between the metal lines.

15. A semiconductor die as in

claim 12 wherein the die is manufactured according to a MOS logic integrated circuit fabrication process having a plurality of metal layers, a lower set of the layers but not a top layer crossing over the array portion of the die, wherein power to the photocells is carried by the lower set of layers.

16. A method of manufacturing, comprising:

creating a plurality of photodetecting sites that are part of a color image sensor on a semiconductor wafer;

depositing a passivation layer above the photodetecting sites;

creating a plurality of microlens structures above the passivation layer, each microlens structure positioned above a respective one of the photodetecting sites to focus incident light onto the respective site; and

creating a color filter layer of multiple colors above the microlens structures.

17. A method according to

claim 16 wherein the created microlens structures are in direct contact with the passivation layer.

18. A method as in

claim 16 further comprising after creating the color filter layer:

hardbaking the wafer; and

without creating any further passivation layer, electrically testing the die while still part of the wafer.

19. A method of manufacturing an image sensor die, comprising:

creating a plurality of microlens structures each positioned above a respective one of a plurality of photodetecting sites in a semiconductor wafer; and

creating a color filter layer of multiple colors above the microlens structures.

20. A method as in

claim 19 wherein the color filter layer is in direct contact with and conforms to an external shape of the microlens structures.

21. A method as in

claim 19, further comprising:

depositing a non-conductive protective layer on the wafer above the photodetecting sites, prior to creating the microlens structures.

22. A method as in

claim 19, further comprising:

creating a metal layer before creating the microlens structures, the metal layer being patterned into a plurality of metal lines above the photodetecting sites that in part define a plurality of wells each positioned above a respective one of the photodetecting sites, and each of the microlens structures being positioned inside a respective one of the wells in between the metal lines.

23. An imaging system comprising:

an image sensor having a plurality of photocells, the photocells providing sensor signals in response to incident light and according to control signals, each photocell having a microlens structure positioned above a photodetecting site and a color filter layer disposed above the microlens structure;

control circuitry configured to generate the control signals for controlling the image sensor;

analog to digital conversion unit for digitizing the sensor signals; and

signal processing circuitry for generating image data in response to the digitized sensor signals.

24. The imaging system of

claim 23 further comprising:

system controller for controlling operation of the imaging system including the signal processing circuitry and the A/D conversion unit.

25. The imaging system of

claim 23 further comprising:

optical system configured to receive the incident light to form an image on the image sensor; and

communication interface for transferring the image data to a stand alone image processing and display system separate from the imaging system.

26. The imaging system of

claim 23 wherein the color filter layer conforms to and is in contact with a convex surface of the microlens structure.

27. The imaging system of

claim 26 further comprising a passivation layer that covers the sensor array, the microlens structures being formed above the passivation layer.