Light Responsive Or Combined With Light Responsive Device Patents (Class 257/290)
  • Patent number: 11128826
    Abstract: A sensor arrangement to sense an external signal comprises a sensor (100) and a charge generator (200) to generate a compensation current (Ic) to compensate the sensor current. A charge generator (200) comprises a first transistor (210) having a parasitic capacitor (212) and a first conductive path. The charge generator (200) comprises a second transistor (220) having a second conductive path being coupled in series to the first transistor (210) and coupled to the output node (O200) of the charge generator (200). The control circuit (600) is configured to control the conductivity of the respective first and second conductive path of the first and the second transistor (210, 220) of the charge generator (200) so that the sensor current is compensated by the compensation current (Ic).
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: September 21, 2021
    Assignee: AMS AG
    Inventor: Herbert Lenhard
  • Patent number: 11114634
    Abstract: A photodiode according to example embodiments includes an anode, a cathode, and an intrinsic layer between the anode and the cathode. The intrinsic layer includes a P-type semiconductor and an N-type semiconductor, and composition ratios of the P-type semiconductor and the N-type semiconductor vary within the intrinsic layer depending on a distance of the intrinsic layer from one of the anode and the cathode.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 7, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung Bae Park, Kyu Sik Kim, Yong Wan Jin, Kwang Hee Lee, Dong-Seok Leem, Seon-Jeong Lim
  • Patent number: 11088193
    Abstract: An image sensor includes a semiconductor substrate providing a plurality of pixel regions, a semiconductor photoelectric device disposed in each of the plurality of pixel regions, an organic photoelectric device disposed above the semiconductor photoelectric device, and a pixel circuit disposed below the semiconductor photoelectric device. The pixel circuit includes a plurality of driving transistors configured to generate a pixel voltage signal from an electric charge generated in the semiconductor photoelectric device and the organic photoelectric device. A driving gate electrode of at least one of the plurality of driving transistors has a region embedded in the semiconductor substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gwi-Deok Ryan Lee, Myung Won Lee, Tae Yon Lee, In Gyu Baek
  • Patent number: 11074845
    Abstract: A display device includes a first amplifier and second data amplifier connected to a first data line and second data line, to a first high voltage power source and second high voltage power source and to a first low voltage power source and second low voltage power source, respectively, a first pixel and second pixel each having a data input terminal connected to the first data line and second data line, respectively. The first high voltage power source and the first low voltage power source determine an upper limit and a lower limit of an output voltage of the first amplifier, respectively, the second high voltage power source and the second low voltage power source determine an upper limit and a lower limit of an output voltage of the second amplifier, respectively, and the first low voltage power source and second low voltage power source are independent power sources.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: July 27, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dae Gwang Jang
  • Patent number: 10998305
    Abstract: A semiconductor die can include: first, second, third, and fourth transistors disposed at intervals, where each two of the first, second, third, and fourth transistors are separated by a separation region to form four separation regions; an isolation structure having a first doping structure of a first doping type, and a second doping structure of a second doping type, to absorb hole carriers and electron carriers flowing between the first, second, third, and fourth transistors; where the first doping structure is located in the separation region to isolate adjacent transistors in the first, second, third, and fourth transistors; and where at least a portion of the second doping structure is surrounded by the first doping structure, and the second doping structure is separated from the first doping structure.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Jianping Qiu, Yicheng Du, Meng Wang
  • Patent number: 10950737
    Abstract: A layered semiconductor structure with a width in a lateral direction, having an operating area covering part of the width of the semiconductor structure, comprises a semiconductor substrate with majority charge carriers of a first polarity; and a first dielectric layer with inducing net charge of the first polarity on the semiconductor substrate. An induced junction is induced in the semiconductor substrate by an electric field generated in the semiconductor substrate by the inducing net charge. The semiconductor structure is configured to confine the electric field generated in the semiconductor substrate in the operating area.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 16, 2021
    Assignee: ELFYS OY
    Inventors: Mikko Juntunen, Hele Savin, Ville Vähänissi, Päivikki Repo, Juha Heinonen
  • Patent number: 10948343
    Abstract: An optical module includes a substrate that has a first surface and a second surface opposite to the first surface and provided with a first hole portion having an opening surface on at least the first surface, an optical element that is provided on the substrate, the optical element having an optical axis located along a thickness direction from the first surface toward the second surface and located in the first hole portion, and a first light shielding portion that is provided on an inner peripheral surface which intersects the opening surface of the first hole portion and has a higher light shielding property than the substrate.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 16, 2021
    Inventor: Noboru Asauchi
  • Patent number: 10903288
    Abstract: A display panel of the present disclosure includes a substrate layer, a light emitting layer and a plurality of photosensitive elements, the light emitting layer includes a plurality of pixel units, the photosensitive elements are formed between the pixel units, the photosensitive elements are configured to sensing light reflected by the fingers and emitted by the pixel units for fingerprint identification, when the finger attaches to the display panel, the light emitted by the light emitting layer and reflected by the fingers reaches the photosensitive elements, the photosensitive elements receive the light for fingerprint identification.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 26, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jian Ye
  • Patent number: 10868157
    Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 15, 2020
    Assignees: Taiwan Semiconductor Manufacturing Co., Ltd., National Taiwan University
    Inventors: Jenn-Gwo Hwu, Chien-Shun Liao
  • Patent number: 10770613
    Abstract: A semiconductor wafer forms on a mold containing a dopant. The dopant dopes a melt region adjacent the mold. There, dopant concentration is higher than in the melt bulk. A wafer starts solidifying. Dopant diffuses poorly in solid semiconductor. After a wafer starts solidifying, dopant can not enter the melt. Afterwards, the concentration of dopant in the melt adjacent the wafer surface is less than what was present where the wafer began to form. New wafer regions grow from a melt region whose dopant concentration lessens over time. This establishes a dopant gradient in the wafer, with higher concentration adjacent the mold. The gradient can be tailored. A gradient gives rise to a field that can function as a drift or back surface field. Solar collectors can have open grid conductors and better optical reflectors on the back surface, made possible by the intrinsic back surface field.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 8, 2020
    Assignee: 1366 TECHNOLOGIES INC.
    Inventors: Ralf Jonczyk, Brian D. Kernan, G.D. Stephen Hudelson, Adam M. Lorenz, Emanuel M. Sachs
  • Patent number: 10743038
    Abstract: The present application provides a live broadcast processing method, an apparatus, a device, and a storage medium thereof, where the method includes: receiving, by a live broadcast server, source media data sent by a first terminal device of a video live broadcast side, where the source media data includes video data and audio data; translating the audio data into audio data in at least one target language; acquiring a playing language required by a video playing side, and acquiring audio data corresponding to the playing language from the audio data in the at least one target language; merging the audio data corresponding to the playing language with the video data to obtain target media data; and transmitting the target media data to a second terminal device of the video playing side for playback.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 11, 2020
    Assignee: BEIJING BAIDU NETCOM SCIENCE TECHNOLOGY CO., LTD.
    Inventor: Zhaomin Zhu
  • Patent number: 10734539
    Abstract: A photodetector is provided with a metal-semiconductor junction for measuring infrared radiation. In another embodiment, the photodetector includes structures to achieve localized surface plasmon resonance at the metal-semiconductor junction stimulated by incident light. The photodetector hence has prompted response and broadband spectra region for photon detection. The photodetector can be used for detecting varied powers of incident light with wavelength from visible to mid-infrared region (300 nm˜20 ?m).
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: August 4, 2020
    Assignee: National Taiwan University
    Inventors: Ching-Fuh Lin, Hung-Chieh Chuang, Meng-Jie Lin, Po-Jui Huang
  • Patent number: 10700798
    Abstract: One general aspect includes a method to receive and deliver media content during a designated time slot, the method including: receiving, via a processor, a first type of media content over a first wireless communication channel; detecting, via the processor, the designated time slot in the first type of media content; receiving, via the processor, a second type of media content over a second wireless communication channel when in proximity of a device configured to wirelessly provide media content; and delivering during the designated time slot, via the processor, the second type of media content to a user.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 30, 2020
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Hassan A. Elnajjar, Steve P. Schwinke, Krishna Soumya Panditha
  • Patent number: 10678074
    Abstract: The present invention relates to a semiconductor optical amplifier, the semiconductor optical amplifier including: a plurality of optical amplification regions arranged in series; a passive waveguide region provided between optical amplification regions; and first and second electrodes provided on an upper surface of each of the optical amplification regions. The passive waveguide region electrically insulates between the first electrodes and between the second electrodes of the adjacent optical amplification regions and optically connects the adjacent optical amplification regions.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 9, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Satoshi Nishikawa
  • Patent number: 10593724
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 17, 2020
    Assignee: ABLiC iNC.
    Inventor: Toshiro Futatsugi
  • Patent number: 10574930
    Abstract: An image sensor includes a first semiconductor layer provided with a pixel, including a photoelectric conversion unit that photoelectrically converts incident light to generate an electric charge, an accumulation unit that accumulates the electric charge generated by the photoelectric conversion unit, and a transfer unit that transfers the electric charge generated by the photoelectric conversion unit to the accumulation unit, a second semiconductor layer provided with a supply unit that supplies the transfer unit with a transfer signal for transferring the electric charge from the photoelectric conversion unit to the accumulation unit, and a third semiconductor layer into which a signal is inputted, the signal being based on the electric charge that has been transferred to the accumulation unit.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: February 25, 2020
    Assignee: NIKON CORPORATION
    Inventors: Atsushi Kamashita, Atsushi Komai, Toru Takagi, Tomohisa Ishida
  • Patent number: 10546962
    Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Tymon Barwicz, William M. Green, Marwan H. Khater, Jessie C. Rosenberg, Steven M. Shank
  • Patent number: 10547318
    Abstract: A DA converter includes a first DA conversion section for obtaining an analog output signal in accordance with a digital input signal value, and a second DA conversion section for obtaining an analog gain control output signal in accordance with a digital gain control input signal value. In the DA converter, the gain control of the analog output signal generated by the first DA conversion section is performed on the basis of the gain control output signal generated by the second DA conversion section.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventors: Go Asayama, Noriyuki Fukushima, Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano
  • Patent number: 10453877
    Abstract: A CMOS detector with pairs of interdigitated elongated finger-like collection gates includes p+ implanted regions that create charge barrier regions that can intentionally be overcome. These regions steer charge to a desired collection gate pair for collection. The p+ implanted regions may be formed before and/or after formation of the collection gates. These regions form charge barrier regions when an associated collection gate is biased low. The barriers are overcome when an associated collection gate is high. These barrier regions steer substantially all charge to collection gates that are biased high, enhancing modulation contrast. Advantageously, the resultant structure has reduced power requirements in that inter-gate capacitance is reduced in that inter-gate spacing can be increased over prior art gate spacing and lower swing voltages may be used. Also higher modulation contrast is achieved in that the charge collection area of the low gate(s) is significantly reduced.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 22, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Cyrus Bamji
  • Patent number: 10374143
    Abstract: A semiconductor integrated circuit constituting a part of a sensor signal processing apparatus for processing sensor signal output from a sensor includes: a first terminal where one end of a vibrator externally attached to the semiconductor integrated circuit is connected and a second terminal where the other end of the vibrator is connected; and an oscillation circuit oscillating the vibrator connected via the first and second terminals, wherein the oscillator circuit intermittently oscillating the vibrator based on control signal, wherein a first period where the oscillation circuit oscillates the vibrator and a second period where the oscillation circuit does not oscillate the vibrator are alternately switched, wherein, during the first period, potentials of the first and second terminals are alternately switched complementarily to high level and low level, and wherein, during the second period, the potentials of the first terminal and the second terminal are fixed to the low level.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignee: Rohm Co., Ltd.
    Inventors: Akihiro Ota, Yuzo Mizushima, Yuji Kaneda, Isao Niwa
  • Patent number: 10256265
    Abstract: An object is to provide an imaging device with high efficiency of transferring charge corresponding to imaging data. The imaging device includes first to fifth conductors, first and second insulators, an oxide semiconductor, a photoelectric conversion element, and a transistor. The first conductor is in contact with a bottom surface and a side surface of the first insulator. The first insulator is in contact with a bottom surface of the oxide semiconductor. The oxide semiconductor is in contact with bottom surfaces of the second and third conductors and the second insulator. Each of the second and third conductors is in contact with the bottom surface and a side surface of the second insulator. The second insulator is in contact with bottom surfaces of the fourth and fifth conductors. The first conductor has regions overlapped by the fourth and fifth conductors. The second conductor has a region overlapped by the fourth conductor. The third conductor has a region overlapped by the fifth conductor.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 9, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takayuki Ikeda
  • Patent number: 10249818
    Abstract: According to one embodiment, a memory element includes a first layer, a second layer, and a third layer. The first layer is conductive. The second layer is conductive. The third layer includes hafnium oxide and is provided between the first layer and the second layer. The first layer includes a first region, a second region, and a third region. The first region includes a first element and a first metallic element. The first element is selected from a group consisting of carbon and nitrogen. The second region includes a second metallic element and is provided between the first region and the third layer. The third region includes titanium oxide and is provided between the second region and the third layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: April 2, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Marina Yamaguchi, Shosuke Fujii, Riichiro Takaishi, Yuuichi Kamimuta, Shoichi Kabuyanagi, Masumi Saitoh
  • Patent number: 10205033
    Abstract: The present disclosure relates to a semiconductor photomultiplier which comprises one or more microcells on a substrate having at least one terminal. At least one ESD protection element is operably coupled to the at least one terminal.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 12, 2019
    Assignee: SensL Technologies Ltd.
    Inventors: Paul Malachy Daly, John Carlton Jackson, Brian McGarvey, Stephen Bellis
  • Patent number: 10193035
    Abstract: A light emitting structure includes a packaged back-emitting light emitting device mounted on a reflective substrate. The properties of the reflective surface may be controlled to provide a desired luminance pattern. In this manner, the creation of a light emitting structure that provides a desired luminance pattern may be independent of the provider of the packaged light emitting device.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: January 29, 2019
    Assignee: Lumileds LLC
    Inventors: Frederic Stephane Diana, Erno Fancsali, Thierry De Smet, Gregory Guth, Yourii Martynov
  • Patent number: 10168570
    Abstract: A display apparatus includes a first substrate, a second substrate assembled to the first substrate, and several spacers disposed between the first substrate and the second substrate. The first substrate includes a first base plate and a first light-shielding layer disposed on the first base plate, wherein the first light-shielding layer includes several first light-shielding portions extending along a first direction. The second substrate includes a second base plate and a second light-shielding layer disposed on the second base plate, wherein the second light-shielding layer includes several second light-shielding portions extending along a second direction, and the second direction is different from the first direction.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: January 1, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Li-Ming Lin, Chih-Ming Liang, Yi-Chun Kuo
  • Patent number: 10163963
    Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: December 25, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Johan Camiel Julia Janssens, Manuel H. Innocent, Sergey Velichko, Tomas Geurts
  • Patent number: 10164160
    Abstract: A light emitting structure includes a packaged back-emitting light emitting device mounted on a reflective substrate. The properties of the reflective surface may be controlled to provide a desired luminance pattern. In this manner, the creation of a light emitting structure that provides a desired luminance pattern may be independent of the provider of the packaged light emitting device.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 25, 2018
    Assignee: Lumileds LLC
    Inventors: Frederic Stephane Diana, Erno Fancsali, Thierry De Smet, Gregory Guth, Yourii Martynov
  • Patent number: 10157956
    Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: December 18, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Hushan Cui, Jinjuan Xiang, Xiaobin He, Tao Yang, Junfeng Li, Chao Zhao
  • Patent number: 10156749
    Abstract: The present invention is for a backplane substrate including an in-cell type touch panel advantageous to reducing the number of masks and the number of processes, a liquid crystal display device including the same, and a method of manufacturing the same, includes a plurality of interlayer dielectric layers disposed above a drain electrode of a thin film transistor are simultaneously patterned after forming a sensing line and a common electrode.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 18, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Seong-Pil Cho, Seon-Yeong Kim
  • Patent number: 10139496
    Abstract: A multi-radiation identification and dosimetry system and method that allows for monitoring of alpha, beta, and gamma radiation is disclosed. The system/method incorporates a segmented silicon drift detector (SSDD) that allows measurement of directly absorbed radiation in the semiconductor (betas, conversion electrons, Lx lines, and alphas) on one SSDD segment and radiation from a radiation scintillation detector (RSD) on multiple segments of the SSDD. With the anode side of the SSDD directed toward the radiation inspection surface (RIS), the SSDD+RSD stacked radiation detector collects radiation which is processed by a charge sensitive amplifier (CSA) and then processed by a time stamping differentiator (TSD). A computing control device (CCD) may be configured to collect the time stamp differentiation data from the various SSDD segments to permit the simultaneous discrimination of several types of radiation by and presentation of these radiation types and counts on a display monitor.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: November 27, 2018
    Assignee: MIRION TECHNOLOGIES (CANBERRA), INC.
    Inventors: Olivier Roger Evrard, Roger Abou-Khalil, Stephane Dogny, Nabil Menaa, Wilhelm Friedrich Mueller, Mathieu Morelle, Edward Lee Reagan
  • Patent number: 10090290
    Abstract: An electrostatic discharge (ESD) protection structure containing a bottom diode and a top diode vertically stacked on the bottom diode is provided to render sufficient protection from ESD events with reduced diode footprint. The bottom diode is serially connected to the top diode via a conductive strap structure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan, Tak Ning
  • Patent number: 10043990
    Abstract: A chemical sensing field effect transistor device is disclosed. The device can include a control gate structure interfacing a control side of a semiconductor channel region, a source region, and a drain region. The control gate structure can comprise a control gate dielectric and a control gate electrode. The device can include a sensing gate structure interfacing the semiconductor channel region, the source region, and the drain region at a sensing side of the semiconductor channel region opposite the control gate structure. The sensing gate structure can comprise a sensing gate dielectric, and a sensing gate electrode. The device can include a functional layer interfacing the sensing gate electrode opposite the sensing gate dielectric. The functional layer can have an exposed interface surface. The functional layer can be capable of binding with a target analyte material sufficient to create a measurable change in conductivity across the semiconductor channel region.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 7, 2018
    Assignee: University of Utah Research Foundation
    Inventors: Ling Zang, Benjamin R. Bunes
  • Patent number: 10043992
    Abstract: A photodiode according to example embodiments includes an anode, a cathode, and an intrinsic layer between the anode and the cathode. The intrinsic layer includes a P-type semiconductor and an N-type semiconductor, and composition ratios of the P-type semiconductor and the N-type semiconductor vary within the intrinsic layer depending on a distance of the intrinsic layer from one of the anode and the cathode.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Bae Park, Kyu Sik Kim, Yong Wan Jin, Kwang Hee Lee, Dong-Seok Leem, Seon-Jeong Lim
  • Patent number: 10043848
    Abstract: In order to form a light receiving element having high reliability and a MOS transistor together on the same silicon substrate, after forming a gate electrode of the MOS transistor, a gate oxide film in a light receiving element forming region is removed. Then, a thermal oxide film is newly formed in the light receiving element forming region, and ion implantation is performed in the light receiving element forming region through the thermal oxide film such that a shallow pn junction is formed.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: August 7, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Toshiro Futatsugi
  • Patent number: 10026791
    Abstract: An organic light emitting display device includes a substrate including a plurality of pixels defined thereon; a first electrode disposed at each pixel; a bank exposing the first electrode of each pixel; a spacer including, sequentially on the bank, a first layer of a first negative photoreactive acryl and a second layer of a second negative photoreactive acryl having a greater photoreactivity than a photoreactivity of the first negative photoreactive acryl, wherein the first layer has a negative taper and the second layer has a positive taper; an organic layer on the bank and the first electrode, the organic layer including an organic light emitting layer; and a second electrode on the bank, the spacer, and the organic layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: July 17, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Mi-Seong Kim, Joung-Woo Lee, Se-Jun Cho, Seung-Hee Kuk
  • Patent number: 10026852
    Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Tymon Barwicz, William M. Green, Marwan H. Khater, Jessie C. Rosenberg, Steven M. Shank
  • Patent number: 10002879
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a plurality of first stacked structures and two second stacked structures disposed on the substrate. Each of the first stacked structures includes alternately stacked metal layers and oxide layers. Each of the second stacked structures includes alternately stacked silicon nitride layers and oxide layers. The first stacked structures are disposed between the two second stacked structures.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: June 19, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Jia-Rong Chiou
  • Patent number: 9986190
    Abstract: Provided is an imaging apparatus, including: a photoelectric conversion element; an amplifier transistor configured to output a voltage corresponding to electric charges generated by the photoelectric conversion element; a load transistor configured to supply a bias current to the amplifier transistor; and a voltage supply unit configured to input one of a first voltage and a second voltage, which have different voltage values, to a control node of the load transistor via an input capacitor. In the imaging apparatus, a current value of the bias current to be supplied by the load transistor at a time when the second voltage is input to the control node via the input capacitor is larger than a current value of the bias current to be supplied by the load transistor at a time when the first voltage is input to the control node via the input capacitor.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 29, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takamasa Sakuragi
  • Patent number: 9946132
    Abstract: An array substrate and a liquid crystal display panel including the array substrate are provided. The array substrate includes: multiple pixel units; at least one additional functional area located in each row of a matrix formed by the multiple pixel units, where the additional functional area is provided with a gate signal detecting transistor; and a detection signal output line and a preset signal line connected with each other. By detecting whether a drive signal on a gate line is normal using the gate signal detecting transistor, the problem of manually detecting one-by one whether a signal on a gate line is normal can be avoided, thereby improving the detection efficiency and accuracy.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: April 17, 2018
    Assignees: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD., TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Zhaokeng Cao, Dandan Qin, Tingting Cui
  • Patent number: 9905601
    Abstract: Some embodiments of the present disclosure provide an image sensor. The image sensor includes a pixel sensor array including a plurality of photosensors arranged in a semiconductor substrate. Peripheral circuitry is arranged in or on the semiconductor substrate and is spaced apart from the pixel sensor array. A protection ring circumscribes an outer perimeter of the pixel sensor array and separates the pixel sensor array from the peripheral circuitry. The protection ring has an annular width of greater than 20 microns. The protection ring includes a first ring in the substrate neighboring the pixel sensor array, a second ring circumscribing the first ring and meeting the first ring at a first p-n junction, and a third ring circumscribing the second ring and meeting the second ring at a second p-n junction.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: February 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Han Tsai, Chun-Hao Chou, Kuo-Cheng Lee, Yung-Lung Hsu, Yun-Wei Cheng
  • Patent number: 9905608
    Abstract: In electron multiplying charge coupled device (EMCCD) image sensors, electron traps in the dielectric stack underneath charge multiplication electrodes may cause undesirable gain ageing. To reduce the gain ageing drift effect, a dielectric stack may be formed that does not include electron traps in regions underneath charge multiplication electrodes. To accomplish this, silicon nitride in the dielectric stack may be removed in regions underneath the charge multiplication electrodes. The EMCCD image sensors can thus be fabricated with a stable charge carrier multiplication gain during their operational lifetime.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 27, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaroslav Hynecek, Eric Stevens, Christopher Parks, Stephen Kosman
  • Patent number: 9899484
    Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroyuki Tomomatsu, Hiroshi Yamasaki, Sameer Pendharkar
  • Patent number: 9881960
    Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: January 30, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihiro Sato, Ryohei Miyagawa, Tokuhiko Tamaki, Junji Hirase, Yoshiyuki Ohmori, Yoshiyuki Matsunaga
  • Patent number: 9869711
    Abstract: A method for evaluating the performance of a plasma transistor comprises: setting a plasma wave velocity, which is adjusted by a gate overdrive voltage, as a first axis; setting an electronic drift velocity, which is adjusted by a drain-to-source voltage, as a second axis; setting a channel length as a third axis; and checking whether the plasma wave transistor is operated as a terahertz emitter according to a change in the performance parameter value of the plasma wave transistor on the basis of a relational expression among the first axis, the second axis, and the third axis.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: January 16, 2018
    Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Kyung Rok Kim, Jong Yul Park, Sung-Ho Kim
  • Patent number: 9859309
    Abstract: A display device in an embodiment according to the present invention includes a first substrate, a second substrate opposing the first substrate, and a transistor provided in the first substrate, a scanning signal line, a video signal line, and a pixel electrode that are electrically connected to the transistor, and a first insulating layer. The thickness of the first substrate is 0.3 mm or less, the first insulating layer contacts the first substrate, and is provided between the first substrate and the transistor, and the first insulating layer includes an organic insulating layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: January 2, 2018
    Assignee: Japan Display Inc.
    Inventors: Takenori Hirota, Hidekazu Miyake, Toshinari Sasaki, Shinichiro Oka
  • Patent number: 9831279
    Abstract: An image sensor includes a photoelectric conversion portion providing a recessed region, a transfer gate provided in the recessed region, and a floating diffusion region adjacent the transfer gate. The transfer gate includes a first pattern and a second pattern, which are sequentially stacked in the recessed region and have different conductivity types from each other.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Younggu Jin, Jungchak Ahn
  • Patent number: 9818788
    Abstract: A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhy-Jyi Sze, Alexander Kalnitsky, Yimin Huang
  • Patent number: 9795037
    Abstract: A touch panel includes: a uni-axially oriented base film; a transparent electrode pattern layer positioned on the uni-axially oriented base film; a first passivation layer formed in an edge region of the transparent electrode pattern layer and covering end portion side walls of the transparent electrode pattern layer; and a contact hole positioned on the first passivation layer and exposing the first passivation layer.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 17, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Koichi Sugitani, Hoon Kang, Chul Won Park, Yang-Ho Jung
  • Patent number: 9755087
    Abstract: Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, Tymon Barwicz, William M. Green, Marwan H. Khater, Jessie C. Rosenberg, Steven M. Shank
  • Patent number: 9729809
    Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa