Dual damascene and method of making the same

Abstract

A method for manufacturing a dual damascene structure comprises forming a first conductive layer over a substrate. An isolation pillar with a second conductive layer is formed on the first conductive layer. A second isolation layer is formed over the second conductive layer. A portion of the second isolation layer is removed, thereby exposing the isolation pillar. A third isolation layer is formed on the first isolation layer. Subsequently, the third isolation layer is patterned to have a trench in the third isolation layer. The isolation pillar is then removed, thereby forming an opening in the first isolation layer. Then, a conductive material is refilled in the trench and the opening, thereby connecting to the first conductive layer.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a method of fabricating integrated circuits, and specifically, to a method of making a dual damascene structure.

BACKGROUND OF THE INVENTION

[0002] The large integration of semiconductor ICs has been accomplished by a reduction in individual device size. As the integration level of semiconductor devices, increases, each cell generally is reduced in size. To provide for such reduction in cell size, various techniques have been used to improve the performance of the device. For example, DRAM has been increased cell capacitance by increasing the effective area of a cell capacitor. To increase the capacitor's effective area, stacked-capacitor and trench-capacitor structures, as well as combinations thereof, have been developed. With this reduction of device size, many challenges arise in the manufacture of the ICs. Each device requires interconnections for exchanging electrical signals from one device to another device. Specially, the high performance integrated circuits have multi-level connections.

[0003] Additional miniaturization is highly desirable for improved IC performance and cost reduction. Interconnects provide the electrical connections between the various electronic elements of an IC and they form the connections between these elements.

[0004] Many devices includes conductive lines for performing certain function, such as a bit line contact and a storage node contact must all be formed in a DRAM unit cell. Thus, design rules for minimizing area and ensuring adequate process margin are required. A variety of techniques are employed to create interconnect lines and vias. One such technique involves a process generally referred to as dual damascene, which includes forming a trench and an underlying via hole. The trench and the via hole are simultaneous filled with a conductor material, thereby simultaneously forming an interconnect and an underlying plug. This is a preferred structure for low RC interconnect structures. Interconnect structures containing copper are typically fabricated by a Damascene process.

[0005] U.S. Pat. No. 6,140,226 to Grill, et al., entitled “Dual damascene processing for semiconductor chip interconnects”. The prior art involves the Dual Damascene process. A further prior art may refer to U.S. Pat. No. 6,133,140 to Yu, et al. , entitled “Method of manufacturing dual damascene utilizing anisotropic and isotropic properties”. Another one of the arts related to the dual damascene is disclosed in U.S. Pat. No. 6,077,770. However, none of the prior art with the capability to control the width of the conductive line.

[0006] What is needed is a method of controlling the wide of the upper conductive line for dual damascene.

SUMMARY OF THE INVENTION

[0007] The object of the present invention is to form a conductive plug with the capability to control the width of the conductive line for dual damascene.

[0008] A method for manufacturing a dual damascene structure comprises forming a first conductive layer over a substrate. An isolation pillar is formed on the first conductive layer. A second conductive layer is next formed along a surface of the isolation pillar and the first conductive layer. A second isolation layer is formed over the second conductive layer. A portion of the second isolation layer is removed, thereby exposing the isolation pillar. A third isolation layer is formed on the first isolation layer. Subsequently, the third isolation layer is to etched to form a trench in the third isolation layer. The isolation pillar is then removed, thereby forming an opening in the first isolation layer. Then, a conductive material is refilled in the trench and the opening, thereby connecting to the first conductive layer.

[0009] The dual damascene structure comprises a first conductive layer 6 over a substrate. A conductive plug 20 is formed on the first conductive layer 6. A second conductive layer 10 is formed on the surface of the first conductive layer and on the side wall of the conductive plug 20. A further isolation layer 12 is formed on the second conductive layer 6 and another isolation layer 14 is formed on the isolation layer 12 to have a trench exposing a portion of the isolation layer 12 and the plug 20. A further conductive material 20 is filled into the trench and connect to the conductive plug.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

[0011] FIG. 1 is a cross sectional view of a semiconductor wafer illustrating the step of forming pillar and thin conductive layer in accordance with the present invention;

[0012] FIG. 2 is a cross sectional view of a semiconductor wafer illustrating the steps of performing a chemical mechanical polishing in accordance with the present invention;

[0013] FIG. 3 is a cross sectional view of a semiconductor wafer illustrating the step of forming an isolation layer in accordance with the present invention;

[0014] FIG. 4 is a cross sectional view of a semiconductor wafer illustrating the step of forming a trench in accordance with the present invention.

[0015] FIG. 5 is a cross sectional view of a semiconductor wafer illustrating the step of forming a conductive plug in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0016] The present invention relates to a method of making a conductive line for interconnections by using dual damascene technique. It is appreciated that the present invention may be applied to any device. A method for manufacturing a conductive plug in a trench with the capability of controlling the width of the conductive line.

[0017] As will be seen below, turning now to FIG. 1, a substrate 2 is provided, the substrate can be formed of silicon, GaAs, Ge and so on. For example, a single crystal silicon substrate 2 with a <100> crystallographic orientation is shown. Within the substrate 2 may be formed one or more semiconductor devices. The particular devices or their functions are not particularly germane to the present invention. However, the conductive structure for the devices are the subjects of the present invention.

[0018] An isolation layer 4 such as silicon oxide layer or silicon nitride layer is then formed on the surface of the substrate 2. The silicon oxide is typically formed by using any suitable oxide chemical compositions and procedures. The silicon nitride layer is deposited by any suitable process. For example, Low Pressure Chemical Vapor Deposition (LPCVD) , Plasma Enhance Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD). The thickness of the silicon nitride layer is about 1000 to 2000 angstroms. In the preferred embodiment, the reaction gases of the step to form silicon nitride layer include SiH4, NH3, N2, N20 or SiH2Cl2, NH3, N2, N2O.

[0019] A conductive layer 6 is formed over the first isolation layer 4. As known in the art, the conductive layer 6 includes any suitable conductive material such as copper, aluminum, titanium, tungsten, gold and the combination thereof. Subsequently, an isolation pillar 8 is formed by patterning a second isolation layer. In a preferred embodiment, the width of the pillar may range from 0.1-0.3 micron meter depending on the requirement. Thereafter, a second conductive layer 10 is formed over the first conductive layer 6 and along the surface of the isolation pillar 8, thereby forming conductive material on the side wall of the pillar 8. It is appreciated that controlling the thickness of the layer 10 may control the width of the conductive layer attached on the side wall. The second conductive layer 10 can be a metallic layer formed by a sputtering method.

[0020] Next, as shown in FIG. 1, a third isolation layer 12 is formed over the second conductive layer 10. Thereafter, a portion of the third isolation layer 12 and a portion of the second conductive layer 10 are removed using a chemical-mechanical polishing method to the surface of the isolation pillar 8, as shown in FIG. 2.

[0021] Please refer to FIG. 3, a further isolation layer 14 is formed over the polished surface. Preferably, the material of the fourth isolation layer 14 is the same with the one of the isolation pillar 8. Next, lithography technique is used to form a trench 18 in the fourth isolation layer 14. The patterned structure is successively used to act as etching mask for removing the pillar 8, thereby forming an opening 16 in the third isolation layer 12 with conductive material attached on the side wall as shown in FIG. 4. The method may expand the width of the plug for interconnection. For example, if the initial opening width is approximately the width of pillar 8. The width may be expanded by adding the second conductive layer to save the cost to modify the photo mask. It has to be noted that the isolation layer 14 and the isolation pillar are made with the same material. The isolation layer 14 or the isolation pillar is different from the isolation layer 12.

[0022] Referring to FIG. 5, a conductive material 20 is then formed over the isolation layer 14 and refilled into the opening 16 and the trench 14. Similarly, a portion of the conductive layer 20 is removed by chemical mechanical polishing for plararization. It can be understand from the illustration, the plug consisting of the conductive material 10, 20 filled in the opening 16 has a wider width. The feature of the present invention is to form an underlying conductive layer prior to form the isolation pillar 8. Thus, the second conductive layer 12 is thinner compared to the first conductive layer 6. The advantage of using the present invention includes control the size of the plug by controlling the thickness of the thin conductive layer 10. A self-alignment dual damascene may be achieved.

[0023] The dual damascene structure comprises a first conductive layer 6 over a substrate. A conductive plug 20 is formed on the first conductive layer 6. A second conductive layer 10 is formed on the surface of the first conductive layer and on the side wall of the conductive plug 20. A further isolation layer 12 is formed on the second conductive layer 6 and another isolation layer 14 is formed on the isolation layer 12 to have a trench exposing a portion of the isolation layer 12 and the plug 20. A further conductive material 20 is filled into the trench and connect to the conductive plug.

[0024] As is understood by a person skilled in the art, the foregoing preferred embodiments of the present invention are illustrated of the present invention rather than limiting of the present invention. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure. While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Appendix A

[0025] William E. Alford, Reg. No. 37,764; Farzad E. Amini, Reg. No. P 42,261; Aloysius T. C. AuYeung, Reg. No. 35,432; William Thomas Babbitt, Reg. No. 39,591; Carol F. Barry, Reg. No. 41,600; Jordan Michael Becker, Reg. No. 39,602; Bradley J. Bereznak, Reg. No. 33,474; Michael A. Bernadicou, Reg. No. 35,934; Roger W. Blakely, r., Reg. No. 25,831; Gregory D. Caldwell, Reg. No. 39,926; Ronald C. Card, Reg. No. P44,587; Thomas M. Coester, Reg. No. 39,637; Stephen M. De Klerk, under 37 C.F.R. §10.9(b); Michael Anthony DeSanctis, Reg. No. 39,957; Daniel M. De Vos, Reg. No. 37,813; Robert Andrew Diehl, Reg. No. 40,992; Matthew C. Fagan, Reg. No. 37,542; Tarek N. Fahmi, Reg. No. 41,402; James Y. Go, Reg. No. 40,621; James A. Henry, Reg. No. 41,064; Willmore F. Holbrow II, Reg. No. P41,845; Sheryl Sue Holloway, Reg. No. 37,850; George W Hoover II, Reg. No. 32,992; Eric . yman, Reg. No. 30,139; Dag H. Johansen, Reg. No. 36,172; William W. Kidd, Reg. No. 31,772; Erica W. Kuo, Reg. No. 42,775; Michael J. Mallie, Reg. No. 36,591; Andre L. Marais, under 37 C.F.R. § 10.9(b); Paul A. Mendonsa, Reg. No. 42,879; Darren J. Milliken, Reg. 42,004; Lisa A. Norris, Reg. No. P44,976; Chun M. Ng, Reg. No. 36,878; Thien T. Nguyen, Reg. No. 43,835; Thinh V. Nguyen, Reg. No. 42,034; Dennis A. Nicholls, Reg. No. 42,036; Kimberley G. Nobles, Reg. No. 38,255; Daniel E. Ovanezian, Reg. No. 41,236; Babak Redjaian, Reg. No. 42,096; William F. Ryann, Reg. 44,313; James H. Salter, Reg. No. 35,668; William W. Schaal, Reg. No. 39,018; James . cheller, Reg. No. 31,195; Jeffrey Sam Smith, Reg. No. 39,377; Maria McCormack Sobrino, Reg. No. 31,639; Stanley . Sokoloff, Reg. No. 25,128; Judith A. Szepesi, Reg. No. 39,393; Vincent P. Tassinari, Reg. No. 42,179; Edwin . Taylor, Reg. No. 25,129; John F. Travis, Reg. No. 43,203; George G. C. Tseng, Reg. No. 41,355; Joseph A. Twarowski, Reg. No. 42,191; Lester J. Vincent, Reg. No. 31,460; Glenn E. Von Tersch, Reg. No. 41,364; John Patrick ard, Reg. o. 40,216; Charles T. J. Weigell, Reg. No. 43,398; Kirk D. Williams, Reg. No. 42,229; James M. Wu, Reg. No. P45,241; Steven D. Yates, Reg. No. 42,242; Ben J. Yorks, Reg. No. 33,609; and Norman Zafman, Reg. No. 26,250; my patent attorneys, and Andrew C. Chen, Reg. No. 43,544; Justin M. Dillon, Reg. No. 42,486; Paramita Ghosh, Reg. No. 42,806; and Sang Hui Kim, Reg. No. 40,450; my patent agents, of BLAKELY, SOKOLOFF, TAYLOR & ZAFMAN LLP, with offices located at 12400 Wilshire Boulevard, 7th Floor, Los Angeles, Calif. 90025, telephone (310) 207-3800, and James R. Thein, Reg. No. 31,710, my patent attorney.

Appendix B

Title 37, Code of Federal Regulations, Section 1.56 Duty to Disclose Information Material to Patentability

[0026] (a) A patent by its very nature is affected with a public interest. The public interest is best served, and the most effective patent examination occurs when, at the time an application is being examined, the Office is aware of and evaluates the teachings of all information material to patentability. Each individual associated with the filing and prosecution of a patent application has a duty of candor and good faith in dealing with the Office, which includes a duty to disclose to the Office all information known to that individual to be material to patentability as defined in this section. The duty to disclosure information exists with respect to each pending claim until the claim is cancelled or withdrawn from consideration, or the application becomes abandoned. Information material to the patentability of a claim that is cancelled or withdrawn from consideration need not be submitted if the information is not material to the patentability of any claim remaining under consideration in the application. There is no duty to submit information which is not material to the patentability of any existing claim. The duty to disclosure all information known to be material to patentability is deemed to be satisfied if all information known to be material to patentability of any claim issued in a patent was cited by the Office or submitted to the Office in the manner prescribed by 2,9001.97(b)-(d) and 1.98. However, no patent will be granted on an application in connection with which fraud on the Office was practiced or attempted or the duty of disclosure was violated through bad faith or intentional misconduct. The Office encourages applicants to carefully examine:

[0027] (1) Prior art cited in search reports of a foreign patent office in a counterpart application, and

[0028] (2) The closest information over which individuals associated with the filing or prosecution of a patent application believe any pending claim patentably defines, to make sure that any material information contained therein is disclosed to the Office.

[0029] (b) Under this section, information is material to patentability when it is not cumulative to information already of record or being made or record in the application, and

[0030] (1) It establishes, by itself or in combination with other information, a prima facie case of unpatentability of a claim; or

[0031] (2) It refutes, or is inconsistent with, a position the applicant takes in:

[0032] (i) Opposing an argument of unpatentability relied on by the Office, or

[0033] (ii) Asserting an argument of patentability.

[0034] A prima facie case of unpatentability is established when the information compels a conclusion that a claim is unpatentable under the preponderance of evidence, burden-of-proof standard, giving each term in the claim its broadest reasonable construction consistent with the specification, and before any consideration is given to evidence which may be submitted in an attempt to establish a contrary conclusion of patentability.

[0035] (c) Individuals associated with the filing or prosecution of a patent application within the meaning of this section are:

[0036] (1) Each inventor named in the application;

[0037] (2) Each attorney or agent who prepares or prosecutes the application; and

[0038] (3) Every other person who is substantively involved in the preparation or prosecution of the application and who is associated with the inventor, with the assignee or with anyone to whom there is an obligation to assign the application.

[0039] (d) Individuals other than the attorney, agent or inventor may comply with this section by disclosing information to the attorney, agent, or inventor.

Claims

1. A method for manufacturing a dual damascene structure, said method comprising the steps of:

forming a first conductive layer over a substrate;

forming an isolation pillar on said first conductive layer;

forming a second conductive layer along a surface of said isolation pillar and said first conductive layer;

forming a second isolation layer over said second conductive layer;

removing a portion of said second isolation layer, thereby exposing said isolation pillar;

forming a third isolation layer on said first isolation layer;

patterning said third isolation layer to form a trench in said third isolation layer;

removing said isolation pillar, thereby forming an opening in said first isolation layer;

refilling a conductive material in said trench and said opening, thereby connecting to said first conductive layer;

wherein said second conductive layer is thinner compared to said first conductive layer, thereby controlling a size of said conductive plug by controlling the thickness of said second conductive layer.

2. The method of claim 1, wherein said first isolation layer is different from said isolation pillar.

3. The method of claim 1, wherein said first isolation layer is different from said second isolation.

4. The method of claim 1, wherein said second isolation and said isolation pillar are made with the same material.

5. A dual damascene structure comprises:

a first conductive layer over a substrate;

a conductive plug formed on said first conductive layer;

a second conductive layer formed on a surface of said first conductive layer and on the side wall of said conductive plug;

a first isolation layer formed on said second conductive layer;

a second isolation layer formed on said first isolation layer to have a trench exposing a portion of said first isolation layer and said conductive plug; and

a conductive material filled into said trench and connect to said conductive plug.

6. The dual damascene structure of claim 4, wherein said first isolation layer is different from said isolation pillar.

7. The dual damascene structure of claim 4, wherein said first isolation layer is different from said second isolation.

8. The dual damascene structure of claim 4, wherein said second isolation and said isolation pillar are made with the same material.