Having Viaholes Of Diverse Width Patents (Class 438/638)
  • Patent number: 11302570
    Abstract: A method for forming an interconnect structure is provided. The method for an interconnect structure includes forming a first metal material over a semiconductor substrate, and forming a first mask element over the first metal material. The first mask element has an opening through the first mask element. The method for forming the interconnect structure also includes forming a second metal material over the first mask element and the first metal material and in the opening, and forming a second mask element corresponding to the opening and over the second metal material. The method for forming the interconnect structure also includes etching the second metal material and the first metal material using the second mask element and the first mask element to form a via and a first metal line respectively.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Hsiang-Wei Liu
  • Patent number: 11256173
    Abstract: An object of the present invention is to provide a treatment liquid for manufacturing a semiconductor and a pattern forming method, in which the formation of particles including metal atoms can be reduced and an excellent pattern can be formed. A treatment liquid for manufacturing a semiconductor according to an embodiment of the present invention includes: a quaternary ammonium compound represented by Formula (N); at least one additive selected from the group consisting of an anionic surfactant, a nonionic surfactant, a cationic surfactant, and a chelating agent; and water. The treatment liquid for manufacturing a semiconductor includes one kind or two or more kinds of metal atoms selected from the group consisting of Na, K, Ca, Fe, Cu, Mg, Mn, Li, Al, Cr, Ni, and Zn, and a total mass of the metal atoms is 1 mass ppt to 1 mass ppm with respect to the sum of a total mass of the additive and the total mass of the metal atoms.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 22, 2022
    Assignee: FUJIFILM Corporation
    Inventors: Tetsuya Kamimura, Tetsuya Shimizu, Satoru Murayama
  • Patent number: 11227829
    Abstract: Integrated circuit structures including device terminal interconnect pillar structures, and fabrication techniques to form such structures. Following embodiments herein, a small transistor terminal interconnect footprint may be achieved by patterning recesses in a gate interconnect material and/or a source or drain interconnect material. A dielectric deposited over the gate interconnect material and/or source or drain interconnect material may be planarized to expose portions of the gate interconnect material and/or drain interconnect material that were protected from the recess patterning. An upper level interconnect structure, such as a conductive line or via, may contact the exposed portion of the gate and/or source or drain interconnect material.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Sairam Subramanian, Walid M. Hafez
  • Patent number: 11114294
    Abstract: A method for forming a layer comprising SiOC on a substrate is disclosed. An exemplary method includes selectively depositing a layer comprising silicon nitride on the first material relative to the second material and depositing the layer comprising SiOC overlying the layer comprising silicon nitride.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: September 7, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Bed Prasad Sharma, Shankar Swaminathan, YoungChol Byun, Eric James Shero
  • Patent number: 11018055
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Patent number: 11011489
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Patent number: 11004735
    Abstract: According to embodiments of the present invention, a semiconductor wafer includes a substrate and an interlayer dielectric located on the substrate. The interlayer dielectric includes an interconnect. A barrier layer is located in between the interconnect and the interlayer dielectric. A semi-liner layer is located in between the interconnect and the barrier layer. The interlayer dielectric, the interconnect, and barrier layer form a substantially planar surface opposite the substrate. The interconnect has an interconnect height from a base to the substantially planar surface and a semi-liner height of the semi-liner layer is less than the interconnect height such that liner layer does not extend to the planar surface.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cornelius B. Peethala, Michael Rizzolo, Oscar Van Der Straten, Chih-Chao Yang
  • Patent number: 10985056
    Abstract: A method of forming fully aligned vias in a semiconductor device, the method including recessing a first level interconnect line below a first interlevel dielectric (ILD), laterally etching the exposed upper portion of the first interlevel dielectric bounding the recess, depositing a dielectric cap layer and a second level interlevel dielectric on top of the first interlevel dielectric, and forming a via opening.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 20, 2021
    Assignee: Tessera, Inc.
    Inventors: Benjamin David Briggs, Joe Lee, Theodorus Eduardus Standaert
  • Patent number: 10957641
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first conductive layer, a second conductive layer, and a contact plug. The first conductive layer is disposed on the substrate and contains a metal silicide. The second conductive layer is disposed on the first conductive layer and contains a metal having bond dissociation energy larger than bond dissociation energy of the metal silicide. The contact plug is disposed on the second conductive layer and includes a main body portion, and a peripheral portion disposed on the surface of the main body portion and containing titanium.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masahiro Inohara
  • Patent number: 10916431
    Abstract: Embodiments of the invention describe a method of forming an integrated circuit. The method includes forming an active semiconductor device region over a substrate. A first contact structure is formed over the active semiconductor device region, wherein the first contact structure includes a first contact liner material and a first contact body material. A conductive gate structure is formed over the active semiconductor device region, and a first gate cap material is formed on the conductive gate structure. The first contact liner material includes a first etch selectivity responsive to a first etch composition, the first contact body material includes a second etch selectivity responsive to the first etch composition, and the first gate cap material includes a third etch selectivity responsive to the first etch composition. The first etch selectivity is greater than each of the second and third etch selectivies.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Raghuveer Reddy Patlolla, Hari Prasad Amanapu, Vimal Kamineni, Sugirtha Krishnamurthy, Viraj Yashawant Sardesai, Cornelius Brown Peethala
  • Patent number: 10756192
    Abstract: A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Kai-Yu Cheng
  • Patent number: 10727119
    Abstract: Interconnects and methods for forming interconnects are described and disclosed herein. The interconnect contains a stack formed on a substrate having a via and a trench formed therein, a first metal formed from a first material of a first type deposited in the via, and a second metal formed from a second material of a second type deposited in the trench.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 28, 2020
    Assignee: Applied Materials, Inc.
    Inventors: He Ren, Feiyue Ma, Yu Lei, Kai Wu, Mehul B. Naik, Zhiyuan Wu, Vikash Banthia, Hua Ai
  • Patent number: 10697084
    Abstract: A high resistance virtual anode for an electroplating cell includes a first layer and a second layer. The first layer includes a plurality of first holes through the first layer. The second layer is over the first layer and includes a plurality of second holes through the second layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Po-Wei Wang, Chun-Lin Chang
  • Patent number: 10651144
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: May 12, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Patent number: 10636701
    Abstract: Semiconductor devices and methods of forming are provided. In some embodiments the method includes forming a dielectric layer over a substrate and patterning the dielectric layer to form a first recess. The method may also include depositing a first layer in the first recess and depositing a second layer over the first layer, the second layer being different than the first layer. The method may also include performing a first chemical mechanical polish (CMP) process on the second layer using a first oxidizer and performing a second CMP process on remaining portions of the second layer and the first layer using the first oxidizer. The method may also include forming a first conductive element over the remaining portions of the first layer after the second CMP polish is performed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Ling-Fu Nieh, Pinlei Edmund Chu, Chi-Jen Liu, Yi-Sheng Lin, Ting-Hsun Chang, Chia-Wei Ho, Liang-Guang Chen
  • Patent number: 10607887
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate and the semiconductor structure having a first conductive contact, forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact. The 3D integrated wiring structure can include a first substrate having a contact hole region; a dielectric layer disposed in the contact hole region; a semiconductor structure formed at the front side of the first substrate, having a first conductive contact; a recess formed at the backside of the first substrate to expose at least a portion of the dielectric layer; and a second conductive layer above the exposed dielectric layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: March 31, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10600737
    Abstract: A non-porous dielectric barrier is provided between a porous portion of a dielectric region and an electrically conductive element of an interconnect portion of an integrated circuit. This non-porous dielectric barrier protects the integrated circuit from breakdown of the least one dielectric region caused by electrical conduction assisted by the presence of defects located in the at least one dielectric region.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 24, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Pascal Fornara, Jean-Philippe Escales
  • Patent number: 10566281
    Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10553480
    Abstract: The present disclosure relates to a method for selectively forming a dielectric material on a first area of a top surface of a substrate. In an embodiment, the method involves providing the substrate including the top surface, the top surface including the first area and a second area, the first area having a hydrophilicity characterized by a water contact angle of at least 45° and the second area having a hydrophilicity characterized by a water contact angle of less than 40°. The method also involves providing a precursor aqueous solution on the substrate, the precursor aqueous solution including: a solvent, a dielectric material precursor, a catalyst for forming a dielectric material from the dielectric material precursor, and an ionic surfactant. Further, the method involves removing the solvent.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: February 4, 2020
    Assignee: IMEC VZW
    Inventors: Murad Redzheb, Silvia Armini
  • Patent number: 10497613
    Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jasmeet S. Chawla, Rami Hourani, Mauro J. Kobrinsky, Florian Gstrein, Scott B. Clendenning, Jeanette M. Roberts
  • Patent number: 10453816
    Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 22, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Bungo Tanaka, Keiji Wada, Satoshi Kageyama
  • Patent number: 10438891
    Abstract: An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-jine Park, Kee-sang Kwon, Jae-jik Baek, Yong-sun Ko, Kwang-wook Lee
  • Patent number: 10276794
    Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 10157774
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact scheme for landing on different contact area levels of a semiconductor structure and methods of manufacture. The structure includes a first contact at a first level of the structure; a jumper contact at a second, upper level of the structure; an etch stop layer having an opening over the first contact and partially encapsulating the jumper contact with an opening exposing the jumper contact; and contacts in electrical contact with the first contact at the first level and the jumper contact at the second, upper level, through the openings.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Carsten K. Peters, Peter Baars
  • Patent number: 10134642
    Abstract: A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and on a p-type field effect transistor (pFET), removing the sacrificial layer and the first work function metal from one of the nFET and the pFET, forming a second work function metal on the one of the nFET and the pFET, a thickness of the second work function metal being substantially the same as a thickness of the first work function metal, and removing the sacrificial layer from the other of the nFET and the pFET.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Ruqiang Bao, Paul Charles Jamison, ChoongHyun Lee
  • Patent number: 9984974
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9927401
    Abstract: A gravimetric detector including a nanoelectronic structure including: a fixed part, at least one part suspended from the fixed part, an excitation device to vibrate the suspended part relative to the fixed part, a detector to detect variations in vibration of the suspended part, and a porous functionalization layer at least partially covering the suspended part, porosity of the functionalization layer being between 3% and 50%.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, APIX ANALYTICS
    Inventors: Muriel Matheron, Regis Barattin, Vincent Jousseaume, Florence Ricoul
  • Patent number: 9842768
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Lin, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 9768063
    Abstract: A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects, wherein the vias are part of a dual damascene structure with trenches and vias is provided. A sealing layer of a first metal or metal alloy that has a low solubility with copper is selectively deposited directly on the copper containing interconnects in at bottoms of the vias, wherein sidewalls of the dielectric layer forming the vias are exposed to the depositing the sealing layer, and wherein the first metal or metal alloy that has a low solubility is selectively deposited to only form a layer on the copper containing interconnects. A via fill of a second metal or metal alloy that has a low solubility with copper is electrolessly deposited over the sealing layer, which fills the vias.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Praveen Nalla, Lie Zhao
  • Patent number: 9728445
    Abstract: In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kuo Hsieh, Ming-Chung Liang
  • Patent number: 9685395
    Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
  • Patent number: 9593205
    Abstract: A polymer, an organic layer composition including the polymer, an organic layer formed from the organic layer composition, and a method of forming patterns using the organic layer composition, the polymer including a moiety represented by Chemical Formula 1: *-A1-A3A2-A4n*.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Soo-Hyoun Mun, Hyo-Young Kwon, Seung-Hyun Kim, Ran Namgung, Dominea Rathwell, Hyeon-Il Jung, Yu-Mi Heo
  • Patent number: 9589832
    Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 7, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Patent number: 9560773
    Abstract: An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, phosphorus, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent decreases throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 31, 2017
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed, Belgacem Haba, Piyush Savalia, Craig Mitchell
  • Patent number: 9553044
    Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang
  • Patent number: 9543191
    Abstract: Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device (100) includes a step in which a CF film (106) is formed on top of a semiconductor substrate (102), a step in which grooves (C) corresponding to a wiring pattern (P) are formed in the CF film (106), and a step in which a copper wiring member (114) is embedded in the grooves (C).
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 10, 2017
    Assignees: ZEON CORPORATION, TOHOKU UNIVERSITY
    Inventors: Takenao Nemoto, Takehisa Saito, Yugo Tomita, Hirokazu Matsumoto, Akihide Shirotori, Akinobu Teramoto, Xun Gu
  • Patent number: 9490205
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming-Han Lee
  • Patent number: 9401359
    Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Yeon Jeong, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Haing Lee, Nam-Myun Cho, In-Ho Kim
  • Patent number: 9384980
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Mitsuhiro Omura, Hisashi Okuchi, Satoshi Wakatsuki, Tsubasa Imamura
  • Patent number: 9355979
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen
  • Patent number: 9345138
    Abstract: A method of manufacturing a laminated substrate, the method includes: forming a first diameter hole to a first surface of a first substrate so as not to penetrate the first substrate; forming a second diameter hole to a second surface of the first substrate so as to communicate with the first diameter hole; plating the first substrate to block the second diameter hole without blocking the first diameter hole; and laminating a second substrate on the second surface of the first substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takumi Hasegawa, Hidehiko Fujisaki
  • Patent number: 9343409
    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Naein Lee
  • Patent number: 9313895
    Abstract: There is provided a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess, which is formed in a predetermined pattern in a Si-containing film of a substrate. The Cu wiring forming method includes forming a Mn film, which becomes a self-aligned barrier film by reaction with an underlying base, at least on a surface of the recess by chemical vapor deposition, forming a Cu film by a physical vapor deposition to fill the recess with the Cu film, and forming a Cu wiring in the recess by polishing the entire surface of the substrate by a chemical mechanical polishing.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Kenji Suzuki, Atsushi Shimada
  • Patent number: 9287162
    Abstract: A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 15, 2016
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Keith Quoc Lao
  • Patent number: 9269563
    Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 23, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Mehul B. Naik
  • Patent number: 9230854
    Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cha-Hsin Chao, Chih-Hao Chen, Hsin-Yi Tsai
  • Patent number: 9214384
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9209392
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 9202838
    Abstract: A method of bonding a semiconductor structure to a substrate to effect both a mechanical bond and a selectively patterned conductive bond, comprising the steps of mechanically bonding a semiconductor structure to a substrate by means of a bonding layer; providing gaps in the bonding layer generally corresponding to a desired conductive bond pattern; providing vias though the substrate generally positioned at the gaps in the bonding layer; causing electrically conductive material to contact the semiconductor structure exposed through the vias. A device made in accordance with the method is also described.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: December 1, 2015
    Inventor: Ian Radley
  • Patent number: 9184054
    Abstract: Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chih-Tsung Shih, Chung-Ju Lee, Chieh-Han Wu, Shinn-Sheng Yu, Jeng-Horng Chen