Having Viaholes Of Diverse Width Patents (Class 438/638)
  • Patent number: 10276794
    Abstract: A memory device includes a substrate, an etch stop layer, a protective layer, and a resistance switching element. The substrate has a memory region and a logic region, and includes a metallization pattern therein. The etch stop layer is over the substrate, and has a first portion over the memory region and a second portion over the logic region. The protective layer covers the first portion of the etch stop layer. The protective layer does not cover the second portion of the etch stop layer. The resistance switching element is over the memory region, and the resistance switching element is electrically connected to the metallization pattern through the etch stop layer and the protective layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
  • Patent number: 10157774
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact scheme for landing on different contact area levels of a semiconductor structure and methods of manufacture. The structure includes a first contact at a first level of the structure; a jumper contact at a second, upper level of the structure; an etch stop layer having an opening over the first contact and partially encapsulating the jumper contact with an opening exposing the jumper contact; and contacts in electrical contact with the first contact at the first level and the jumper contact at the second, upper level, through the openings.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 18, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Carsten K. Peters, Peter Baars
  • Patent number: 10134642
    Abstract: A method of forming a semiconductor device, includes forming a first work function metal and sacrificial layer on an n-type field effect transistor (nFET) and on a p-type field effect transistor (pFET), removing the sacrificial layer and the first work function metal from one of the nFET and the pFET, forming a second work function metal on the one of the nFET and the pFET, a thickness of the second work function metal being substantially the same as a thickness of the first work function metal, and removing the sacrificial layer from the other of the nFET and the pFET.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Alan Anderson, Ruqiang Bao, Paul Charles Jamison, ChoongHyun Lee
  • Patent number: 9984974
    Abstract: A method for fabricating semiconductor device first includes providing a substrate and a shallow trench isolation (STI) in the substrate, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask as mask are utilized to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess and on the STI.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9927401
    Abstract: A gravimetric detector including a nanoelectronic structure including: a fixed part, at least one part suspended from the fixed part, an excitation device to vibrate the suspended part relative to the fixed part, a detector to detect variations in vibration of the suspended part, and a porous functionalization layer at least partially covering the suspended part, porosity of the functionalization layer being between 3% and 50%.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, APIX ANALYTICS
    Inventors: Muriel Matheron, Regis Barattin, Vincent Jousseaume, Florence Ricoul
  • Patent number: 9842768
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first dielectric layer and a first conductive structure over a substrate. The first dielectric layer surrounds the first conductive structure. The method includes forming a second dielectric layer over the first dielectric layer. The second dielectric layer has an opening exposing the first conductive structure. The method includes forming a seal layer over the first conductive structure and an inner wall of the opening. The seal layer is in direct contact with the first dielectric layer and the second dielectric layer, and the seal layer includes a dielectric material comprising an oxygen compound. The method includes removing the seal layer over the first conductive structure. The method includes filling a second conductive structure into the opening.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Lin, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 9768063
    Abstract: A method for filling vias formed in a dielectric layer with a metal or metal alloy that has a low solubility with copper over copper containing interconnects, wherein the vias are part of a dual damascene structure with trenches and vias is provided. A sealing layer of a first metal or metal alloy that has a low solubility with copper is selectively deposited directly on the copper containing interconnects in at bottoms of the vias, wherein sidewalls of the dielectric layer forming the vias are exposed to the depositing the sealing layer, and wherein the first metal or metal alloy that has a low solubility is selectively deposited to only form a layer on the copper containing interconnects. A via fill of a second metal or metal alloy that has a low solubility with copper is electrolessly deposited over the sealing layer, which fills the vias.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 19, 2017
    Assignee: Lam Research Corporation
    Inventors: Artur Kolics, Praveen Nalla, Lie Zhao
  • Patent number: 9728445
    Abstract: In accordance with some embodiments, a method for forming via holes is provided. The method includes providing a substrate with an etch stop layer and a dielectric layer sequentially formed thereon. The method also includes etching the dielectric layer to form a first via hole of a first size and a second via hole of a second size within the dielectric layer by a plasma generated from an etch gas, until both the first via hole and the second via hole are reaching the etch stop layer. The etch gas includes CH2F2 and an auxiliary gas of N2 or O2.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: August 8, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kuo Hsieh, Ming-Chung Liang
  • Patent number: 9685395
    Abstract: A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
    Type: Grant
    Filed: March 5, 2015
    Date of Patent: June 20, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Chih-Tsung Yao, Heng-Kai Liu, Ming-Jer Chiu, Chien-Wen Chen
  • Patent number: 9593205
    Abstract: A polymer, an organic layer composition including the polymer, an organic layer formed from the organic layer composition, and a method of forming patterns using the organic layer composition, the polymer including a moiety represented by Chemical Formula 1: *-A1-A3A2-A4n*.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: March 14, 2017
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Soo-Hyoun Mun, Hyo-Young Kwon, Seung-Hyun Kim, Ran Namgung, Dominea Rathwell, Hyeon-Il Jung, Yu-Mi Heo
  • Patent number: 9589832
    Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 7, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Daisuke Shimizu, Jong Mun Kim
  • Patent number: 9560773
    Abstract: An electrical connection structure includes a variable-composition nickel alloy layer with a minor constituent selected from a group consisting of boron, carbon, phosphorus, and tungsten, wherein at least over a portion of a conductive substrate, the concentration of the minor constituent decreases throughout the variable-composition nickel alloy layer in a direction from the bottom surface of the variable-composition nickel alloy layer to the top surface of the variable-composition nickel alloy layer.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: January 31, 2017
    Assignee: Tessera, Inc.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed, Belgacem Haba, Piyush Savalia, Craig Mitchell
  • Patent number: 9553044
    Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 24, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang
  • Patent number: 9543191
    Abstract: Provided are a semiconductor device and semiconductor-device manufacturing method that make it possible to improve the contact between an insulating film and a wiring member and the reliability thereof. This method for manufacturing a semiconductor device (100) includes a step in which a CF film (106) is formed on top of a semiconductor substrate (102), a step in which grooves (C) corresponding to a wiring pattern (P) are formed in the CF film (106), and a step in which a copper wiring member (114) is embedded in the grooves (C).
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: January 10, 2017
    Assignees: ZEON CORPORATION, TOHOKU UNIVERSITY
    Inventors: Takenao Nemoto, Takehisa Saito, Yugo Tomita, Hirokazu Matsumoto, Akihide Shirotori, Akinobu Teramoto, Xun Gu
  • Patent number: 9490205
    Abstract: A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsiung Tsai, Chung-Ju Lee, Tsung-Jung Tsai, Hsiang-Huan Lee, Ming-Han Lee
  • Patent number: 9401359
    Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: July 26, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Yeon Jeong, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Haing Lee, Nam-Myun Cho, In-Ho Kim
  • Patent number: 9384980
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: forming a first film on a processing target by using a first material; forming a second film on the first film by using a second material; selectively removing the second and first films to provide an opening pierced in the second and first films; selectively forming a metal film on an inner surface of the opening in the first film; and processing the processing target by using the metal film as a mask.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: July 5, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhito Yoshimizu, Mitsuhiro Omura, Hisashi Okuchi, Satoshi Wakatsuki, Tsubasa Imamura
  • Patent number: 9355979
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen
  • Patent number: 9343409
    Abstract: A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: May 17, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangho Rha, Jongmin Baek, Wookyung You, Sanghoon Ahn, Naein Lee
  • Patent number: 9345138
    Abstract: A method of manufacturing a laminated substrate, the method includes: forming a first diameter hole to a first surface of a first substrate so as not to penetrate the first substrate; forming a second diameter hole to a second surface of the first substrate so as to communicate with the first diameter hole; plating the first substrate to block the second diameter hole without blocking the first diameter hole; and laminating a second substrate on the second surface of the first substrate.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: May 17, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Takumi Hasegawa, Hidehiko Fujisaki
  • Patent number: 9313895
    Abstract: There is provided a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess, which is formed in a predetermined pattern in a Si-containing film of a substrate. The Cu wiring forming method includes forming a Mn film, which becomes a self-aligned barrier film by reaction with an underlying base, at least on a surface of the recess by chemical vapor deposition, forming a Cu film by a physical vapor deposition to fill the recess with the Cu film, and forming a Cu wiring in the recess by polishing the entire surface of the substrate by a chemical mechanical polishing.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 12, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tadahiro Ishizaka, Kenji Suzuki, Atsushi Shimada
  • Patent number: 9287162
    Abstract: A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 15, 2016
    Assignees: Samsung Austin Semiconductor, L.P., Samsung Electronics Co., Ltd.
    Inventor: Keith Quoc Lao
  • Patent number: 9269563
    Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 23, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: He Ren, Mehul B. Naik
  • Patent number: 9230854
    Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cha-Hsin Chao, Chih-Hao Chen, Hsin-Yi Tsai
  • Patent number: 9214384
    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chih-Jung Wang
  • Patent number: 9209392
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode that provides for efficient switching of the RRAM cell, and an associated method of formation. In some embodiments, the RRAM cell has a bottom electrode surrounded by a spacer and a bottom dielectric layer. The bottom electrode, the spacer, and the bottom dielectric layer are disposed over a lower metal interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the dielectric data storage layer. Placement of the spacer narrows the later formed bottom electrode, thereby improving switch efficiency of the RRAM cell.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 9202838
    Abstract: A method of bonding a semiconductor structure to a substrate to effect both a mechanical bond and a selectively patterned conductive bond, comprising the steps of mechanically bonding a semiconductor structure to a substrate by means of a bonding layer; providing gaps in the bonding layer generally corresponding to a desired conductive bond pattern; providing vias though the substrate generally positioned at the gaps in the bonding layer; causing electrically conductive material to contact the semiconductor structure exposed through the vias. A device made in accordance with the method is also described.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: December 1, 2015
    Inventor: Ian Radley
  • Patent number: 9184054
    Abstract: Provided is a method of patterning a substrate. The method includes forming a resist layer over the substrate, wherein a layer of resist scum forms in between a first portion of the resist layer and the substrate. The method further includes patterning the resist layer to form a plurality of trenches in the first portion, wherein the layer of resist scum provides a floor for the plurality of trenches. The method further includes forming a first material layer in the plurality of trenches, wherein the first material layer has a higher etch resistance than the resist layer and the layer of resist scum. The method further includes etching the first material layer, the resist layer, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chih-Tsung Shih, Chung-Ju Lee, Chieh-Han Wu, Shinn-Sheng Yu, Jeng-Horng Chen
  • Patent number: 9147748
    Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Ajey Poovannummoottil Jacob, Andreas Knorr, Christopher Prindle
  • Patent number: 9147572
    Abstract: Methods for controlling the length of a replacement metal gate to a designed target gate length and the resulting device are disclosed. Embodiments may include removing a dummy gate from above a substrate forming a cavity, wherein side surfaces of the cavity are lined with an oxidized spacer layer and a bottom surface of the cavity is lined with a gate oxide layer, conformally forming a sacrificial oxide layer over the substrate and the cavity, and removing the sacrificial oxide layer from the bottom surface of the cavity and the substrate leaving sacrificial oxide spacers lining the side surfaces of the cavity.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ashish Kumar Jha, Haiting Wang, Meng Luo, Yong Meng Lee
  • Patent number: 9130077
    Abstract: An image sensor device and a method for manufacturing the image sensor device are provided. An image sensor device includes a substrate, sensor elements disposed at a front surface of the substrate, and a dielectric grid disposed over a back surface of the substrate. The dielectric grid includes a first dielectric layer as a bottom portion, a metal pillar, as a core portion of a upper portion, disposed over the first dielectric layer and a second dielectric layer wrapping around the metal pillar. The image sensor device also includes a stack of layers disposed over the back surface of the substrate. Refractive index of each layers increases from top layer to bottom layer. The image sensor device also includes a color filter and a microlens disposed over the back surface of the substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: September 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ssu-Chiang Weng, Kuo-Cheng Lee, Chi-Cherng Jeng
  • Patent number: 9123722
    Abstract: Some embodiments include methods of forming interconnects. A first circuitry level may be formed, and a first dielectric region may be formed over such first level. A second level of circuitry may be formed over the first dielectric region. An interconnect may be formed to extend through such second level. A second dielectric region may be formed over the second level of circuitry, and a third level of circuitry may be formed over the second dielectric region. The third level of circuitry may be electrically connected to the first level of circuitry through the interconnect. Some embodiments include constructions having interconnects extending from a first level of circuitry, through an opening in a second level of circuitry, and to a third level of circuitry; with an individual interconnect including multiple separate electrically conductive posts.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Ming-Chuan Yang, Zengtao T. Liu, Vishal Sipani
  • Patent number: 9064850
    Abstract: A device include a substrate and an interconnect structure over the substrate. The interconnect structure comprising an inter-layer dielectric (ILD) and a first inter-metal dielectric (IMD) formed over the ILD. A through-substrate via (TSV) is formed at the IMD extending a first depth through the interconnect structure into the substrate. A metallic pad is formed at the IMD adjoining the TSV and extending a second depth into the interconnect structure, wherein the second depth is less than the first depth. Connections to the TSV are made through the metallic pad.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 9054052
    Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: June 9, 2015
    Assignee: GLOBAL FOUNDRIES INC.
    Inventors: Nicholas Vincent Licausi, Errol Todd Ryan, Ming He, Moosung M. Chae, Kunaljeet Tanwar, Larry Zhao, Christian Witt, Ailian Zhao, Sean X. Lin, Xunyuan Zhang
  • Patent number: 9041216
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Jen Sung, Yi-Nien Su
  • Publication number: 20150137368
    Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In one embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 8, 2014
    Publication date: May 21, 2015
    Inventors: Christopher M. Pelto, Ruth A. Brain, Kevin J. Lee, Gerald S. Leatherman
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Publication number: 20150130074
    Abstract: A semiconductor device may include: a wiring layer formed over an interlayer dielectric layer; and one or more wiring characteristic control parts extended from the wiring layer into the interlayer dielectric layer. The bottom of the one or more wiring characteristic control parts may be positioned at a higher level than the bottom of the interlayer dielectric layer.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 14, 2015
    Applicant: SK hynix Inc.
    Inventor: Wang Su KIM
  • Patent number: 9006902
    Abstract: A semiconductor device is provided having an insulating layer on a semiconductor substrate. The insulating layer and the semiconductor substrate define a through hole penetrating the semiconductor substrate and the insulating layer. A through electrode is provided in the through hole. A spacer is provided between the semiconductor substrate and the through electrode. An interconnection in continuity with the through electrode is provided on the insulating layer. A barrier layer covering a side and a bottom of the interconnection and a side of the through electrode is provided and the barrier layer is formed in one body.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: April 14, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Il Choi, Su-Kyoung Kim, Kun-Sang Park, Seong-Min Son, Jin-Ho An, Do-Sun Lee
  • Patent number: 9006101
    Abstract: An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first metallization layer formed over the interlayer dielectric layer, wherein the first metallization layer comprises a first metal line and a dielectric layer formed over the first metallization layer, wherein the dielectric layer comprises a metal structure having a bottom surface coplanar with a top surface of the first metal line.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yu Chen, Ku-Feng Yang, Tasi-Jung Wu, Lin-Chih Huang, Yuan-Hung Liu, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 8987916
    Abstract: A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 24, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Douglas M. Reber
  • Patent number: 8987869
    Abstract: An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Jeong-woo Park, Ju-il Choi
  • Patent number: 8981563
    Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: March 17, 2015
    Assignees: Renesas Electronics Corporation, Ulvac, Inc.
    Inventors: Shinichi Chikaki, Takahiro Nakayama
  • Publication number: 20150072519
    Abstract: A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.
    Type: Application
    Filed: February 26, 2014
    Publication date: March 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 8975750
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 8963319
    Abstract: According to one embodiment, a semiconductor chip includes a semiconductor substrate, a via and an insulating layer. The semiconductor substrate has a first major surface and a second major surface on opposite side from the first major surface. The semiconductor substrate is provided with a circuit section including an element and a wiring and a guard ring structure section surrounding the circuit section on the first major surface side. The via is provided in a via hole extending from the first major surface side to the second major surface side of the semiconductor substrate. The insulating layer is provided in a first trench extending from the first major surface side to the second major surface side of the semiconductor substrate.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumichi Tsumura, Kazuyuki Higashi
  • Patent number: 8962476
    Abstract: A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xia Feng, Jianmin Feng, Kang Chen
  • Publication number: 20150050805
    Abstract: A semiconductor pattern is formed on a substrate. An interlayer insulating layer is formed on the semiconductor pattern. A contact hole in the interlayer insulating layer is formed the semiconductor pattern is exposed. A lower plug is formed in the contact hole by a selective epitaxial growth (SEG) process. An upper plug is formed in the contact hole on the lower plug by alternately and repeatedly performing a deposition process and an etching process.
    Type: Application
    Filed: March 7, 2014
    Publication date: February 19, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: HYOUNG-WON OH, Tae-Jin Lim, Tae-Ki Hong
  • Publication number: 20150048514
    Abstract: This disclosure provides systems, methods and apparatus for a stacked via having a top via structure and a bottom via structure. In one aspect, the bottom via structure includes a bottom dielectric layer and a bottom via extending through the bottom dielectric layer. The bottom via includes a bottom metal formed on the bottom dielectric layer, where the bottom via is substantially filled by a dielectric material. The top via structure includes a top dielectric layer over the bottom metal and a top via extending to a top plane of the bottom via in the top dielectric layer. The top via includes a top metal formed on the top dielectric layer, where the top metal is in electrical contact with the bottom metal at a peripheral area of the bottom via structure.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: QUALCOMM MEMS Technologies, Inc.
    Inventors: Hairong Tang, Yaoling Pan, Tsengyou Syau
  • Patent number: 8956967
    Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata