Planarized To Top Of Insulating Layer Patents (Class 257/752)
  • Patent number: 10593563
    Abstract: Fan-out wafer level packages with resist vias are provided. In an implementation, an example wafer level process or panel fabrication process includes adhering a die to a carrier, applying a temporary resist layer over the die and the carrier, developing the resist layer to form channels or spaces, filling the channels or the spaces with a molding material, removing the remaining resist to create vias in the molding material, and metalizing the vias in the molding material to provide conductive vias for the microelectronics package. The methods automatically create good via and pad alignment. In another implementation, an example process includes adhering a die to a carrier, applying a permanent resist layer over the die and the carrier, developing the resist layer to form vias in the resist layer, and metalizing the vias in the remaining resist of the permanent resist layer to provide conductive vias for the microelectronics package.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: March 17, 2020
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Rajesh Katkar
  • Patent number: 10522463
    Abstract: A semiconductor structure is provided and includes a base substrate including a device region and a peripheral region surrounding the device region, the base substrate including a base interconnection structure formed in each of the device region and the peripheral region; a medium layer on the base substrate; a first interconnection structure through the medium layer and on the base interconnection structure in the device region; and a second interconnection structure through the medium layer and on the base interconnection structure in the peripheral region. The first interconnection structure includes: a first portion over the base interconnection structure, and a second portion partially on the first portion and partially on a portion of the medium layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Cheng Long Zhang, Qi Yang He, Yan Wang
  • Patent number: 10483461
    Abstract: Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: November 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Bharat Bhushan, Mahesh Bhatkar, Juan Boon Tan
  • Patent number: 10381278
    Abstract: A testing method of a packaging process includes following steps. A substrate is provided. A circuit structure is formed on the substrate. The circuit structure includes a real unit area and a dummy side rail surrounding the real unit area, and a plurality of first circuit patterns is disposed on the real unit area. A second circuit pattern is formed on the dummy side rail, and the second circuit pattern emulates the configurations of at least a portion of the first circuit patterns for operating a simulation test. In addition, a packaging structure adapted for a testing process is also mentioned.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 13, 2019
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Shang-Yu Chang Chien, Nan-Chun Lin
  • Patent number: 10360341
    Abstract: Systems and techniques are described for optimizing an integrated circuit (IC) design. Before routing is performed on the IC design in an IC design flow, an IC design tool can iteratively perform a set of operations, the set of operations comprising: (1) modifying a net in the IC design to obtain a modified net, (2) determining a metal layer for routing the modified net, (3) computing a resistance value and a capacitance value of the modified net based on the metal layer, and (4) computing a delay value for the modified net based on the resistance value and the capacitance value.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Synopsys, Inc.
    Inventors: Abhijeet Chakraborty, David John Seibert, Pingkan Fok, Ramoji Karumuri Rao
  • Patent number: 10347578
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate including a device region and a peripheral region. The base substrate includes a base interconnection structure. The method also includes forming a medium layer on the base substrate. In addition, the method includes forming a first trench having a first depth in the peripheral region, and forming a second trench having a second depth in the device region. The second depth is greater than the first depth. Moreover, the method includes forming a first opening in the device region and forming a second opening in the peripheral region. Further, the method includes forming a first interconnection structure by filling the first opening with a conductive material and forming a second interconnection structure by filling the second opening with the conductive material.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 9, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Cheng Long Zhang, Qi Yang He, Yan Wang
  • Patent number: 10345694
    Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 9, 2019
    Assignee: BLOBALFOUNDRIES INC.
    Inventor: Ayman Hamouda
  • Patent number: 10319723
    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kiyoshi Kato
  • Patent number: 10211448
    Abstract: A hybrid nanostructured surface and methods are shown. In one example the hybrid nanostructured surface is used to form one or more electrodes of a battery. Devices such as lithium ion batteries are shown incorporating hybrid nanostructured surfaces.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: February 19, 2019
    Assignee: The Regents of the University of California
    Inventors: Cengiz S Ozkan, Mihrimah Ozkan, Wei Wang
  • Patent number: 10199275
    Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 5, 2019
    Assignee: TESSERA, INC.
    Inventors: Cyprian Uzoh, Vage Oganesian, Ilyas Mohammed
  • Patent number: 10192832
    Abstract: An alignment mark structure including a substrate, an alignment mark and at least one dummy pattern is provided. The alignment mark is disposed on the substrate. The at least one dummy pattern is disposed on the substrate and located adjacent to the alignment mark, wherein a size of the at least one dummy pattern is smaller than a size of the alignment mark.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 29, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Jen Hsiao, Chun-Yun Tsai, Cheng-Yi Hsu
  • Patent number: 10177087
    Abstract: A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Vincent Chun Fai Lau, Jung-ho Do, Byung-sung Kim, Chul-hong Park
  • Patent number: 10167425
    Abstract: The present disclosure relates to an etching solution capable of suppressing particle appearance including a first silane compound in which three or more hydrophilic functional groups are independently bonded to a silicon atom and a second silane compound in which one or two hydrophilic functional groups are independently bonded to a silicon atom.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: January 1, 2019
    Assignee: OCI COMPANY LTD.
    Inventors: Hoseong Yoo, Seunghyun Han, Wook Chang, Yongil Kim
  • Patent number: 10147747
    Abstract: A semiconductor device includes a first layer, a second layer over the first layer, and a third layer over the second layer. The first layer includes a first transistor. The third layer includes a second transistor. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The second layer includes a first insulating film, a second insulating film, and a conductive film. The conductive film has a function of electrically connecting the first transistor and the second transistor. The first insulating film is over and in contact with the conductive film. The second insulating film is provided over the first insulating film. The second insulating film includes a region with a carbon concentration of greater than or equal to 1.77×1017 atoms/cm3 and less than or equal to 1.0×1018 atoms/cm3.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Yoshikazu Hiura, Mai Sugikawa
  • Patent number: 10043767
    Abstract: A method is disclosed that includes the operations outlined below. A plurality of dummy conductive cells that provide different densities are formed in a plurality of empty areas in a plurality of metal layers of a semiconductor device according to overlap conditions of the empty areas between each pair of neighboring metal layers.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: August 7, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
  • Patent number: 9941199
    Abstract: An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Lien Lee, Chun-Chieh Lin
  • Patent number: 9868902
    Abstract: The disclosure is related to a composition for etching, a method for manufacturing the composition, and a method for fabricating a semiconductor using the same. The composition may include a first inorganic acid, at least one of silane inorganic acid salts produced by reaction between a second inorganic acid and a silane compound, and a solvent. The second inorganic acid may be at least one selected from the group consisting of a sulfuric acid, a fuming sulfuric acid, a nitric acid, a phosphoric acid, and a combination thereof.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: January 16, 2018
    Assignee: SOULBRAIN CO., LTD.
    Inventors: Jin Uk Lee, Jae Wan Park, Jung Hun Lim
  • Patent number: 9871012
    Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: January 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vaishnav Srinivas, Bernie Jord Yang, Michael Brunolli, David Ian West, Charles David Paynter
  • Patent number: 9842801
    Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: December 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy Chih-Hung Wei, Mark A. Zaleski
  • Patent number: 9818936
    Abstract: A method for fabricating a semiconductor device includes: forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer; forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer; protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer; oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern; removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 14, 2017
    Assignee: SK hynix Inc.
    Inventor: Sang-Soo Kim
  • Patent number: 9799553
    Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 9786551
    Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: October 10, 2017
    Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Hongguang Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise
  • Patent number: 9754829
    Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Erik R. Hosler, Deniz E. Civay
  • Patent number: 9748176
    Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 29, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deniz E. Civay, Erik R. Hosler
  • Patent number: 9704807
    Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deniz E. Civay, Erik R. Hosler
  • Patent number: 9666529
    Abstract: Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: May 30, 2017
    Assignee: International Business Machines Corporation
    Inventors: Elbert Emin Huang, Takeshi Nogami, Raghuveer R. Patlolla, Christopher J. Penny, Theodorus Eduardus Standaert
  • Patent number: 9646939
    Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: May 9, 2017
    Assignees: International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier
  • Patent number: 9490212
    Abstract: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close or eliminate undesirable opens or voids between two integrated circuits.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 8, 2016
    Inventor: Huilong Zhu
  • Patent number: 9379057
    Abstract: Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: June 28, 2016
    Assignee: International Business Machines Corporation
    Inventors: Elbert Emin Huang, Takeshi Nogami, Raghuveer R. Patlolla, Christopher J. Penny, Theodorus Eduardus Standaert
  • Patent number: 9368395
    Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: June 14, 2016
    Assignee: GlobalFoundries Inc.
    Inventors: Andy Chih-Hung Wei, Mark A. Zaleski
  • Patent number: 9337087
    Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: May 10, 2016
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier
  • Patent number: 9324841
    Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hong Yu, Hyucksoo Yang, Huang Liu, Richard J. Carter
  • Patent number: 9184174
    Abstract: Semiconductor devices are provided. A semiconductor device may include a substrate and a plurality of lines on the substrate. The semiconductor device may include a dielectric layer on the substrate and adjacent the plurality of lines. The semiconductor device may include a connection element in the dielectric layer. In some embodiments, the semiconductor device may include a plurality of contacts on the connection element, and a conductive interconnection on one of the plurality of contacts that are on the connection element and on a contact that is spaced apart from the connection element.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-Gn Yun, Hongsoo Kim, Aaron Park, Hoosung Cho
  • Patent number: 9177815
    Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: November 3, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Gregory Menk, Errol Antonio C. Sanchez, Bingxi Wood
  • Patent number: 9034755
    Abstract: Embodiments of the present invention provide a method of forming contact structure for transistor. The method includes providing a semiconductor substrate having a first and a second gate structure of a first and a second transistor formed on top thereof, the first and second gate structures being embedded in a first inter-layer-dielectric (ILD) layer; epitaxially forming a first semiconductor region between the first and second gate structures inside the first ILD layer; epitaxially forming a second semiconductor region on top of the first semiconductor region, the second semiconductor region being inside a second ILD layer on top of the first ILD layer and having a width wider than a width of the first semiconductor region; and forming a silicide in a top portion of the second semiconductor region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo A. Vega
  • Patent number: 9006895
    Abstract: A metal cap is formed on an exposed upper surface of a conductive structure that is embedded within an interconnect dielectric material. During the formation of the metal cap, metallic residues simultaneously form on an exposed upper surface of the interconnect dielectric material. A thermal nitridization process or plasma nitridation process is then performed which partially or completely converts the metallic residues into nitrided metallic residues. During the nitridization process, a surface region of the interconnect dielectric material and a surface region of the metal cap also become nitrided.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Stephan A. Cohen
  • Patent number: 8993435
    Abstract: In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO2). The precursor is selected from the group consisting essentially of 1-methylsilane (1MS), 2-methylsilane (2MS), 3-methylsilane (3MS), 4-methylsilane (4MS), and combinations thereof.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Chen Wang, Po-Cheng Shih, Chung-Chi Ko, Keng-Chu Lin, Shwang-Ming Jeng
  • Patent number: 8962478
    Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Kunaljeet Tanwar
  • Patent number: 8946835
    Abstract: A planarization process may planarize a media disk that has data trenches between data features and larger servo trenches between servo features. A filler material layer is deposited on the media disk and provides step coverage of the trenches. The filler material has data recesses over the data trenches and servo recesses over the servo trenches that must be removed to produce a planar media surface. A first planarization process is used to remove the data recesses and a second planarization process is used to remove the servo recesses.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Seagate Technology LLC
    Inventors: Yuan Xu, Wei Hu, Justin Jia-Jen Hwu, Gene Gauzner, Koichi Wago, David Shiao-Min Kuo
  • Patent number: 8922018
    Abstract: According to one embodiment, a semiconductor device includes an interconnect provided on a first interlayer insulating film covering a semiconductor substrate in which an element is formed, a cap layer provided on the upper surface of the interconnect, and a barrier film provided between the interconnect and a second interlayer insulating film covering the interconnect. The interconnect includes a high-melting-point conductive layer, and the width of the interconnect is smaller than the width of the cap layer. The barrier film includes a compound of a contained element in the high-melting-point conductive layer.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 30, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Ishizaki, Atsuko Sakata, Junichi Wada, Masahiko Hasunuma
  • Patent number: 8901724
    Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: John Stephen Guzek, Javier Soto Gonzalez, Nicholas R. Watts, Ravi K. Nalla
  • Patent number: 8896121
    Abstract: An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 25, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8883642
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a concave portion on a surface of a substrate to be processed. The method further includes forming a coating film on the substrate to embed the coating film in the concave portion. The method further includes performing a first heat treatment in an atmosphere including an oxidant which contains polar molecules. The method further includes performing a second heat treatment after the first heat treatment by irradiating the coating film with a microwave after or while exposing the coating film to a liquid or a gas containing polar molecules.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: November 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakana Kai, Tomonori Aoyama
  • Patent number: 8884432
    Abstract: An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 11, 2014
    Assignee: Tessera, Inc.
    Inventors: Kazuo Sakuma, Philip Damberg, Belgacem Haba
  • Patent number: 8853862
    Abstract: Embodiments of the present invention provide a contact structure for transistor. The contact structure includes a first epitaxial-grown region between a first and a second gate of, respectively, a first and a second transistor; a second epitaxial-grown region directly on top of the first epitaxial-grown region with the second epitaxial-grown region having a width that is wider than that of the first epitaxial-grown region; and a silicide region formed on a top portion of the second epitaxial-grown region with the silicide region having an interface, with rest of the second epitaxial-grown region, that is wider than that of the first epitaxial-grown region. In one embodiment, the second epitaxial-grown region is at a level above a top surface of the first and second gates of the first and second transistors.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Reinaldo Vega
  • Patent number: 8803317
    Abstract: Interconnect structures and methods of fabricating the same are provided. The interconnect structures provide highly reliable copper interconnect structures for improving current carrying capabilities (e.g., current spreading). The structure includes an under bump metallurgy formed in a trench. The under bump metallurgy includes at least: an adhesion layer; a plated barrier layer; and a plated conductive metal layer provided between the adhesion layer and the plated barrier layer. The structure further includes a solder bump formed on the under bump metallurgy.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Raschid J. Bezama, Harry D. Cox, Timothy H. Daubenspeck, Krystyna W. Semkow, Timothy D. Sullivan
  • Patent number: 8785901
    Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: July 22, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junho Jeong, Sukhun Choi, Jangeun Lee, Kyunghyun Kim, Sechung Oh, Kyungtae Nam
  • Patent number: 8749064
    Abstract: A semiconductor device includes an interlayer insulation film, an underlying line provided in the interlayer insulation film, a liner film overlying the interlayer insulation film, an interlayer insulation film overlying the liner film. The underlying line has a lower hole and the liner film and the interlayer insulation film have an upper hole communicating with the lower hole, and the lower hole is larger in diameter than the upper hole. The semiconductor device further includes a conductive film provided at an internal wall surface of the lower hole, a barrier metal provided along an internal wall surface of the upper hole, and a Cu film filling the upper and lower holes. The conductive film contains a substance identical to a substance of the barrier metal. A highly reliable semiconductor device can thus be obtained.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Maekawa, Kenichi Mori
  • Patent number: 8710661
    Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Patent number: 8710660
    Abstract: A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 29, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao