Diverse Conductive Layers Limited To Viahole/plug Patents (Class 438/629)
  • Patent number: 11522099
    Abstract: Disclosed herein is a method for making a radiation detector. The method comprises forming a recess into a substrate and forming a semiconductor single crystal in the recess. The semiconductor single crystal may be a cadmium zinc telluride (CdZnTe) single crystal or a cadmium telluride (CdTe) single crystal. The method further comprises forming electrical contacts on the semi conductor single crystal and bonding the substrate to another substrate comprising an electronic system therein or thereon. The electronic system is connected to the electrical contact of the semiconductor single crystal and configured to process an electrical signal generated by the semiconductor single crystal upon absorption of radiation particles.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: December 6, 2022
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 11233019
    Abstract: A method including followings is provided. An encapsulated device including a semiconductor die and an insulating encapsulation laterally encapsulating the semiconductor die is provided. An insulating layer is formed over a surface of the encapsulated device. A groove pattern is formed on the insulating layer. A conductive paste is filled in the groove pattern and the conductive paste filled in the groove pattern is cured.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Ching-Feng Yang, Kai-Chiang Wu
  • Patent number: 11195749
    Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Tohru Shirakawa
  • Patent number: 11170992
    Abstract: A method of area selective deposition for cap layer formation in advanced semiconductor contacts. The method includes providing a planarized substrate including a first dielectric layer and a first metal layer, oxidizing a surface of the first metal layer to form an oxidized metal layer, and selectively depositing a second dielectric layer on the oxidized metal layer. The selectively depositing the second dielectric layer can include moving the planarized substrate below a gas inlet dispensing a deposition gas during a spatial vapor phase deposition process, where the deposition gas is preferentially exposed to the oxidized metal layer extending above a surface of the first dielectric layer.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: November 9, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara Tapily, Gerrit Leusink
  • Patent number: 11075270
    Abstract: The present disclosure provides a semiconductor structure and a method for forming the same. The method includes: providing a base, the base including a source-drain doped region and an interlayer dielectric layer over the source-drain doped region; etching the interlayer dielectric layer to form an opening that exposes the source-drain doped region; and forming a first doped region at the top of the source-drain doped region exposed by the opening and a second doped region over the first doped region, a projection of the second doped region on the base covering a projection of the first doped region on the base, the doping ion types of the first doped region, the second doped region and the source-drain doped region being the same, and the ion doping concentration of the first doped region and the second doped region being higher than the ion doping concentration of the source-drain doped region.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 27, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventor: Zhaomeng
  • Patent number: 11075115
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 27, 2021
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10957628
    Abstract: A method for producing a conductive through-via, including applying a seed layer on a surface of a first substrate, and forming a surface modification layer on at least one of the seed layer and a second substrate. Next, the second substrate is bonded to the first substrate with the surface modification layer to form an assembly. A conductive release layer is formed in the at least one through-via by placing a conductive release material into the at least one through-via. The conductive release layer is present on the seed layer and in the at least one through-via. A conductive metal material is applied to the at least one through-via, and the second substrate is removed from the assembly after applying the conductive metal material to the at least one through via.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: March 23, 2021
    Assignee: Corning Incorporated
    Inventors: Robert Alan Bellman, Rajesh Vaddi
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Patent number: 10763158
    Abstract: Embodiments of hybrid-bonded semiconductor structures and methods for forming a hybrid-bonded semiconductor structure are disclosed. The method can include providing a substrate and forming a base dielectric layer on the substrate. The method also includes forming first and second conductive structures in the base dielectric layer and disposing an alternating dielectric layer stack. Disposing alternating dielectric layer stack includes disposing a first dielectric layer on the base dielectric layer and the first and second conductive structures and sequentially disposing second, third, and fourth dielectric layers. The method further includes planarizing the disposed alternating dielectric layer stack and etching the alternating dielectric layer stack to form first and second openings using preset etching rates for each of the first, second, third, and fourth dielectric layers. The etching continues until at least portions of the first and second conductive structures are exposed.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: September 1, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Meng Yan, Jifeng Zhu, Si Ping Hu
  • Patent number: 10763159
    Abstract: A method is provided for forming a multi-level interconnect structure on a semiconductor substrate, e.g., for use in an integrated circuit, comprising forming on the substrate a first interconnection level comprising a first dielectric layer and a first set of conductive structures arranged in the first dielectric layer, forming on the first interconnection level a second interconnection level comprising a second dielectric layer and a second set of conductive structures arranged in the second dielectric layer, and forming on the second interconnection level a third interconnection level.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 1, 2020
    Assignee: IMEC vzw
    Inventors: Basoene Briggs, Christopher Wilson, Juergen Boemmels
  • Patent number: 10755917
    Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Yi Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
  • Patent number: 10727310
    Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10410919
    Abstract: A method of fabricating a wiring structure for a semiconductor device may include forming a lower wiring in a lower insulating layer, forming an etch stop layer covering the lower insulating layer and the lower wiring, forming an interlayer insulating layer on the etch stop layer, forming a preliminary via-hole through the interlayer insulating layer, partially etching the interlayer insulating layer to form a trench partially merged with the preliminary via-hole and a via-hole defined by a remaining portion of the preliminary via-hole, removing the etch stop layer exposed by the via-hole to expose the lower wiring, partially etching a contact area at which the trench and the via-hole are in contact with each other and forming an upper wiring in the via-hole and the trench to be electrically connected to the lower wiring.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yeong-Shin Park, Young-Jae Kim
  • Patent number: 10347564
    Abstract: A semiconductor device composed of a through-substrate-via (TSV) interconnect, and methods for forming the interconnect.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: Matthieu Lagouge, Qing Zhang, Mohommad Choudhuri, Gul Zeb
  • Patent number: 10306760
    Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Islam Salama, Charan Gurumurthy, Hamid Azimi
  • Patent number: 10283604
    Abstract: A method of fabricating semiconductor device includes forming a plurality of gate structures on a semiconductor substrate. A first inter layer dielectric layer is deposited on the gate structures. A first contact plug is formed in the first inter layer dielectric layer in between every two immediately adjacent gate structures. An etch stop layer is deposited on the first inter layer dielectric layer. A second inter layer dielectric layer is deposited on the first inter layer dielectric layer. A second contact plug is formed in the second inter layer dielectric layer aligning with the first contact plug. A metal layer is deposited overlying the second inter layer dielectric layer and the second contact plug.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Szu-Hsien Lu, Hung-Che Liao, Kun-Tsang Chuang, Shih-Lu Hsu, Yu-Chu Lin, Jyun-Guan Jhou
  • Patent number: 10232613
    Abstract: In one example, a liquid ejection device. The device includes a first metal layer over a substrate, a dielectric layer over the first metal layer, and an orifice through the dielectric layer to the first metal layer. The device also includes a second metal layer over the dielectric layer and partially filling the orifice to form a via to electrical connect the two metal layers. The via has a depth-to-width ratio of at least 0.4. The device further includes a passivation stack covering the second metal layer including all interior surfaces of the via. The stack includes an ALD-deposited layer formed by atomic layer deposition.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: March 19, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Zhizhang Chen, Mohammed Saad Shaarawi, Roberto A Pugliese, Jr.
  • Patent number: 10141332
    Abstract: A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure, forming a reflective metal pattern in the first hole, filling an etch stop layer in the first hole and over the reflective metal pattern, forming a second stacked structure over the first stacked structure, and forming a second hole penetrating the second stacked structure to expose the etch stop layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 27, 2018
    Assignee: SK Hynix Inc.
    Inventors: Woo June Kwon, Jong Hoon Kim, Chan Sun Hyun
  • Patent number: 10128148
    Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Viet Ha Nguyen, Nae In Lee, Thomas Oszinda, Byung Hee Kim, Jong Min Baek, Tae Jin Yim
  • Patent number: 10103058
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang
  • Patent number: 10079288
    Abstract: A method and structure is provided in which germanium or a germanium tin alloy can be used as a channel material in either planar or non-planar architectures, with a functional gate structure formed utilizing either a gate first or gate last process. After formation of the functional gate structure, and contact openings within a middle-of-the-line (MOL) dielectric material, a hydrogenated silicon layer is formed that includes hydrogenated crystalline silicon regions disposed over the germanium or a germanium tin alloy, and hydrogenated amorphous silicon regions disposed over dielectric material. The hydrogenated amorphous silicon regions can be removed selective to the hydrogenated crystalline silicon regions, and thereafter a contact structure is formed on the hydrogenated crystalline silicon regions.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek
  • Patent number: 10050139
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Jan Ropohl
  • Patent number: 9966299
    Abstract: Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber to deposit film on a substrate including a feature; after the first ALD cycle, exposing the substrate to an inhibitor plasma in the processing chamber for a predetermined period to create a varying passivated surface in the feature; and after the predetermined period, performing a second ALD cycle in the processing chamber to deposit film on the substrate.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 8, 2018
    Assignee: Lam Research Corporation
    Inventors: Wei Tang, Bart Van Schravendijk, Jun Qian, Hu Kang, Adrien LaVoie, Deenesh Padhi, David C. Smith
  • Patent number: 9947618
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: April 17, 2018
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
  • Patent number: 9735107
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 9564589
    Abstract: A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: February 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yuji Awano, Noriyoshi Shimizu
  • Patent number: 9379044
    Abstract: A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer.
    Type: Grant
    Filed: October 20, 2012
    Date of Patent: June 28, 2016
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
  • Patent number: 9368614
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: June 14, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: François Hébert
  • Patent number: 9355901
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 31, 2016
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9312172
    Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Dirk Meinhold, Heinrich Koerner, Wolfgang Dickenscheid
  • Patent number: 9245826
    Abstract: Disclosed is a structure having anchor vias for improved backside metal adhesion and an associated method for the structure's fabrication. The structure includes at least one anchor via disposed in at least one corner of a semiconductor substrate. A metal filler may be formed within the at least one anchor via, the metal filler having a protruding portion extending from a backside of the semiconductor substrate. The structure may further include a backside metal layer on a bottom surface of the semiconductor substrate, the backside metal layer being bonded to the protruding portion of the metal filler in the at least one anchor via. The at least one anchor via may include a cluster of anchor vias, a plurality of anchor vias disposed in a straight line and/or in a staggered configuration along a periphery of the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: January 26, 2016
    Assignee: Newport Fab, LLC
    Inventors: Hadi Jebory, David J. Howard, Scott B. Stetson
  • Patent number: 9190543
    Abstract: Methods of producing photo-voltaic devices include spray coating deposition of metal chalcogenides, contact lithographic methods and/or metal ion injection. Photo-voltaic devices include devices made by the methods, tandem photo-voltaic devices and bulk junction photovoltaic devices.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: November 17, 2015
    Assignee: The Regents of the University of California
    Inventors: Yang Yang, Wei-Jen Hou, Bao Lei, Shenghan Li
  • Patent number: 9171731
    Abstract: The invention relates to microelectronic technology and, more specifically, relates to a method of forming a gate with a LELE double pattern. The method adopts an ONO structure (Oxide-SiN-Oxide). The ONO structure is exposed twice, and the advanced patterning film is used as a mask in the processing of polysilicon etching. The ONO structure is used to replace the traditional hardmask of silicon oxide, and the substructure of ODL (Organic Under Layer) which is based on the spin-on, and the middle layer structure of SHB (Si-based hardmask). The method saves cost and improves the process of advanced patterning film as a mask with the nodes in 40 nm and above which is applied to the process with the nodes in 22/20 nm and below. Consequently, the maturity and stability of the process for poly gate with the nodes in 22/20 nm and below are improved.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: October 27, 2015
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Jun Huang, ZhiBiao Mao, QuanBo Li, ZhiFeng Gan, RunLing Li
  • Patent number: 9159670
    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 13, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chin-Kwan Kim, Rajneesh Kumar, Omar James Bchir
  • Patent number: 9112002
    Abstract: A method of manufacturing an electrical conductor includes providing a substrate layer, depositing a surface layer on the substrate layer that has pores at least partially exposing the substrate layer, and forming graphene deposits in the pores. Optionally, the graphene deposits may be formed only in the pores. The graphene deposits may be formed along the exposed portions of the substrate layer. The graphene layers may be selectively deposited or may be deposited to cover an entire layer. Optionally, the forming of the graphene deposits may include processing the electrical conductor using a chemical vapor deposition process using an organic compound precursor and heat of sufficient temperature to facilitate graphene growth on the metal compound comprising the substrate layer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 18, 2015
    Assignee: TYCO ELECTRONICS CORPORATION
    Inventors: Mary Elizabeth Sullivan-Malervy, Robert Daniel Hilty, Rodney I. Martens, Min Zheng, Jessica Henderson Brown Hemond, Zhengwei Liu
  • Patent number: 9099534
    Abstract: A manufacturing method of a semiconductor device includes exposing a wiring layer which is formed of an alloy including two or more types of metals having different standard electrode potentials, on one surface side of a semiconductor substrate and performing a plasma process of allowing plasma generated by a mixture gas of a gas including nitrogen and an inert gas or plasma generated by a gas including nitrogen to irradiate a range which includes an exposed surface of the wiring layer.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: August 4, 2015
    Assignee: Sony Corporation
    Inventors: Kazuto Watanabe, Atsushi Matsushita, Hiroshi Horikoshi, Iwao Sugiura, Yuuji Nishimura, Syota Yamabata
  • Patent number: 9093348
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first circuit substrate having a first interconnection; forming a second circuit substrate having a second interconnection; bonding the first circuit substrate to the top surface of the second circuit substrate so as to be stacked facing each other; and performing an etching process of simultaneously removing parts formed on the first interconnection and the second interconnection in a stacked body of the first circuit substrate and the second circuit substrate so as to form a first opening in the top surface of the first interconnection and to form a second opening in the top surface of the second interconnection. The forming of the first circuit substrate includes forming an etching stopper layer on the surface of the first interconnection out of a material having an etching rate lower than that of the first interconnection in the etching process.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 28, 2015
    Assignee: SONY CORPORATION
    Inventor: Ikue Mitsuhashi
  • Patent number: 9076792
    Abstract: A semiconductor device includes a recess defined in a dielectric layer and an interconnect structure defined in the recess. The interconnect structure includes a first barrier layer lining the recess, the first barrier layer including an alloy of tantalum and a first transition metal other than tantalum, wherein a first interface between the first barrier layer and the dielectric layer has a first stress level. A second barrier layer is positioned on the first barrier layer, the second barrier layer including at least one of tantalum and tantalum nitride, wherein a second interface between the second barrier layer and the first barrier layer has a second stress level that is less than the first stress level. The interconnect structure further includes a fill material substantially filling the recess.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: July 7, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vivian W. Ryan, Xunyuan Zhang, Paul R. Besser
  • Patent number: 9059096
    Abstract: A method for forming silicide contacts includes forming a dielectric layer on a gate spacer, a gate stack, and a first semiconductor layer. The first semiconductor layer comprises source/drain regions. Contact trenches are formed in the dielectric layer so as to expose at least a portion of the source/drain regions. A second semiconductor layer is formed within the contact trenches. A metallic layer is formed on the second semiconductor layer. An anneal is performed to form a silicide region between the second semiconductor layer and the metallic layer. A conductive contact layer is formed on the metallic layer or the silicide region.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Guillorn, Christian Lavoie, Ghavam G. Shahidi, Bin Yang, Zhen Zhang
  • Publication number: 20150145593
    Abstract: Microfeature dies with redistribution structures that reduce or eliminate line interference are disclosed. The microfeature dies can include a substrate having a bond site and integrated circuitry electrically connected to the bond site. The microfeature dies can also include and a redistribution structure coupled to the substrate. The redistribution structure can include an external contact site configured to receive an electric coupler, a conductive line that is electrically connected to the external contact site and the bond site, and a conductive shield that at least partially surrounds the conductive line.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventor: Mark S. Johnson
  • Publication number: 20150145135
    Abstract: Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Inventor: Gurtej S. Sandhu
  • Patent number: 9034664
    Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Junjing Bao, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9018092
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: April 28, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 9018089
    Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eric G. Liniger, Griselda Bonilla, Pak Leung, Stephen A. Cohen, Stephen M. Gates, Thomas M. Shaw
  • Patent number: 9012321
    Abstract: Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-ik Kim, Hyoung-sub Kim, Yoo-sang Hwang, Nak-jin Son, Ji-young Kim
  • Patent number: 8987869
    Abstract: An integrated circuit device including an interlayer insulating layer on a substrate, a wire layer on the interlayer insulating layer, and a through-silicon-via (TSV) contact pattern having an end contacting the wire layer and integrally extending from inside of a via hole formed through the interlayer insulating layer and the substrate to outside of the via hole.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-gi Jin, Jeong-woo Park, Ju-il Choi
  • Patent number: 8981570
    Abstract: A through-holed interposer is provided, including a board body, a conductive gel formed in the board body, and a circuit redistribution structure disposed on the board body. The conductive gel has one end protruding from a surface of the board body, and an area of the protruded end of the conductive gel that is in contact with other structures (e.g., packaging substrates or circuit structures) is increased, thereby strengthening the bonding of the conductive gel and reliability of the interposer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 17, 2015
    Assignee: Unimicron Technology Corporation
    Inventors: Tzyy-Jang Tseng, Dyi-Chung Hu, Ying-Chih Chan
  • Patent number: 8980715
    Abstract: Multilayer dielectric structures are provided having silicon nitride (SiN) and silicon oxynitride (SiNO) films for use as capping layers, liners, spacer barrier layers, and etch stop layers, and other components of semiconductor nano-devices. For example, a semiconductor structure includes a multilayer dielectric structure having multiple layers of dielectric material including one or more SiN layers and one or more SiNO layers. The layers of dielectric material in the multilayer dielectric structure have a thickness in a range of about 0.5 nanometers to about 3 nanometers.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 17, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alfred Grill, Seth L. Knupp, Son V. Nguyen, Vamsi K. Paruchuri, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 8970046
    Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Lyong Kim, Taehoon Kim, Jongho Lee, Chul-Yong Jang