Method of making printed circuit board with varying depth conductive holes adapted for receiving pinned electrical components
A method of making a printed circuit board in which openings of different length are formed using a cover atop one of the openings to prevent dielectric material from an interim layer of heat-deformable dielectric material from entering the opening when the sub-composite having the opening therein is bonded to a second sub-composite. The bonded sub-composites are then provided with a second opening which extends there-through, this second opening being longer than the first. Pins of an electrical component may then be inserted within the first and second openings of different length.
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In application Ser. No. 10/737,974, filed Dec. 18, 2003 and entitled “METHOD OF PROVIDING PRINTED CIRCUIT BOARD WITH CONDUCTIVE HOLES AND BOARD RESULTING THEREFROM” (Inventors: J. Larnerd et al), there is defined a method of making a printed circuit board in which conductive thru-holes are formed within two dielectric layers of the board's structure so as to connect designated conductive layers. One hole connects two adjacent conductive layers and the other also connects two adjacent conductive layers, including one of the conductive layers connected by the other hole. It is also possible to connect all three conductive layers using one or more holes. The resulting holes may be filled, e.g., with metal plating, or conductive or non-conductive paste. In the case of the latter, it is also possible to provide a top covering conductive layer over the paste, e.g., to serve as a pad or the like on the board's external surface. Application Ser. No. 10/737,974 is assigned to the same Assignee as the present invention.
This application is a continuation-in-part application of Ser. No. 10/737,974.
In Ser. No. 10/955,741, filed Sep. 30, 2004 and entitled “HIGH SPEED CIRCUITIZED SUBSTRATE WITH REDUCED THRU-HOLE STUB, METHOD FOR FABRICATION AND INFORMATION HANDLING SYSTEM UTILIZING SAME” (Inventors: B. Chan et al), there is defined a circuitized substrate including a plurality of conductive and dielectric layers and also a plurality of conductive thru-holes therein for passing high speed signals, e.g., from one component to another mounted on the substrate. The substrate utilizes a signal routing pattern which uses the maximum length of each of the thru-holes wherever possible to thereby substantially eliminate signal loss (noise) due to thru-hole “stub” resonance.
In application Ser. No. 10/811,817, filed Mar. 30, 2004 and entitled “HIGH SPEED CIRCUIT BOARD AND METHOD FOR FABRICATION” (Inventors: B. Chan et al), there is defined a multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections there-between. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components.
All of the above applications are assigned to the same Assignee as the present invention.TECHNICAL FIELD
This invention relates to printed circuit (or wiring) boards and particularly to multilayered printed circuit boards having a plurality of conductive holes therein. Even more particularly, the invention relates to such boards which are adapted for having one or more electrical connectors positioned thereon and electrically coupled thereto.BACKGROUND OF THE INVENTION
As indicated from the following listing of patents, there are different methods of making multilayered printed circuit boards (hereinafter also referred to as PCBs) known today. In the manufacture of some printed circuit boards, for example, it has become commonplace to produce printed circuitry on both sides of a planar rigid or flexible insulating substrate. In addition, such boards also typically include several parallel and planar, alternating inner layers of insulating substrate material and conductive metal. The exposed outer sides of the laminated structure are typically provided with circuit patterns, and the metal inner layers typically contain circuit patterns, except in the case of internal power or ground planes which are usually substantially solid, albeit also containing clearance openings or other openings if desired.
In multilayered printed circuit boards such as these, it is necessary to provide conductive interconnections between the various conductive layers or sides of the board. This is commonly achieved by providing metallized conductive holes in the board which communicate with the sides and layers requiring electrical interconnection. For some applications, it is desired that electrical connection be made with almost if not all of the conductive layers. In such a case, conductive holes are also typically provided through the entire thickness of the board. For these, as well as other applications, it is often desired to also provide electrical connection between the circuitry on one face of the board and one or more of the inner circuit layers. In those cases, holes referred to as “blind vias”, passing only part way through the board, are provided. In still another case, such multilayered boards often require internal holes referred to simply as “vias” which are located entirely within the board's structure and covered by external layering, including both dielectric and conductive. Such internal “vias” are typically formed within a sub-part structure (sub-composite) of the final board and then combined with other layers (including other sub-composites) during final lamination of the board. For purposes of this application, the term “thru-hole” is meant to include conductive holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as an “internal via” which is internal “captured” by the board's outer layers.
To provide the desired circuit pattern on the board, the art has developed a variety of manufacturing sequences, many of which fall into the broad categories of “subtractive” or “additive” techniques. Common to subtractive processes is the need to etch away (or subtract) metal to expose substrate surface in areas where no circuitry is desired. Additive processes, on the other hand, begin with exposed substrate surfaces (or thin commoning metallization layers for additive electroplate) and build up thereon of metallization in desired areas, the desired areas being those not masked by a previously-applied pattern of plating resist material (e.g., called photo-resist in the printed circuit board field).
Typically, thru-holes are drilled (including mechanically or more recently using lasers) or punched into or through the board at desired locations. Drilling or punching provides newly-exposed surfaces including via barrel surfaces and via peripheral entry surfaces. The dielectric substrate, comprising a top surface, a bottom surface, and at least one exposed via hole surface, consisting partly or entirely of insulating material, is then metallized, generally by utilization of electro-less metal depositing techniques, albeit other deposition processes are also known in the field.
In the manufacture of circuitized printed circuit boards, a dielectric sheet material is typically employed as the base component for the substrate. This base component is usually comprised of an organic material, such as fiberglass-reinforced epoxy resin (also referred to in the field as, simply, “FR4”), polytetrafluoroethylene (e.g., Teflon, a trademark of E.I. duPont deNemours & Company), Driclad dielectric material (Driclad being a trademark of Endicott Interconnect Technologies, Inc.), etc. Since the dielectric substrate is nonconductive, in order to plate on the substrate, the substrate is typically “seeded” and plating then occurs. Such processing is known in the field and further description is not believed necessary, except to add that known metals used for plating the dielectric barrel to form the thru holes include copper, nickel and gold.
Examples of methods of making boards, including providing same with such thru holes, are shown and described in the following U.S. Letters Patents:
The present invention is able to produce a printed circuit board which is capable of having high speed signals pass through the signal conductors thereof, another highly desirable feature required of many of today's newer boards. By the term “high speed” is of course also meant to mean high frequency. Further description is provided below.
The present invention represents a new and unique method of forming conductive thru holes in a printed circuit board in comparison to those above and other processes known in the art. It is believed that such a method, and the board resulting there-from, will represent a significant advancement in the art.DESCRIPTION OF THE INVENTION
It is, therefore, a primary object of the present invention to enhance the printed circuit board art by providing a new and unique method of producing such boards.
It is another object of the invention to provide such a process and resulting board in which several conductive thru holes are formed to interconnect various conductive layers of the board in a new and expeditious manner.
It is still another object of the invention to provide such a process which can be implemented using conventional printed circuit board technologies and thus performed with little or no increased cost over conventional techniques.
According to one aspect of the invention, there is provided a method of making a multilayered printed circuit board (PCB), the method comprising providing a first sub-composite including at least one dielectric layer and at least one opening therein having first and second opposing open end portions and extending substantially through the at least one dielectric layer, positioning a cover on the first opposing open end portion of the at least one opening, aligning the first sub-composite having the at least one opening therein having the cover on the first opposing open end portion with a second sub-composite including at least one dielectric layer such that the cover faces the second sub-composite, positioning a layer of heat-deformable dielectric material between the first and second sub-composites, and bonding the first and second sub-composites and layer dielectric material together using heat and/or pressure sufficient to deform the layer of heat-deformable material, the cover on the at least one opening preventing the dielectric material of the layer of heat-deformable dielectric material from entering the opening.BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in connection with the above-described drawings. It is understood that like numerals will be used to indicate like elements from FIG. to FIG.
As stated above, the term “high speed” as used herein is meant signals of high frequency. Examples of such signal frequencies attainable for the multilayered PCBs defined herein and as produced using the methods taught herein include those within the range of from about 3.0 to about 10.0 gigabits per second (GPS). These examples are not meant to limit this invention, however, because frequencies outside this range, including those higher, are attainable. As further understood from the following, the PCB products produced herein are formed of at least two separate multilayered portions (sub-composites) which have themselves been formed prior to bonding to each other. At a minimum, each of these sub-composites will include at least one dielectric layer and at least one thru-hole” therein, with most likely embodiments including more than one dielectric layer and usually more then one internal conductive layer, in addition to more than one thru-hole. Examples are provided below and are just that (only examples) and the numbers of layers shown and described are not meant to limit the scope of this invention.
As also stated above, the term “thru-hole” is meant to include conductive holes that pass entirely through the board (also referred to in the printed circuit field as plated thru holes or PTHs), “blind vias” which extend from an external surface of the board into a specified conductive layer of the board, as well as “internal vias” (sometimes referred to as “buried vias”) which is internally “captured” by the board's outer layers.
Examples of dielectric materials usable for dielectric layers in the sub-composites taught herein include the aforementioned fiberglass-reinforced epoxy resins (some referred to simply as “FR4” dielectric materials in the art, for the flame retardant (FR) rating of same), polytetrafluoroethylene (e.g., Teflon), and Driclad dielectric material. In addition, polyimides, polyamides, cyanate resins, photo-imageable materials, and other like materials may also be utilized. Examples of conductor materials usable for the conductor layers used in such sub-composites include copper or copper alloys, but may include or comprise additional metals (e.g., nickel, aluminum, etc.) or alloys thereof. Such conductor materials are used to form these layers, which in turn may serve as power, signal and/or ground layers. If as a signal layer, several conductor lines and/or pads may constitute the layer, while if used as power or ground, such layers will typically be of substantially solid construction. Combinations of signal, power and/or ground are possible in one layer.
The resulting multilayered PCBs defined herein are particularly adapted for use in what can be defined as “information handling systems”. By the term “information handling system” as used herein shall mean any instrumentality or aggregate of instrumentalities primarily designed to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, measure, detect, record, reproduce, handle or utilize any form of information, intelligence or data for business, scientific, control or other purposes. Examples include personal computers and larger processors such as servers, mainframes, etc. Understandably, the substrates herein are also adaptable for use in other environments and are not limited to such usage.
By the term “electrical component” as used herein is meant components having pinned connections which project there-from and are adapted for being positioned within receptive holes of a PCB. The most notable example of such a component in an electrical connector which typically includes an electrically insulating housing with a plurality of contacts therein and a plurality of pins extending from the housing for hole placement. The invention is not so limited, however, because the PCBs produced in accordance with the present teachings are adapted for receiving pins and the like from any electrical component having same. Although this invention is particularly adapted for use with pinned components, other components such as conventional surface mount, ball grid array (BGA), land grid array (LGA) and the like may be used on the finished PCB surfaces.
By the term “electrical assembly” as used herein is meant at least one PCB as defined herein in combination with at least one electrical component as defined above electrically coupled thereto and forming part of the assembly.
Finally, by the term “sub-composite” as used herein is meant a structure including at least one dielectric layer. In at least one instance, this term is also meant to define such a structure with at least one thru-hole therein, the thru-hole having an open portion on at least one end thereof which is exposed at the corresponding outer surface of the dielectric. Examples are defined in greater detail herein-below.
Sub-composite 21 as shown in
The two sub-composites 21 and 41 and the interim dielectric layer 51 are now bonded together, preferably using conventional lamination. In one example, the lamination process was conducted at a temperature within the range of from about 180 degrees Celsius (hereinafter also simply referred to as C) to about 200 degrees C., and at a pressure within the range of from about 100 pounds per square inch (hereinafter also simply referred to as PSI) to about 700 PSI. During this lamination, the heat of the process causes the interim layer 51 to deform, meaning that is softens and is compressible to the extent that it “flows” laterally under compression. Significantly, providing layer 51 of a greater thickness than the corresponding land-cover thicknesses T1 enables the interim layer to prevent the deformed material from entering the thru-holes, while still assuring the effective compression of the entire sub-composite and interim layer sub-assembly. In the finally laminated structure, shown in
In the steps shown in
The resulting sub-assembly shown in
The resulting electrical assembly shown in
The embodiment of
Thus there has been shown and described a new and unique method of making a printed circuit board in which openings of different length are formed which do not include dielectric material therein such that the openings may receive pins from an electrical component inserted therein and be electrically coupled thereto so that the pins may make contact with selected conductive elements within and/or upon the board. The formed board is capable of having electrical components inserted from both sides thereof, with relatively minor modification to the process. The resulting board is capable of passing high speed signals. The invention thus represents a significant advancement in the art.
While there have been shown and described what are at present the preferred embodiments of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims.
1. A method of making a multilayered printed circuit board (PCB), said method comprising:
- providing a first sub-composite including at least one dielectric layer and at least one opening therein having first and second opposing open end portions and extending substantially through said at least one dielectric layer;
- positioning a cover on said first opposing open end portion of said at least one opening;
- aligning said first sub-composite having said at least one opening therein having said cover on said first opposing open end portion with a second sub-composite including at least one dielectric layer such that said cover faces said second sub-composite;
- positioning a layer of heat-deformable dielectric material between said first and second sub-composites; and
- bonding said first and second sub-composites and said layer of heat-deformable dielectric material together using heat and/or pressure sufficient to deform said layer of heat-deformable material, said cover on said first open end portion of said at least one opening preventing said dielectric material of said layer of heat-deformable dielectric material from entering said at least one opening.
2. The method of claim 1 further including forming a second opening within said first and second sub-composites when said sub-composites are bonded, said second opening extending substantially through said first and second sub-composites and being longer than said at least one opening.
3. The method of claim 2 wherein said forming of said second opening within said first and second sub-composites is accomplished using a laser.
4. The method of claim 2 wherein said at least one opening is provided as a first conductive thru-hole prior to said positioning of said cover, said method further including providing a conductive material on the internal walls of said second opening to form at least a second conductive thru-hole within said bonded first and second sub-composites.
5. The method of claim 4 further including providing an electrical component having at least two pins extending there-from and inserting a first of said pins within said first conductive thru-hole and a second of said pins within said at least one second conductive thru-hole to form an electrical assembly.
6. The method of claim 5 further including positioning said electrical assembly within a housing to form an information handling system.
7. The method of claim 5 wherein said providing said conductive material on said internal walls of said second opening is accomplished using an electroplating operation.
8. The method of claim 1 further including providing each of said first and second sub-composites with at least one electrically conductive layer therein.
9. The method of claim 8 further including forming circuitry as at least part of said electrically conductive layers.
10. The method of claim 1 wherein said positioning of said cover on said first opposing open end portion of said at least one opening is accomplished using solder-mask material.
11. The method of claim 10 wherein said solder-mask material is provided in the form of a continuous layer and positioned on said first sub-composite, selected portions of said continuous layer of said solder-mask material thereafter being removed such that only the remaining portion thereof covers said at least one opening.
12. The method of claim 1 wherein said bonding of said first and second sub-composites and said layer dielectric material together using said heat and/or pressure sufficient to deform said layer of heat-deformable material is accomplished using a lamination process.
13. The method of claim 1 further including providing an opening with said layer of heat-deformable dielectric material and aligning said opening within said layer of heat-deformable material with said at least one opening within said first sub-composite and said cover positioned on said first opposing open end portion of said at least one opening during said bonding of said first and second sub-composites.
Filed: Jan 19, 2006
Publication Date: Jun 8, 2006
Applicant: Endicott Interconnect Technologies, Inc. (Endicott, NY)
Inventors: Norman Card (Lockwood, NY), Benson Chan (Vestal, NY), Richard Day (Whitney Point, NY), John Lauffer (Waverly, NY), Roy Magnuson (Endicott, NY), Voya Markovich (Endwell, NY)
Application Number: 11/334,445
International Classification: H01L 21/4763 (20060101); H01L 21/44 (20060101); H05K 1/00 (20060101); H05K 1/11 (20060101);