CMOS image sensor using shared transistors between pixels having mirror symmetry

Abstract

A CMOS image sensor that has reduced transistor count is disclosed. The individual pixels are formed by a photodiode and a transfer transistor. An output node receives the signal from the photodiode via the transfer transistor. The output node is shared between multiple pixels. Further, a reset transistor is coupled between a selectable low voltage rail Vss or a high voltage reference Vref and the output node. The gate of an output transistor is then coupled to the output node. Both the reset transistor and output transistors are shared between multiple pixels. Further, the pixels have a mirror symmetry about the output transistor or output node.

Description

RELATED APPLICATIONS

This is a continuation-in-part of U.S. patent application Ser. No. 10/771,839 filed Feb. 4, 2004 to which priority is claimed.

TECHNICAL FIELD

The present invention relates to CMOS image sensors, and more particularly, to a CMOS image sensor having a pixel architecture that allows for sharing of transistors within a vertical column between pixels and having mirror symmetry.

BACKGROUND

Integrated circuit technology has revolutionized various fields, including computers, control systems, telecommunications, and imaging. In the field of imaging, complimentary metal oxide semiconductor (CMOS) active pixel image sensors have made considerable inroads into applications served by charge coupled imaging devices. As noted in U.S. Pat. No. 5,625,210 to Lee et al. (“the '210 patent”), an active pixel sensor refers to an electronic image sensor with active devices, such as transistors, that are associated with each pixel. The active pixel sensor has the advantage of being able to incorporate both signal processing and sensing circuitry within the same integrated circuit because of the CMOS manufacturing techniques.

A popular active pixel structure consists of four transistors and a pinned photodiode. The pinned photodiode has gained favor for its ability to have good color response for blue light, as well as advantages in dark current density and image lag. Reduction in dark current is accomplished by “pinning” the diode surface potential to the Pwell or Psubstrate (GND) through a P+ region. Because of the particular characteristics of pinned photodiodes, it is necessary to incorporate a transfer transistor that is not required in the three-transistor design discussed above.

Still, one disadvantage of this design is that it requires four transistors for each pixel. Thus, a one-megapixel image sensor would require 4 million transistors simply for the imaging array. As higher resolution image sensors become popular, coupled with the need for higher integration densities, it is desirable to implement the “4-transistor” photodiode pixel while reducing the number of required transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of the invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a prior art active pixel.

FIG. 2 is a cross section view of the prior art active pixel of FIG. 1.

FIG. 3 is a schematic diagram of a portion of a column of a prior art image sensor array.

FIG. 4 is a schematic diagram of a portion of a column of an imaging array formed in accordance with the present invention.

FIG. 5 shows an alternative embodiment of the present invention where 4 pixels share an amplifier and reset transistor and there is mirror symmetry.

FIG. 6 shows a top layout view of the embodiment of FIG. 5 where 4 pixels share an amplifier and reset transistor and there is mirror symmetry.

FIG. 7 shows a top layout view of the embodiment of FIG. 5 where 4 pixels share an amplifier transistor and reset transistor and there is mirror symmetry, wherein signal lines are schematically overlayed.

FIGS. 8-10 show alternative layouts of the pixels in accordance with the present invention.

FIG. 11 is a block diagram of a CMOS image sensor formed in accordance with the present invention.

DETAILED DESCRIPTION

The present invention relates to an active pixel design using a photodiode that requires fewer than an average of four transistors per active pixel. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, etc. In other instances, well-known structures or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIGS. 1 and 2 show a prior art active pixel 101 with a pinned photodiode 103, though it can be appreciated that the present invention may be used with other types of light sensitive elements, such as photodiodes, photogates, and partially pinned photodiodes. The pinned photodiode 103 is typically an N-well formed in a P-type substrate. A P+ region is formed atop of the N-well. A transfer gate (also referred to as a transfer transistor) controls the transfer of the signal from the pinned photodiode 103 to an output node 107 (also referred to as a floating node or FD). The output node 107 is connected to the gate of a source-follower transistor 109 (also referred to as a drive, amplifier, or output transistor). This results in the signal on the output node 107 being amplified and placed onto a column line out 111 (also referred to as a column readout line).

A row select transistor (SEL) is used to select the particular pixel to be read out on the column line out 111. The row select transistor is controlled by a row select line. Further, a reset transistor 113 is used to reset the voltage on the sensing node. In order to reduce the leakage current from the silicon surface and kTC noise, the photodiode is typically provided with a pinning P+ surface shield layer at the silicon surface and is completely depleted.

FIG. 3 illustrates a portion of a column from a sensor array using pinned photodiode pixels. In the illustration, column one of the array is shown and the first three rows of the array are shown. As seen, a column line out 111 carries the signals from the rows to readout circuitry (not shown). The row select (SEL) transistors for each pixel are selectively activated one at a time to read out the pixel signals. As seen, for three pixels, twelve transistors are required. Extrapolated out, a one megapixel array would require four million transistors for the imaging array.

The present invention can reduce the amount of transistors required to implement a pinned photodiode sensor array. This reduction is made possible by sharing the source follower transistor 109 and reset transistor between two or more adjacent rows of pixels. This sharing of transistors will reduce greatly the overall number of transistors required to implement a pinned photodiode image sensor.

Specifically, turning to FIG. 4, a portion of an imaging array is shown. This specific portion shows a single column (Column 1) and four rows. In contrast to the prior art, note that adjacent pixels in rows 1 and 2 share a source follower and a reset transistor. Similarly, adjacent pixels in rows 3 and 4 share a source follower and reset transistor. Further, note that in accordance with the present invention there is no row select transistor needed. Instead, the drain of the source follower transistor is connected directly to the column line out 111. Thus, the total number of transistors required for these four pixels is eight. Therefore, on average, each pixel requires only two transistors. This is a significant savings from the four transistors for each pixel in the prior art of FIG. 3.

It should also be noted that the described embodiments herein contemplate a typical image sensor where the pixel array is read out row by row from “top to bottom”. Nevertheless, it is equally possible in other embodiments to read out the pixel array column by column from “left to right”. Indeed, variations in readout scheme can be contemplated, such as where signals from pixels are read out to a row readout line. Thus, the term column readout line is meant to encompass any readout line that follows one dimension of the pixel array.

Further, while it is shown that two pixels share a common reset transistor and source follower transistor, this can be increased to perhaps four or more pixels in a column for greater transistor savings. However, in the embodiment shown in FIG. 4, two pixels in adjacent rows share the reset transistor and source follower transistor.

Moreover, the reset transistor has its upper connection (the drain) connected to either a low voltage V_ss or a high voltage reference V_ref. As will be seen below, the reset transistor will place either V_ss or V_ref onto node A as appropriate for the operation of the present invention. The actual switching between V_ss or V_ref can be easily done using a simple control switch (not shown) as is apparent to those of ordinary skill in the art.

The output node 107 (also referred to Node A) thus is shared between two pixels. The operation of the present invention is explained as follows. When the signal from row 1 is to be read out, the reset transistor is turned on to allow high voltage reference V_ref to be placed on node A. The other node A's for all of the other rows are placed at voltage V_ss through their respective reset transistors. Thus, only node A associated with the row to be read is at high voltage, while all of the other node A's for the other rows are at low voltage.

Next, the reset transistor for the row to be read is turned off and the transfer gate for the row is turned on. The accumulated charge from the photodiode is then transferred to Node A and, along with the high voltage already placed on node A, will modulate the source follower transistor. The transfer gate for the adjacent row pixel (row 2) is off at this time. Thus, the signal produced by the photodiode of the pixel in row 1 modifies the high voltage “base point” and is then amplified by the source follower and the signal is provided onto the column line output 111.

Once this has been done, the reset transistor drain voltage is switched over to low and the reset transistor is turned on. This resets node A to the low reference voltage, such as V_ss.

For reading of the next row (Row 2), the procedure is repeated where the reset transistor places a high voltage onto Node A and then turning on the transfer gate for row 2 is turned on and the signal from the photodiode of the row 2 pixel is transferred to the output node 107 to mix with the high voltage.

At this time, the transfer gate for the row 1 pixel is turned off. The signal on the output node 107 from the row 2 pixel is then amplified by the source follower and the signal is output via the column line out 111. Note that during the read out of rows 1 and 2, Node A of rows 3 and 4 (and all other rows) are held at a low voltage reference, such as V_ss, by turning on the reset transistors for those rows and keeping the reset transistors' drain voltage at low.

The process of reading the remaining rows of the image sensor are the same as for as for rows 1 and 2. Thus, by carefully controlling the timing of the signal readout and of the various transistor switches, the pixel signals can be read out.

In one actual embodiment, the transistors that form the reset transistor and the source follower transistor for a grouping of rows is typically formed in those areas of the imaging array that are outside of the actual photodiode and transfer gate pixel area. This will increase the fill factor of the pixel and provide additional balancing to the operation of the read out circuit.

Turning to FIG. 5, an alternative embodiment of the present invention is shown schematically. As seen in FIG. 5, four adjacent pixels in a common column of a pixel array are arranged vertically. The pixels have photodiodes PD1-PD4. Each of the photodiodes PD1-PD4 are connected to either a floating node FD1 or FD2 through their respective transfer gates TX1-TX4.

As noted above, the embodiments described here refer to shared pixels within a single column. However, the shared pixels can be within a single row. It is just a matter of rotating the pixel array ninety degrees to turn columns into rows. Thus, the terms columns and rows as used herein may be reversed in actual embodiments. For example, the term column readout line may be instead a row readout line where readout of the pixel signals are made horizontal. The generic term readout line is used to describe the signal line used to readout pixel signals, regardless of direction.

As will be seen below in the layout diagram of FIG. 6, adjacent photodiodes PD1 and PD2 share a first floating node FD1. Similarly, adjacent photodiodes PD3-PD4 share a second floating node FD2. Note that in one embodiment, nodes FD1 and FD2 are typically doped diffusion regions formed in the semiconductor substrate. Floating nodes FD1 and FD2 are electrically connected together and to the gate of a source follower output transistor. The combination of FD1, FD2 and the gate of the output transistor collectively can be referred to as the output node. Additionally, a reset transistor is connected to the output node FD and a reset (or reference) voltage V_rs.

Also shown in FIG. 5 are the timing diagrams for the signaling on the various transistors (switches). Note that in the embodiment shown in FIG. 5, a row select transistor is not required and that 4 pixels require a total of 6 transistors.

The timing diagrams shown in FIG. 5 illustrate the timing of the readout when PD1 of the first pixel is selected for readout. The transfer gates TX2-TX4 are all turned off for the duration of the read operation. Initially, the reset transistor is turned on which allows the voltage V_rs to flow to the output node FD. The voltage V_rs can be switched between a V_rs-off position and V_rst-on position. While the reset transistor is on, the voltage V_rs goes from V_rs-off to V_rs-on. This causes the output node FD potential to rise to the level of the V_rst-on. Then, the reset transistor is opened and the output node FD remains at V_rst-on.

Next, the transfer transistor TX1 for the first photodiode PD1 is pulsed on and then off, thereby reading out the signal from PD1. The signal from PD1 lowers the potential on the output node FD and leaves a signal voltage on the output node. The signal on the output node is then used to modulate the source follower transistor and an amplified signal is read out to the column readout line. Finally, the reset transistor is turned back on, the V_rs is brought back to the V_rs-off position, and the output node FD has a voltage that is below the threshold “turn on” voltage for the source follower transistor.

Turning to FIG. 6, a top layout view of FIG. 5 is shown. The four photodiodes PD1-PD4 in the common column are placed vertically. Note that PD1 and PD2 share a common floating node FD1. The transfer gates TX1 and TX2, when turned on, allows signal to flow from their respective photodiodes to the floating node FD1. Importantly, there is mirror symmetry between PD 1 and PD2 about an axis through FD1. In this case, the axis runs through FD1 and between PD1 and PD2. It has been found that this aids in the overall performance of the image sensor.

PD3 and PD4 also have mirror symmetry and share the floating node FD2. Floating nodes FD1 and FD2 are electrically connected to each other and are connected to the gate of the source follower transistor. Note also that there is symmetry vertically around an axis through the source follower transistor.

Further, while it is shown that the output transistor is placed between PD2 and PD3, and the reset transistor is below PD4 (and typically between PD4 and the PD1 of the next lower grouping of pixels), the positions of these two transistors can easily be interchanged.

FIG. 7 illustrates a schematic view of the various control lines for the shares pixels. Further, there are also alternative layout views and possibilities. For example, FIG. 8 shows the gate of the transfer transistors being at the corner of the photodiodes, but still maintaining symmetry about the floating nodes FD1 and FD2. FIG. 9 shows yet another embodiment where the transfer gates have a slightly different shape, but are still at the corners of the photodiode closest to the floating node FD1 and FD2. Once again, symmetry is maintained. Finally, FIG. 9 illustrates the transfer gates arranged vertically along one side of the photodiodes but again maintaining symmetry vertically about the floating nodes FD1 and FD2.

The active pixels described above may be used in a sensor array of a CMOS image sensor 1101. Specifically, FIG. 11 shows a CMOS image sensor formed in accordance with the present invention. The CMOS image sensor includes a sensor array 1103, a processor circuit 1105, an input/output (I/O) 1107, memory 1109, and bus 1111. Preferably, each of these components is formed on a single N-type semiconductor silicon substrate and manufactured to be integrated onto a single chip using standard CMOS processes.

The sensor array 1103 portion may be, for example, substantially similar to the sensor arrays portions of image sensors manufactured by the assignee of the present invention, OmniVision Technologies, Inc., of Sunnyvale, Calif., except that the pixels are replaced with the active pixels disclosed herein.

More specifically, the sensor array 1103 includes a plurality of individual pixels arranged in a two-dimensional array. In operation, as an image is focused onto the sensor array 1103, the sensor array 1103 can obtain the raw image data.

The raw image data is then received by the processor circuit 1105 via bus 1111 to begin signal processing. The processor circuit 1105 is capable of executing a set of preprogrammed instructions (perhaps stored in memory 1107) necessary to carry out the functions of the integrated circuit 1101. The processor circuit 1105 may be a conventional microprocessor, DSP, FPGA or a neuron circuit.

While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changed can be made therein without departing from the spirit and scope of the invention. As one example, one embodiment of the present invention shows 4 pixels in a common column sharing an amplifier transistor and a reset transistor. It could just as easily be reversed wherein 4 pixels in a common row share an amplifier and reset transistor, assuming that the array is read out “column-by-column” through row lines. More generically, the present invention teaches that multiple pixels sharing a common signal readout line can be grouped together to share amplifier and reset transistors.

The present invention has thus been described in relation to a preferred and several alternate embodiments. One of ordinary skill after reading the foregoing specification will be able to affect various changes, alterations, and substitutions of equivalents without departing from the broad concepts disclosed. It is therefore intended that the scope of the letters patent granted hereon be limited only by the definitions contained in appended claims and equivalents thereof, and not by limitations of the embodiments described herein.

Claims

1. An apparatus comprising:

a first pair of pixels formed in a semiconductor substrate and using a common column readout line, each of said pixels comprising:

(1) a light sensing element; and

(2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a first floating node (FD1);

a second pair of pixels formed in the semiconductor substrate and using the common column readout line, each of said pixels comprising:

(1) a light sensing element; and

(2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a second floating node (FD2);

an output transistor that has its gate electrically connected to said FD1 and FD2, the combination of said FD1, FD2, and said gate of the output transistor forming an output node; and

a reset transistor coupled between a voltage reference and said output node.

2. The apparatus of claim 1 wherein the voltage reference is selectable between an off state VRST-OFF or an on state VRST-ON.

3. The apparatus of claim 1 wherein said light sensing element is a photodiode, photogate, or pinned photodiode, or partially pinned photodiode.

4. The apparatus of claim 1, wherein the output transistor is connected to the column readout line without the use of a row select transistor.

5. The apparatus of claim 1, further wherein said FD1 and FD2 are two separate diffusion regions formed in said semiconductor substrate.

6. The apparatus of claim 1, wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the output transistor.

7. The apparatus of claim 1, wherein the pixels within said first pair of pixels have mirror symmetry to each other about said FD1.

9. A method of forming a portion of a pixel array comprising:

forming a first pair of pixels in a semiconductor substrate that use a common column readout line, each of said pixels comprising:

(1) a light sensing element; and

(2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a first floating node (FD1);

forming a second pair of pixels in the semiconductor substrate that use the common column readout line, each of said pixels comprising:

(1) a light sensing element; and

(2) a transfer transistor that selectively allows the transfer of signal from said light sensing element to a second floating node (FD2);

forming an output transistor that has its gate electrically connected to said FD1 and FD2, the combination of said FD1, FD2, and said gate of the output transistor being an output node; and

forming a reset transistor coupled between a voltage reference and said output node.

10. The method of claim 9 wherein the voltage reference is selectable between an off state VRST-OFF or an on state VRST-ON.

11. The method of claim 9, wherein the output transistor is connected to the column readout line without the use of a row select transistor.

12. The method of claim 9, further including forming said FD 1 and FD2 as two separate diffusion regions formed in said semiconductor substrate.

13. The method of claim 9, wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the output transistor.

14. The method of claim 9, wherein said first pair of pixels and said second pair of pixels have mirror symmetry to each other about any portion of the reset transistor.

15. The method of claim 9, wherein the pixels within said first pair of pixels have mirror symmetry to each other about said FD 1.

16. A set of pixels in a pixel array comprising:

a first pair of adjacent pixels having mirror symmetry about an axis through a first floating node (FD1), said first pair of adjacent pixels having a photodiode and a transfer gate;

a second pair of adjacent pixels having mirror symmetry about an axis through a second floating node (FD2), said second pair of adjacent pixels having a photodiode and a transfer gate, wherein said first pair of adjacent pixels and said second pair of adjacent pixels are adjacent to each other and share a common readout line;

an amplifier transistor having its gate connected to FD1 and FD1 to form an output node; and

a reset transistor for resetting said output node to a reset voltage VRST.

17. The set of pixels of claim 16 wherein either said amplifier transistor or said reset transistor is located between said first pair of pixels and said second pair of pixels and there is mirror symmetry of said first pair of pixels and said second pair of pixels about an axis through said amplifier transistor or said reset transistor.

18. The set of pixels of claim 16 wherein the reset voltage is selectable between an off state VRST-OFF or an on state VRST-ON.

19. The set of pixels of claim 16, wherein the output transistor is connected to the readout line without the use of a row select transistor.

20. The set of pixels of claim 16, further wherein said FD1 and FD2 are two separate diffusion regions formed in said semiconductor substrate.