METHODS OF IMPLEMENTING AND ENHANCED SILICON-ON-INSULATOR (SOI) BOX STRUCTURES
Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
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The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures.
DESCRIPTION OF THE RELATED ARTSilicon-on-insulator (SOI) transistors provide better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. Superior performance of SOI transistors at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. A buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, reducing junction capacitance.
Various SOI transistor arrangements are known. For example, Wei et al., U.S. patent application Publication No. US 2003/0223258 published Dec. 4, 2003, and assigned to the present assignee, discloses a method comprising forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In other embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode.
While the above disclosed methods and silicon-on-insulator (SOI) structures provide improvements over prior art arrangements, a need exists for enhanced SOI devices and methods for manufacturing thereof. It is desirable to provide new backgate processing techniques and enhanced SOI BOX structures.
SUMMARY OF THE INVENTIONPrincipal aspects of the present invention are to provide enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures. Other important aspects of the present invention are to provide such enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures.
In accordance with one embodiment of the invention, a silicon-on-insulator (SOI) structure is provided including a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. The silicon substrate layer is thinned and an oxygen implant step is performed from the backside into the thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer.
In accordance with features of one embodiment of the invention, the oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
In accordance with features of one embodiment of the invention, a gate oxide and a gate electrode are formed over the active region above the backgate. Doping, formation and activation of each respective source/drain region and the gate electrode are provided for the SOI transistor
In accordance with features of one embodiment of the invention, an image of the gate electrode is larger than a backgate image, whereby gate alignment problems of the SOI transistor are minimized. A programmable body contact is provided, for example, by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.
In accordance with features of one embodiment of the invention, a doping implant into the active layer above the backgate forms a doped plate region from the active layer. A contact formation on the backgate and doped plate region provides respective anti-fuse (AF) connections. A voltage supply source is connected between the respective anti-fuse (AF) connections in a fuse programming step forming a conduction path between the backgate and doped plate region.
BRIEF DESCRIPTION OF THE DRAWINGSThe present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein:
In accordance with features of preferred embodiments, novel backgate processing methods and backgate structures are provided. The novel backgate processing methods and backgate structures provide preferential Si island strain for both NF and PF device mobility enhancement. Simultaneous thin and thick BOX regions are provided for minimized junction capacitance, and improved backgate coupling. A novel backgate Anti-Fuse structure using a Thin/Thick gate SOI device and another backgate Anti-Fuse (AF) structure of one of preferred embodiment is arranged for providing a programmable body contact.
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Qualitative analysis or simulation has been performed for a method for operating the device 1502, where the body contact of the SOI transistor and the gate are used to set the electric field across the back oxide in order to create oxide damage or breakdown. What this simulation shows is that for moderate well/halo doses and 90 nm type oxides (˜1 nm) and potentials, for example, 1.1 V across the oxide, sufficient field strength was achieved for causing oxide breakdown, such as electric field strength in excess of 10 MV/cm. Also the back oxide could be made intrinsically weaker by design to assist in this process.
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While the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing, these details are not intended to limit the scope of the invention as claimed in the appended claims.
Claims
1. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures comprising the steps of:
- providing a thin buried oxide (BOX) layer under a device channel in a silicon substrate layer and a pad oxide layer carried by the active layer;
- thinning the silicon substrate layer;
- performing an oxygen implant step from the backside into the thinned silicon substrate layer; and
- forming thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer.
2. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 1 wherein the oxygen implant step forms an isolated region near the oxygen implants.
3. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 2 includes a backside implant step for selectively doping the isolated region to form a backgate for an SOI device being formed, the SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
4. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 3 includes forming a gate oxide and a gate electrode over the active region above the backgate.
5. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 4 includes doping each respective source/drain region and the gate electrode for forming the SOI transistor.
6. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 1 includes forming a gate oxide and a gate electrode over the active region above the backgate, said gate electrode having an image larger than a backgate image.
7. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 6 includes doping each respective source/drain region and the gate electrode for forming the SOI transistor.
8. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 7 includes forming a programmable body contact by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.
9. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 3 includes providing a doping implant into the active layer above the backgate to form a doped plate region from the active layer.
10. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 9 includes forming a respective contact on the backgate and doped plate region to form respective anti-fuse (AF) connections.
11. A method for implementing enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures as recited in claim 10 includes applying a voltage potential between the respective anti-fuse (AF) connections in a fuse programming step forming a conduction path between the backgate and doped plate region.
12. A silicon-on-insulator (SOI) buried oxide (BOX) structure comprising:
- a thin buried oxide (BOX) layer;
- an active channel region over said thin buried oxide (BOX) layer;
- a pair of spaced apart thick buried oxide (BOX) regions;
- an isolated region between said pair of spaced apart thick buried oxide (BOX) regions; said isolated region being selectively doped for forming a backgate for an SOI device to be formed.
13. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 12 wherein the SOI device to be formed includes a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices
14. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 12 wherein the SOI device to be formed is a SOI transistor including a gate oxide and a gate electrode over the active region above the backgate.
15. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 14 wherein the gate electrode has a gate image larger than a backgate image.
16. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 14 includes a respective source/drain region above respective thick buried oxide (BOX) regions forming the SOI transistor.
17. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 16 includes a programmable body contact for creating a resistive path between the active layer and the backgate; said programmable body contact being formed by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential.
18. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 12 wherein the SOI device to be formed is an anti-fuse (AF) device including a doped plate region in the active layer above the backgate.
19. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 18 includes a respective contact on the backgate and doped plate region to form respective anti-fuse (AF) connections.
20. A silicon-on-insulator (SOI) buried oxide (BOX) structure as recited in claim 19 includes a programmable fuse conduction path between the backgate and doped plate region; said programmable fuse conduction path formed by applying a voltage potential between the respective anti-fuse (AF) connections.
Type: Application
Filed: Apr 14, 2005
Publication Date: Oct 19, 2006
Applicant: International Business Machines Corporation (Armonk, NY)
Inventors: Toshiharu Furukawa (Essex Junction, VT), Carl Radens (LaGrangeville, NY), William Tonti (Essex Junction, VT), Richard Williams (Essex Junction, VT)
Application Number: 11/106,004
International Classification: H01L 21/84 (20060101); H01L 21/00 (20060101);