Polysilicon Conductor Width Measurement for 3-Dimensional FETs
An apparatus and method is disclosed for determining polysilicon conductor width for 3-dimensional field effect transistors (FinFETs). Two or more resistors are constructed using a topology in which polysilicon conductors are formed over a plurality of silicon “fins”. A first resistor has a first line width. A second resistor has a second line width. The second line width is slightly different than the first line width. Advantageously, the first line width is equal to the nominal design width used to make FET gates in the particular semiconductor technology. Resistance measurements of the resistors and subsequent calculations using the resistance measurements are used to determine the actual polysilicon conductor width produced by the semiconductor process. A composite test structure not only allows calculation of the polysilicon conductor width, but provides proof that differences in the widths used in the calculations do not introduce objectionable etching characteristics of the polysilicon conductors.
Latest IBM Patents:
This patent application is a divisional of a patent application of the same title, Ser. No. 10/944,622filed on Sep. 17, 2004, which is incorporated herein by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The current invention generally relates to semiconductor products. More specifically, the present invention relates to making electrical resistance measurements that allow accurate measurement of the width of polysilicon conductors used in making FET (field effect transistor) gates in a FinFET semiconductor process.
2. Description of the Related Art
Field Effect Transistors (FETs) have been the dominant semiconductor technology used to make Application Specific Integrated Circuit (ASIC) chips, microprocessor chips, Static Random Access Memory (SRAM) chips, and the like for many years. In particular, Complementary Metal Oxide Semiconductor (CMOS) technology has dominated the semiconductor process industry for a number of years.
Technology advances have scaled FETs on semiconductor chips to increasingly small dimensions, allowing power per logic gate to be dramatically reduced, and further allowing a very large number of FETs to be fabricated on a single semiconductor chip. Scaling of FETs is currently running into limits. Gate oxides have become thin enough that leakage occurs through the gate oxides. Further scaling of gate oxide thickness will bring an exponential increase in leakage. Power dissipated by leakage currents has become a significant portion of total chip power, and an exponential increase in leakage results in unacceptable power dissipation for many types of chips.
Silicon on Insulator (SOI) processes have reduced FET source and drain capacitances, resulting in an improved powerperformance ratio for CMOS chips fabricated in an SOI process. However, conventional SOI processes are reaching fundamental limits, resulting in undesirable effects such as the leakage effects mentioned above. Therefore, innovative new ways to make CMOS devices are being created. Associated apparatus and methods are also needed to test the innovative devices at various steps in the process of making them.
A conventional SOI FET is shown in
Resistor RA is simply a rectangle of polysilicon having a width “W” and a length “L”. The Sheet resistance of polysilicon conductor 12 is Rs ohms/square. Therefore,
RA=Rs*L/W (1)
Similarly, resistor RB is designed with a length of L (other lengths are possible, but L is a convenient dimension for resistor RB as well as resistor RA. Resistor RB, in the illustrative
RB=⅙*Rs*L/Leff (2)
Rs is “unknown” (without measurement of further test structures to determine the sheet resistivity of the polysilicon), but is the same for both resistors RA and RB on any particular semiconductor chip. Resistors RA and RB are readily measured for resistance values by suitable resistance measurements through contacts 11A, 11B, and 11C.
Rs=RA*W/L (3)
(rearranging (1))
Leff=Rs*L/(6*RB); (rearranging (2)); then, using Rs from (3) in (4), (4)
Leff=RA*W(6*RB) (5)
Note that the use of L1 for both resistors RA and RB conveniently eliminated L in the final equation. W still remains, and varies slightly from semiconductor chip to another semiconductor chip due to process variations, but W is made large enough that the process variations in W for a particular chip will have an insignificant effect on the determination of Leff.
Although only six
The test structure and method of Leff determination described work very well when the polysilicon line has a substantially constant thickness.
Prior art
Therefore, there is a need for a method and apparatus that allow easy and accurate determination of channel length of a FinFET using resistance measurements.
SUMMARY OF THE INVENTIONThe current invention teaches a test structure for easily determining the finished width of a polysilicon conductor (and therefore the FET channel length defined by the polysilicon conductor width) that serves as a gate electrode of a FinFET, a three dimensional field effect transistor. The finished width of a polysilicon conductor is the finished width of the polysilicon conductor after completion of processing the polysilicon conductor in a semiconductor process.
In an apparatus embodiment of the invention, two or more resistors are formed, each resistor having two contacts that allow resistive measurements to be taken. Each of the two or more resistors is routed over one or more semiconductor (typically silicon) “fins”, in a direction substantially orthogonal to the direction of the fins as viewed from the top. Each of the two or more resistors is constructed with one or more fingers of the polysilicon conductor. A first of the two or more resistors is designed with fingers of a first width of the polysilicon conductor. A second of the two or more resistors is designed with fingers of a second width, with a known, but slight, difference from the first width. In embodiments shown and described, a third resistor is implemented. The third resistor is designed with fingers of a third width, the third width slightly different from both the first width and the second width. Calculations made using measured resistance of each of the resistors determine the widths of the fingers in the resistors. Those skilled in the art will understand that table lookup or other suitable techniques could also be used, instead of a calculation, to determine the widths of the fingers, using the resistance of each of the resistors. Advantageously, the first width is designed to be equal to the nominal width of polysilicon conductors used to make FET gates on the semiconductor chip, therefore providing the value of the effective channel length for FETs on a particular chip made in a semiconductor process, since polysilicon conductor width is the primary determinant of the effective channel length of an FET. Those skilled in the art will recognize that although two resistors suffice to make a determination of the polysilicon conductor width, accuracy is improved by implementing more than two resistors.
A method embodiment of the invention includes the steps of making a plurality of “fins” suitable for making FinFET transistors; making two or more resistors of polysilicon, each of the resistors comprising one or more polysilicon fingers; each of the resistors configured to travel over the plurality of fins in a direction substantially orthogonal to the fins as viewed from the top; each resistor having polysilicon fingers of different width. The method continues with the steps of measuring a resistance of each of the two or more resistors, and computing the width of the polysilicon fingers, using the resistances measured. The step of measuring the resistance can be done prior to forming a silicide on the polysilicon fingers or after forming a silicide on the polysilicon fingers.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in detail with reference to the figures. It will be appreciated that this description and these figures are for illustrative purposes only, and are not intended to limit the scope of the invention. In particular, various descriptions and illustrations of the applicability, use, and advantages of the invention are exemplary only, and do not define the scope of the invention. Accordingly, all questions of scope must be resolved only from claims set forth elsewhere in this disclosure.
The current invention teaches a test structure apparatus that provides for easily determining a processed width of a polysilicon conductor that travels over one or more semiconductor “fins” on a FinFET semiconductor chip. A processed width is a final width of the polysilicon conductor after completion of a polysilicon etching step in a semiconductor process. The one or more semiconductor fins rise from a dielectric surface on the semiconductor chip. Although fins are typically higher than they are wide, the present invention is not limited to any particular height to width ratio.
In an embodiment, two or more resistors are formed, each resistor having two contacts that allow resistive measurements to be taken. Two resistors are required in the method and apparatus described below. Additional resistors allow improved accuracy in determination of the width of the polysilicon conductors. The resistors are routed over the fins, substantially orthogonally to the fins as viewed from the top.
Three resistors are used for exemplary purposes in the following description, but any number of resistors where the number is two or more is contemplated.
Each of the three resistors is routed, at least in part, over one or more silicon “fins”, substantially orthogonally to the fins as viewed from the top; i.e., looking perpendicularly down toward the dielectric surface. Each of the three resistors is constructed with one or more polysilicon conductor fingers. A first of the three resistors is designed with one or more fingers of a first width of the polysilicon conductor. A second of the three resistors is designed with one or more fingers of a second width, the second width slightly different from the first width. A third of the three resistors is designed with one or more fingers of a third width, the third width slightly different from both the first width and the second width. Calculations made using measured resistance of each of the three resistors and the known slight differences in widths determine the widths of the fingers in the three resistors. Those skilled in the art will understand that table lookup or other techniques employing the measured resistance of each of the three resistors and the known slight differences in widths can also be used in determining the widths of the fingers in the three resistors.
Advantageously, the first width is designed to be equal to the typical designed width of polysilicon conductors used to make FET gates electrodes on the semiconductor chip, therefore providing the value of the typical effective FET channel length for a particular chip made in a semiconductor process. Polysilicon conductor width is the primary determinant of the effective channel length in a FinFET.
Turning now to
In a process step after the creation of fins 50, polysilicon conductors are formed orthogonal to fins 50, following the process of making FinFETs. A first resistor, R1, comprises one or more polysilicon conductors 51 (for simplicity of illustration, only one polysilicon conductor 51 is circled and referenced), each polysilicon conductor 51 having a design width L1. A design width of L1 will result in a processed width that may differ from the design width. For example, a design width L1 of 120 (measured in arbitrary units) may result in a processed width of 100. Processing tolerances may cause the processed width to vary from, for example, 80 to 120. For clarity, L1P will be used to denote the processed width of a polysilicon conductor having a design width of L1.
It is important to note that process etching of polysilicon conductors has processing tolerances, as does any manufacturing process. However, etching of polysilicon conductors affects all polysilicon conductors by substantially the same amount, rather than proportional to width of the polysilicon conductors. Therefore, if a polysilicon conductor has a design width of 100 (arbitrary units), and an etching process causes the processed width to be 95 units, a polysilicon conductor having a design width of 110 units will have a processed width to be 105 units; that is, both the 100 unit and the 110 unit polysilicon conductor were reduced by a particular pass through the etching process by 5 units. That is, L1+dL (“dL” represents a small difference in width added to design width L1) results in a processed width of L1P+dL. Polysilicon conductors of extremely disparate widths may have slightly different etching characteristics, and a maximum design width difference parameter is introduced later to ensure that the dL values do not introduce substantially different etching characteristics.
A contact C1 is provided at a first end of R1. A contact Cx is provided at a second end of R1. Resistance of R1 can be made by conventional resistance measurement means coupled to contacts C1 and Cx.
A second resistor, R2, comprises one or more polysilicon conductors 52, each polysilicon conductor 52 having a design width, L2+L1−dL. dL is intended to denote a small width difference that does not introduce unacceptable width dependent “second order” polysilicon etching effects. For example, a very wide polysilicon conductor may have significantly different etch characteristics than a typical narrow polysilicon conductor used to make FinFET gate electrodes. Discussion of a maximum design width difference will be given later. In the example, design width L2 is designed to be slightly narrower than the design width L1. A contact C2 is provided at a first end of R2. Contact Cx is provided at a second end of R2. Although a single contact Cx is shown for simplicity of illustration, those skilled in the art will appreciate that separate contacts could be used instead of a single contact. When a resistive measurement is made of R2, the probe of the ohmmeter (or other suitable resistance measuring technique, such as “force a current; measure a voltage”) at second end of R2 should be placed on a portion of contact Cx at the second end of R2.
If resistance measurement is made later in the process, when metal (aluminum, copper, or other suitable low resistance conductor) couples contacts Cx, C1, C2, and C3, resistance measurements can be made at probe points further away, subject to constraints of known resistance measurement techniques, or even be made electronically by resistance measurement circuitry on the chip (not shown).
Etching of polysilicon conductors is affected by absence or presence of other polysilicon conductors nearby. A polysilicon conductor of a particular design width having no nearby other polysilicon conductors will have a processed width narrower than a polysilicon conductor of the same particular design width but having other polysilicon conductors nearby. Dummy polysilicon conductors 54 are shown in test structure 55 to ensure that all polysilicon conductor fingers in resistors R1, R2, R3 have polysilicon conductor “neighbors”. More than one polysilicon conductor 54 maybe implemented if needed to ensure that all polysilicon conductor fingers in resistors R1, R2, R3 have similar etching properties. Dummy polysilicon conductors 54 are optional if other circuitry nearby provides polysilicon conductors. Although, for simplicity, dummy polysilicon conductors 54 are shown having no contacts, in general, one or more contacts would be provided, with the contacts coupling dummy polysilicon conductors 54 to a voltage supply. Note that although resistors R1, R2, and R3 are shown be slightly separated for easy identification of the resistors (i.e., having a gap between the nearest polysilicon conductors of resistors R1 and R2, or the nearest polysilicon conductors of resistors R2 and R3), advantageously, all the polysilicon conductors (including dummy polysilicon conductors 54) shown are equally spaced to ensure similar etching of the polysilicon conductors.
In an embodiment illustrated in
Similarly, a third resistor, R3, comprises one or more polysilicon conductors 53, each polysilicon conductor 53 having a design width L3=L1+dL. In the example, design width L3 is designed to be slightly wider than the design width L1. A contact C3 is provided at a first end of R3. Contact Cx is shown to contact a second end of R3.
The above exemplary design widths of R1, R2, and R3 are illustrative only. For example, if design width L2 could be designed to be slightly larger than the design width L1 (i.e., L2=L1+dL), and the design width L3 could be designed to be slightly larger than design width L2 (i.e., L3=L2+dL).
Equations for the values of R1, R2, and R3 shown in
R1=Rs*L0L1P/N (1)
R2=Rs*L0(L1P −dL)N (2)
R3=Rs*L0(L1P+dL)N (3)
From (1) and (2),
L1P=R2*dL/(R2−R1) (4)
From (1) and (3),
L1P=R3*dL/(R1−R3) (5)
The resistances of R1, R2, and R3 are measured resistances, as described above, and are therefore known. dL, as described above, is a small design perturbation in design width of the polysilicon conductor fingers in R2 and R3 versus R1 as described earlier, and is therefore also known. Therefore, L1P, the processed width of the fingers 51 of R1 is as calculated in (4) and (5).
It will be understood that either (4) or (5) provides a calculated value of the processed width L1P, and therefore only two resistors (i.e., R1 and R2; R1 and R3; R2 and R3) are required, improved confidence and accuracy in determination of L1P is achieved by having more than two resistors.
It will also be understood that different values of dL can be used to ensure that etching properties of the polysilicon conductor are not adversely affecting the determination of L1P.
Those skilled in the art will understand that the etching test structure described above can also be embodied as an etching test structure having more resistors of increasing perturbation in a single test structure. Etching test structure 60A, as shown in
As with composite test structure 60, composite test structure 60A provides the designer the ability to ensure that width related polysilicon etching effects are not affecting the calculation of L1P, the processed width of a polysilicon finger having a design width L1. As with test structure 55, dummy polysilicon conductors 54 should be added where required to ensure that all polysilicon fingers in resistors R10, R11, R12, R13, and R14 have a nearby polysilicon conductor.
A method embodiment of the invention is illustrated as a flowchart in
Claims
1. A method of determining a finished width of a polysilicon conductor routed over fins of a FinFET on a semiconductor chip comprising the steps of:
- creating one or more semiconductor fins on a semiconductor chip;
- constructing a first resistor having one or more fingers having a first design width, the fingers constructed of polysilicon and routed, at least in part, substantially orthogonally over the one or more fins;
- constructing a second resistor having one or more fingers having a second design width that is different from the first design width, the fingers constructed of polysilicon and routed, at least in part, orthogonally over the one or more fins;
- measuring a first resistance value of the first resistor;
- measuring a second resistance value of the second resistor; and
- determining the finished width of the first design width, using the first design width, the second design width, the first resistance value and the second resistance value.
2. The method of claim 1, further comprising the step of ensuring that the one or more fingers of the first resistor have substantially the same process each properties as the one or more fingers of the second resistor.
3. The method of claim 2, further comprising the steps of:
- creating one or more additional resistors having one or more fingers having design widths different enough from the first design width and the second design width to provide information as to design widths that result in different polysilicon etch characteristics from the first design width and the second design width, the fingers constructed of polysilicon and routed, at least in part, orthogonally over the one or more fins;
- measuring resistance values of the one or more additional resistors;
- determining estimates of the finished width of the first design width using the resistance values of the one or more additional resistors and the resistance value of the first resistor; and
- determining a maximum design width difference.
4. The method of claim 3, the step of determining a maximum design width difference further comprising the step of creating the one or more additional resistors having design width differences beyond which a determination of the finished width of the first design width differ from determination of the finished width of the first design width using design widths less than the maximum design width difference by a predetermined amount.
5. The method of claim 1, further comprising the steps of:
- constructing a third resistor having one or more fingers having a third design width that is different from the first design width and different from the second design width, the fingers constructed of polysilicon and routed, at least in part,
- orthogonally over the one or more fins;
- measuring a third resistance value of the third resistor;
- determining the finished width of the first design width, using the first design width, the second design width, the third design width, the first resistance value, the second resistance value, and the third resistance value.
Type: Application
Filed: Feb 1, 2007
Publication Date: Jun 7, 2007
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Richard Donze (Rochester, MN), William Hovis (Rochester, MN), Terrance Kueper (Rochester, MN), John Sheets (Zumbrota, MN), Jon Tetzloff (Rochester, MN)
Application Number: 11/670,008
International Classification: H01L 21/66 (20060101);