DYNAMIC RANDOM ACCESS MEMORY CELL LAYOUT AND FABRICATION METHOD THEREOF
A dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof. An active area comprises two vertical transistors, a common bitline contact and two deep trenches. The first vertical transistor is formed on a region where the first deep trench is partially overlapped with the first gate conductive line. The second vertical transistor is formed on a region where the second deep trench is partially overlapped with the second gate conductive line.
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1. Field of the Invention
The invention relates to a memory cell of a semiconductor device, and more particularly to a dynamic random access memory (DRAM) cell layout for arranging deep trenches and active areas and a fabrication method thereof.
2. Description of the Related Art
A dynamic random access memory (DRAM) cell typically includes a memory cell coupled to a storage capacitor. Generally the storage capacitor is formed within a deep trench etched into a semiconductor substrate. The storage capacitor is accessed using an access transistor which allows charge to be stored in the storage capacitor or retrieves charge from the storage capacitor depending on whether the desired action is a read or write function. For a buried strap type trench capacitor, dopant outdiffusion near a wordline can cause a short channel effect in the access transistor channel, thus reducing subthreshold conduction and causing a fail in retention time.
Accordingly, an object of the present invention is to provide a DRAM cell layout and a fabrication method thereof to improve subthreshold conduction and retention time performance.
According to the object of the invention, a dynamic random access memory cell layout has a first gate conductor pair and a second gate conductor pair extending along a first direction, in which each gate conductor pair comprises a first gate conductive line and a second gate conductive line. A bitline pair has a first bitline and a second bitline, which extend along a second direction and intersect the gate conductor pairs. Corresponding to the first bitline, a first active area extends along the second direction to cross the first gate conductor pair. Corresponding to the second bitline, a second active area extends along the second direction to cross the second gate conductor pair. Each active area has a first deep trench and a second deep trench formed in a substrate underneath the first gate conductive line and the second gate conductive line, respectively. A bitline contact is formed between the first gate conductive line and the second gate conductive line to be electrically connected to the corresponding bitline. A common source/drain region is formed in the substrate between the first gate conductive line and the second gate conductive line to be electrically connected to the bitline contact. A first vertical transistor and a second vertical transistor are formed overlying the first deep trench and the second deep trench, respectively. Each vertical transistor has a buried strap out-diffusion region formed in the substrate adjacent to one sidewall of the deep trench.
DESCRIPTION OF THE DRAWINGSThe present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention.
FIGS. 7A˜7L are cross-sections of a fabrication method for above-described deep trenches and vertical transistors.
DETAILED DESCRIPTION OF THE INVENTION First Embodiment
The first active area AA1 extends along the first bitline BL1 to cross the first gate conductive line GC1 and a second gate conductive line GC2 of the second gate conductor pair P2, and comprises two vertical transistors T1 and T2, a common bitline contact BC and two deep trenches DT1 and DT2. The first vertical transistor T1 is formed on a region where the first deep trench DT1 is partially overlapped with the first gate conductive line GC1. The second vertical transistor T2 is formed on a region where the second deep trench DT2 is partially overlapped with the second gate conductive line GC2.
The second active area AA2 extends along the second bitline BL2 to cross the first gate conductive line GC1 and a second gate conductive line GC2 of the first gate conductor pair P1. Alternatively, the second active area AA2 crosses the first gate conductive line GC1 and a second gate conductive line GC2 of the third gate conductor pair P3. The second active area AA2 comprises two vertical transistors T1 and T2, a common bitline contact BC and two deep trenches DT1 and DT2. The first vertical transistor T1 is formed on a region where the first deep trench DT1 is partially overlapped with the first gate conductive line GC1. The second vertical transistor T2 is formed on a region where the second deep trench DT2 is partially overlapped with the second gate conductive line GC2.
The DRAM cell layout of deep trenches and active areas of the second embodiment is substantially similar to that of the first embodiment, with the similar portions omitted herein. The different portion is the profile of the overlapping region between the deep trench and the vertical transistor. In the first embodiment, on the overlapping region between the deep trench and the vertical transistor, the sidewall profile of the deep trench is a line. Comparatively, in the second embodiment, on the overlapping region between the deep trench and the vertical transistor, the sidewall profile of the deep trench comprises at least three edges. For example, a five-edge sidewall profile, such as a -shaped sidewall.
Preferably, on an active area AA, the first deep trench DT1 is partially overlapped with the first gate conductive line GC1, and the first deep trench DT1 comprises a -shaped sidewall within the overlapping portion therebetween. Similarly, the second deep trench DT2 is partially overlapped with the second gate conductive line GC2, and the second deep trench DT2 comprises a -shaped sidewall within the overlapping portion therebetween. Therefore, the vertical channel region between the common source/drain region S/D and the buried strap out-diffusion region BS becomes a multilateral structure, viewed as a three-dimensional design, which can further improve subthreshold conduction and retention time performance.
Third Embodiment
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While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims
1-18. (canceled)
19. A transistor, comprising:
- a source/drain region;
- a buried strap out-diffusion region adjacent to one sidewall of a deep trench; and
- a bended gate structure having a bended gate and a bended gate insulating layer, wherein the bended gate structure comprises a first portion extending along a first direction and a second portion extending along a second direction intersecting with the first direction, wherein the first portion of the bended gate is adjacent to the source/drain region and the second portion of the bended gate is adjacent to the buried strap out-diffusion region, and on an overlapping region between the deep trench and the bended gate structure, the sidewall profile of the deep trench comprises at least three edges.
20. The transistor as claimed in claim 19, wherein the deep trench is a trench of a deep trench capacitor.
21. The transistor as claimed in claim 19, wherein the bended gate is adjacent to a shallow trench isolation.
22. The transistor as claimed in claim 19, further comprising a bit line contact electrically contacting the source/drain region.
23. The transistor as claimed in claim 21, wherein the bit line contact is separated from the bit line contact by a spacer on a sidewall of the bended gate.
24. The transistor as claimed in claim 19, wherein the bended gate is L shaped in a cross section view.
25. The transistor as claimed in claim 19, wherein the bended gate insulating layer is L shaped in a cross section view.
26. The transistor as claimed in claim 19, wherein the first direction and the second direction are perpendicular.
27. The transistor as claimed in claim 19, wherein the source/drain region is disposed in a substrate.
28. The transistor as claimed in claim 27, wherein the first direction is parallel to the substrate surface.
29. The transistor as claimed in claim 19, wherein the second direction is parallel to a sidewall of the trench.
30. A memory device, comprising a deep trench capacitor and a transistor controlling the deep trench capacitor, wherein the transistor is as claimed in claim 19.
31. The transistor as claimed in claim 19, wherein on the overlapping region between the deep trench and bended gate structure, the sidewall profile of the deep trench comprises at least five edges.
32. A memory device, comprising:
- a source/drain region;
- a buried strap out-diffusion region adjacent to one sidewall of a deep trench; and
- a bended gate structure having a bended gate and a bended gate insulating layer, wherein the bended gate structure comprises a first portion extending along a first direction and a second portion extending along a second direction intersecting with the first direction, wherein the first portion of the bended gate is adjacent to the source/drain region and the second portion of the bended gate is adjacent to the buried strap out-diffusion region, and on an overlapping region between the deep trench and the bended gate structure, the sidewall profile of the deep trench is -shaped.
Type: Application
Filed: Mar 16, 2007
Publication Date: Jul 5, 2007
Applicant: NANYA TECHNOLOGY CORPORATION (TAOYUAN)
Inventors: Ming-Cheng Chang (Taoyuan Hsien), Tieh-Chiang Wu (Ilan), Yi-Nan Chen (Taipei), Jeng-Ping Lin (Taoyuan)
Application Number: 11/687,573
International Classification: H01L 29/788 (20060101);