Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.

Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

Abstract: Semiconductor devices and methods for forming a semiconductor device are disclosed. The method includes providing a substrate prepared with a memory cell region. A first gate structure is formed on the memory cell region. An isolation layer is formed on the substrate and over the first gate structure. A second gate structure is formed adjacent to and separated from the first gate structure by the isolation layer. The first and second gate structures are processed to form at least one split gate structure with first and second adjacent gates. Asymmetrical source and drain regions are provided adjacent to first and second sides of the split gate structure.

Abstract: A nonvolatile memory device includes a unit cell with a transistor and a capacitor. The transistor is disposed on a substrate having a tunneling region and a channel region and includes a floating gate crossing both the tunneling region and the channel region. The capacitor is coupled to the floating gate.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: Memory cells formed to include a charge storage node having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems.

Abstract: A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge<Ltop and Lgate<Ltop”.

Abstract: In one embodiment, there is provided a nonvolatile semiconductor storage device. The device includes: a plurality of nonvolatile memory cells. Each of the nonvolatile memory cells includes: a first semiconductor layer including a first source region, a first drain region, and a first channel region; a block insulating film formed on the first channel region; a charge storage layer formed on the block insulating film; a tunnel insulating film formed on the charge storage layer; a second semiconductor layer formed on the tunnel insulating film and including a second source region, a second drain region, and a second channel region. The second channel region is formed on the tunnel insulating film such that the tunnel insulating film is located between the second source region and the second drain region. A dopant impurity concentration of the first channel region is higher than that of the second channel region.

Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract: Non-volatile memory devices, and fabricating methods thereof, include a floating gate over a substrate, a lower barrier layer including a first lower barrier layer on the upper surface of the floating gate, and a second lower barrier layer on a side surface of the floating gate to have a thickness smaller than a thickness of the first lower barrier layer, an inter-gate dielectric layer over the lower barrier layer, and a control gate over the inter-gate dielectric layer.

Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.

Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

Abstract: A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

Abstract: A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.

Abstract: A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation.

Abstract: A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

Abstract: A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region.

Abstract: In a semiconductor device using a nonvolatile memory, high speed erasing operation and low power consumption are realized. In a nonvolatile memory in which a channel formation region, a tunnel insulating film, and a floating gate are stacked in this order, the channel formation region is formed using an oxide semiconductor layer. In addition, a metal wiring for erasing is provided in a lower side of the channel formation region so as to face the floating gate. With the above structure, when erasing operation is performed, charge accumulated in the floating gate is extracted to the metal wiring through the channel formation region. Consequently, high speed erasing operation and low power consumption of the semiconductor device can be realized.

Abstract: An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region.

Abstract: The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

Abstract: A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer.

Abstract: A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region.

Abstract: According to one embodiment, a semiconductor device includes a stacked structure that is formed by laminating a first insulating film, first conductive layer, second insulating film and second conductive layer on a semiconductor substrate and in which the first and second conductive layers are connected with a via electrically, an interlayer insulating film formed to electrically separate the second conductive layer into a first region including a connecting portion with the first conductive layer and a second region that does not include the connecting portion, a first contact plug formed on the first region and a second contact plug formed on the second region. An isolation insulating film is buried in portions of the substrate, first insulating film and first conductive layer in one peripheral portion on the second region side of the stacked structure and the second contact plug is formed above the isolation insulating film.

Abstract: A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.

Abstract: A flash memory device including a lower tunnel insulation layer on a substrate, an upper tunnel insulation layer on the lower tunnel insulation layer, and a P-type gate on the upper tunnel insulation layer, wherein the upper tunnel insulation layer includes an amorphous oxide layer.

Abstract: According to one embodiment, a semiconductor device includes a substrate, conductive members, an interlayer insulating film, and a plurality of contacts. The conductive members are provided in an upper portion of the substrate or above the substrate to extend in one direction. The interlayer insulating film is provided on the substrate and the conductive members. The plurality of contacts is provided in the interlayer insulating film. In a first region on the substrate, the contacts are located at some of lattice points of an imaginary first lattice. In a second region on the substrate, the contacts are located at some of lattice points of an imaginary second lattice. The second lattice is different from the first lattice. Each of the first lattice and the second lattice includes some of the lattice points located on the conductive members or on an extension region extended in the one direction of the conductive members.

Abstract: Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

Abstract: A memory device includes gate lines and select lines formed over a substrate, and at least two dummy lines formed in a gap region between adjacent select lines. The memory device is able to reduce a width of the select line by enhancing uniformity of the line pattern density. Therefore, a degree of integration of the memory device is enhanced and the cost of production is reduced. Furthermore, by forming a source line in a gap region between adjacent dummy lines, it is possible to secure a process margin of photolithography for forming a contact hole and to reduce contact resistance.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract: The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed threshold element by a tunnel insulator over the substrate, a charge trapping layer over the tunnel insulator, a charge blocking layer over the trapping layer, and a control gate, having a nitride layer, over the charge blocking layer. In one embodiment, the gate insulator, tunnel insulator and charge trapping layers are all SiON with thicknesses that depend on the designed programming voltage. The control gate can be formed overlapping the access gate or the access gate can be formed overlapping the control gate.

Abstract: A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer.

Abstract: Two diffusion layers are provided in an element area. A tunnel insulating film is provided on the surface of the element area between the two diffusion layers. A charge storage layer is provided on the tunnel insulating film. A first insulator provided on the upper surface of the charge storage layer. An inter-electrode insulating film provided on the first insulator, on the side surface of the charge storage layer in a first direction and on the isolation insulating film. And a control gate electrode extends in the first direction and covers the charge storage layer via the first insulator and the inter-electrode insulating film. The first insulator is thicker than the inter-electrode insulating film, and the inter-electrode insulating film has a first slit on the first insulator.

Abstract: A semiconductor memory device and a method of fabricating the same which is suitable for fabrication of a non-volatile memory, such as an EEPROM, using a polysilicon-insulator-polysilicon (PIP) process. The semiconductor memory device includes isolation layers defining a tunneling region and a read transistor region of a semiconductor substrate, a lower polysilicon film formed on and/or over the tunneling region and the read transistor region, a dielectric film formed on and/or over the lower polysilicon film in the tunneling region, and an upper polysilicon film formed on and/or over the dielectric film.

Abstract: A semiconductor flash memory includes a tunnel oxide film formed over a semiconductor substrate, a first spacer composed of polysilicon formed over the semiconductor substrate including the tunnel oxide film, a second spacer composed of an insulating material formed at sidewalls of the first spacer, a dielectric film formed at the uppermost surface of the first spacer and the second spacer, a control gate formed at the uppermost surface of the dielectric film, and a third spacer composed of an insulating material formed at and contacting sidewalls of the second spacer, the dielectric film and the control gate. A first source/drain region formed may be formed in the semiconductor substrate and self-aligned with the first spacer and a second source/drain region may be formed in the semiconductor substrate and self-aligned with the second spacer.

Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors arranged in a direction and a select transistor to select the memory cell transistors, each of the memory cell transistors of a charge trap type are at least composed of a first insulating layer and a first gate electrode respectively, and the select transistor is at least composed of a second insulating layer and a second gate electrode. The first gate electrode is provided with a first silicide layer of a first width formed on the first insulating layer. The second gate electrode is provided with an impurity-doped silicon layer formed on the second insulating layer and with a second silicide layer of a second width formed on the impurity-doped silicon layer. The second silicide has the same composition as the first silicide. The second width is larger than the first width.

Abstract: A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.

Abstract: Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel.

Abstract: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.

Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.

Abstract: Techniques are disclosed herein for applying different process steps to single-level cell (SLC) blocks in a memory array than to multi-level cell (MLC) blocks such that the SLC blocks will have high endurance and the MLC blocks will have high reliability. In some aspects, different doping is used in the MLC blocks than the SLC blocks. In some aspects, different isolation is used in the MLC blocks than the SLC blocks. Techniques are disclosed that apply different read parameters depending on how many times a block has been programmed/erased. Therefore, blocks that have been cycled many times are read using different parameters than blocks that have been cycled fewer times.

Abstract: An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.

Abstract: A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.

Abstract: Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode.

Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.