For Multilayer Capacitor Patents (Class 361/306.3)
  • Patent number: 10284017
    Abstract: A coil device and a wireless power transmission device which can detect the happened open fault or short fault reliably in any one of the plurality of capacitor elements constituting the capacitor circuit. Coil device includes coil for power transmission, capacitor circuit connected to coil for power transmission and having a plurality of capacitor elements, conductive metal portion which is disposed close to coil for power transmission, and measuring portion for measuring a voltage or a current generated in metal portion.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: May 7, 2019
    Assignee: TDK CORPORATION
    Inventors: Narutoshi Fukuzawa, Ayako Sato, Tsunehiro Saen
  • Patent number: 10269499
    Abstract: A multilayer ceramic capacitor may include: three external electrodes disposed on a mounting surface of a ceramic body to be spaced apart from one another. When a thickness of an active layer including a plurality of first and second internal electrodes disposed therein is defined as AT, and a gap between a first or second lead part of the first internal electrode and a third lead part of the second internal electrode is defined as LG, the following Equation may be satisfied: 0.00044?LG*log [1/AT]?0.00150.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 23, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Byoung Hwa Lee, Kyo Kwang Lee, Min Cheol Park, Young Ghyu Ahn, Sang Soo Park
  • Patent number: 10242803
    Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Conductive layer ends and dielectric layer edges of a multilayer ceramic capacitor may be modified to comprise a round shape, which may increase voltage limits by reducing electric field intensity that results from sharp corners. Further, the capacitor may comprise wave-like structures to increase surface area of a conductive layer and/or dielectric layer. The round shape of the conductive layer end may in-part reduce the need for a wide protective gap due to its dome-shape permitting the dielectric layer to be wider on top and bottom, and thinner at the center, e.g. concave, which provides strength support to the layers. The 3D Printing process permits the distance between the conductive layer end of the conductive layer to be much closer to the dielectric layer edge of the dielectric layer, such as below the standard 500 microns.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: March 26, 2019
    Assignee: VQ RESEARCH, INC.
    Inventor: John L. Gustafson
  • Patent number: 10224149
    Abstract: Provided is a module comprising a carrier material, comprising a first conductive portion and a second conductive portion, and a multiplicity of electronic components wherein each electronic component comprises a first external termination with at least one first longitudinal edge and a second external termination with at least one second longitudinal edge. A first longitudinal edge of a first electronic component is connected to the first conductive portion by a first interconnect; and a second longitudinal edge of the first electronic component is connected to the second conductive portion by a second interconnect.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 5, 2019
    Assignee: KEMET Electronics Corporation
    Inventors: Galen W. Miller, John E. McConnell, John Bultitude, Garry L. Renner
  • Patent number: 10204737
    Abstract: Relatively low noise capacitors are provided for surface mounted applications. Electro-mechanical vibrations generate audible noise, which are otherwise relatively reduced through modifications to MLCC device structures, and/or their mounting interfaces on substrates such as printed circuit boards (PCBs). Different embodiments variously make use of flexible termination compliance so that surface mounting has reduced amplitude vibrations transmitted to the PCB. In other instances, side terminal and transposer embodiments effectively reduce the size of the mounting pads relative to the case of the capacitor, or a molded enclosure provides standoff, termination compliance and clamping of vibrations.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: February 12, 2019
    Assignee: AVX CORPORATION
    Inventors: Andrew P. Ritter, Carl L. Eggerding
  • Patent number: 10204739
    Abstract: A multilayer electronic component includes a capacitor body, first and second external electrodes, first and second land portions, and first and second insulating portions. The first and second external electrodes are disposed and spaced apart from each other on a mounting surface of the capacitor body. The first and second land portions include a conductive material and are disposed on the first and second external electrodes, respectively. The first and second insulating portions are disposed between the first and second land portions on the mounting surface of the capacitor body to be spaced apart from each other and each have one end connected to a respective one of the first and second land portions. A board having a multilayer electronic component includes a circuit board having first and second electrode pads disposed on one surface thereof, and the multilayer electronic component mounted thereon.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Gu Won Ji, Heung Kil Park, Se Hun Park
  • Patent number: 10192683
    Abstract: A multilayer capacitor includes a capacitor body, dielectric layers and a plurality of first internal electrodes and second internal electrodes forming a portion of the capacitor body, the plurality of first internal electrodes and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, the capacitor body further having a first surface and a second surface opposing each other, a third surface and a fourth surface opposing each other, and a fifth surface and a sixth surface opposing each other, the first internal electrodes and the second internal electrodes being exposed through at least the third surface and the fourth surface, respectively, an insulating layer disposed in the first surface of the capacitor body, a buffer layer at least partially covering the insulating layer, and a first terminal electrode and a second terminal electrode spaced apart from each other.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Se Hun Park
  • Patent number: 10186377
    Abstract: A multilayer ceramic capacitor includes a capacitor body and first to fourth outer connectors. The capacitor body includes dielectric layers and conductor layers, first and second principal surfaces facing each other in a height direction, first and second side surfaces facing each other in a length direction, and third and fourth side surfaces facing each other in a width direction. The first to fourth outer connectors cover portions of the first to fourth side surfaces, respectively. In a case where L0, W0, and H0 are maximum external dimensions of the multilayer ceramic capacitor in the length direction, the width direction, and the height direction, respectively, L0, W0, and H0 satisfy a condition of about 2.67?L0/H0 and a condition of about 1/1.72?L0/W0?about 1.72.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: January 22, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasuo Fujii
  • Patent number: 10153089
    Abstract: The present disclosure discloses a thin-film capacitor for an electric vehicle, including: a casing, a plurality of capacitor cores, an anode busbar, a cathode busbar, a first electrode terminal, a second electrode terminal, a first connection sheet, a second connection sheet, a first battery connection sheet, a second battery connection sheet, a first battery connection terminal and a second battery connection terminal, in which the first battery connection sheet is connected to the anode busbar and adjacent to an end of the anode busbar, the second battery connection sheet is connected to the cathode busbar and adjacent to the first battery connection sheet, an axis of one of the plurality of the capacitor cores is arranged to be perpendicular to the anode busbar and the cathode busbar and two ends of the one capacitor core are connected to the first battery connection sheet and the second battery connection sheet respectively.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: December 11, 2018
    Assignee: BYD Company Limited
    Inventors: Wei Yang, Siyuan Liu, Lusheng Wu
  • Patent number: 10128047
    Abstract: Methods and systems to improve a multilayer ceramic capacitor using additive manufacturing are disclosed. Layers of a capacitor may be modified from its traditional planar shape to a wavy structure. The wavy shape increases surface area within a fixed volume of the capacitor, thus increasing capacitance, and may comprise smooth and repetitive oscillations without the presence of voltage-degrading sharp corners. In addition, the ends of each conductive layer do not have sharp edges, such as comprising of a round corner. The one-dimensional wave pattern may run parallel to the width of the capacitor, or it may align in parallel to the length of the capacitor. In some embodiments, the wave pattern may be parallel to both the width and the length—in two dimensions—such that it forms an egg-crate shape. Further, the wavy structures may comprise of secondary or tertiary wavy structures to further increase surface area.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: November 13, 2018
    Assignee: VQ RESEARCH, INC.
    Inventor: John L. Gustafson
  • Patent number: 10128198
    Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 13, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Chih-Cheng Lee, Yuan-Chang Su
  • Patent number: 10128048
    Abstract: A multilayer capacitor includes a body including a capacitor body formed by layering a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the capacitor body and disposed to be spaced apart from each other, respectively; and first, second and third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the first, second and third external electrodes each include first, second and third electrode layers which are sequentially stacked, the first and second electrode layers containing metal and glass particles, and the third electrode layer containing a conductive resin.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: November 13, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Jong Hwan Park
  • Patent number: 10102972
    Abstract: A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Chun Hua, Chung-Long Chang, Chun-Hung Chen, Chih-Ping Chao, Jye-Yen Cheng, Hua-Chou Tseng
  • Patent number: 10079108
    Abstract: A multilayer capacitor includes a pair of external electrodes each having an end face portion; a first principal face extending portion; a second principal face extending portion; a first side face extending portion; and a second side face extending portion. The pair of external electrodes each includes a base electrode and a metallic layer. The metallic layer includes a first metallic layer and a second metallic layer located outside the first metallic layer. An intermetallic compound layer is located outside the first metallic layer, and is exposed from the second metallic layer in a ridge portion lying between the end face portion and the first principal face extending portion, a ridge portion lying between the first side face extending portion and the first principal face extending portion, and a ridge portion lying between the second side face extending portion and the first principal face extending portion.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: September 18, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Hidefumi Hatanaka, Katsuichi Kato
  • Patent number: 10068839
    Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Brunschwiler, Sebastian Gerke, Stefano Sergio Oggioni
  • Patent number: 10056384
    Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: August 21, 2018
    Assignee: Apple Inc.
    Inventors: Jared L. Zerbe, Emerson S. Fang, Jun Zhai, Shawn Searles
  • Patent number: 10057988
    Abstract: A multilayer capacitor and a board having the same includes external electrodes and internal electrodes. The external electrodes include connection portions formed on a mounting surface of a capacitor body and band portions formed on side surfaces of the capacitor body, and the internal electrodes include body portions overlapping each other and lead portions extended from the body portions to the mounting surface of the capacitor body, to thereby be connected to the connection portions of the external electrodes. The body portions are formed to be spaced apart from virtual lines connecting distal ends of the connection portions and distal ends of the band portions to each other.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 21, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Ghyu Ahn, Byoung Hwa Lee
  • Patent number: 10026554
    Abstract: A length in a first direction of the element body is smaller than a length in a second direction of the element body and smaller than a length in a third direction of the element body, the second direction being perpendicular to the first direction, the third direction being perpendicular to the first and second direction. Each of a first terminal electrode and a second terminal electrode includes a sintered conductor layer formed on the element body, a first plated layer formed on the sintered conductor layer, and a second plated layer formed on the first plated layer. In each of a first electrode portion disposed on a principal face and a third electrode portion disposed on a principal face, a maximum thickness of the sintered conductor layer is larger than a thickness of the first plated layer and not more than a thickness of the second plated layer.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: July 17, 2018
    Assignee: TDK CORPORATION
    Inventors: Toru Onoue, Ken Morita, Kenta Yamashita
  • Patent number: 10028381
    Abstract: A composite electronic component includes a multilayer ceramic capacitor including a ceramic body in which dielectric layers and internal electrodes are alternately disposed, and first and second external electrodes disposed on a lower surface of the ceramic body; a tantalum capacitor including a body portion containing a sintered material of a tantalum powder and a tantalum wire having a portion embedded in the body portion, and disposed on the multilayer ceramic capacitor; and an encapsulant part enclosing the tantalum capacitor and the multilayer ceramic capacitor, wherein the internal electrodes are led to the lower surface of the ceramic body.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: July 17, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soo Hwan Son, Young Ghyu Ahn, Yu Jin Choi
  • Patent number: 10014114
    Abstract: A mounting substrate on which at least any one of three kinds of electronic components including a first electronic component, a second electronic component, and a third electronic component are able to be mounted includes a pair of first edge portions and a pair of second edge portions. When a dimension of the first electronic component in its length direction is designated as L1, a dimension of the first electronic component in its width direction is designated as W1, a dimension of the second electronic component in its length direction is designated as L2, and a dimension of the second electronic component in its width direction is designated as W2, a dimension of the third electronic component in its width direction is any one of W1 and W2, and a dimension of the third electronic component in its length direction is L2 when the dimension of the third electronic component in its width direction is W1, and is L1 when the dimension of the third electronic component in its width direction is W2.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 3, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Wakashima, Yuta Saito, Kohei Shimada, Naobumi Ikegami
  • Patent number: 10008332
    Abstract: In an embodiment, a capacitor body 11 of a multilayer ceramic capacitor 10 has, at a position adjoining a lower height-direction surface f6, a tapered part 11a whose width gradually decreases toward the lower height-direction surface f6 over the entire length of the part. Also, the first external electrode 12 and second external electrode 13 have, at their two ends in the width direction, engagement parts 12a, 13a that wrap around onto the width-direction outer surfaces f3a, f4a of the tapered part 11a, respectively. The multilayer ceramic capacitor, after it has been mounted on a circuit board, can mitigate the phenomenon of the first external electrode and second external electrode separating from the capacitor body without reducing the benefit of capacitance increase.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: June 26, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Kotaro Mizuno
  • Patent number: 9978518
    Abstract: In a multilayer ceramic capacitor, each outer electrode includes a first outer electrode layer that contains Ni and that is disposed on each main surface of a multilayer body and a second outer electrode layer that contains a glass component and Cu and that covers one end portion of the first outer electrode layer which is closer to an end surface of the multilayer body, the first and second outer electrode layers are joined together in a region including an edge shared by the main surface and the end surface, the other end portion of the first outer electrode layer is exposed from the second outer electrode layer, and Ni of the first outer electrode layer is diffused in the second outer electrode layer and is dissolved in Cu of the second outer electrode layer to define a solid solution in the region including the edge.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 22, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yasuhiro Nishisaka
  • Patent number: 9978514
    Abstract: There is provided a multilayer ceramic electronic component including, a ceramic body including a plurality of dielectric layers stacked in a thickness direction, satisfying T/W>1.0 when a width and a thickness thereof are defined as W and T, respectively, and having a groove portion inwardly recessed in a length direction in at least one main surface thereof, a plurality of first and second internal electrodes disposed in the ceramic body to face each other, having the dielectric layers interposed therebetween, and alternately exposed through both end surfaces of the ceramic body, and first and second external electrodes formed to extend from the both end surfaces of the ceramic body to the at least one main surface having the groove portion formed therein.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byung Woo Han, Dae Bok Oh, Jae Yeol Choi, Sang Huk Kim
  • Patent number: 9978536
    Abstract: Electroconductive paste is applied onto an electronic component body to form an external electrode by supplying the electroconductive paste to a first groove on an outer circumferential surface of a roller to extend along a circumference of the roller, disposing the electronic component body such that a second main surface of the electronic component body and an outer circumferential surface of the roller are opposed to each other while a first edge portion defined by the second main surface and a first end surface of the electronic component body is in the first groove when viewed in plan, and pressing the electronic component body against the outer circumferential surface of the roller so that the first edge portion is located in the first groove in a depth direction of the first groove.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 22, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takashi Sawada
  • Patent number: 9960110
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also he used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 1, 2018
    Assignee: INTEL CORPORATION
    Inventor: Boyan Boyanov
  • Patent number: 9953766
    Abstract: A multilayer ceramic electronic component includes a ceramic body including an electrode structure including internal electrodes stacked to face each other with respective dielectric layers interposed therebetween and alternately exposed to first and second end surfaces thereof and ceramic bands enclosing regions spaced apart from the first and second end surfaces of the electrode structure; and external electrodes covering the first and second end surfaces of the electrode structure and at least portions of surfaces of the electrode structure connected to the first and second end surfaces of the electrode structure, respectively.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong Tack Shin, Jae Yeol Choi, Ji Hea Kim
  • Patent number: 9918380
    Abstract: A noise reduction board includes: a first board; a second board arranged under the first board; a plurality of power feeding parts made of a metal in a shape of a pole and configured to electrically interconnect the first board and the second board; and a noise reduction part arranged between the power feeding parts, wherein the noise reduction part includes: a metal plate; an insulator configured to cover a surface of the metal plate; a first terminal provided on the side of the first board of the metal plate and electrically coupled to a ground pattern of the first board; and a second terminal provided on the side of the second board of the metal plate and electrically coupled to a ground pattern of the second board.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: March 13, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Hajime Murakami
  • Patent number: 9911535
    Abstract: An electronic device includes a chip component and an external terminal. The external terminal includes a terminal electrode connection part, a mounting connection part, and a support part. The terminal electrode connection part is arranged to face an end surface electrode part of a terminal electrode of the chip component. The mounting connection part is connectable to a mounting surface. The support part faces one side surface of an element body of the chip component closest to the mounting surface so as to support the one side surface spaced from the mounting surface. A bonding region and a non-bonding region are formed between the terminal electrode connection part of the external terminal and the end surface electrode part of the terminal electrode. The non-bonding region is formed from the terminal electrode connection part to the support part.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: March 6, 2018
    Assignee: TDK CORPORATION
    Inventors: Masahiro Mori, Takayuki Sakai, Katsumi Kobayashi
  • Patent number: 9892855
    Abstract: An external electrode includes a sintered metal layer disposed on at least an end surface and a conductive resin layer disposed on the sintered metal layer. The sintered metal layer includes a first portion, a second portion, and a third portion. The first portion is disposed at a central region of the end surface. The second portion is disposed at a part of a peripheral region of the end surface, and extends to an edge portion of the end surface from the first portion. The third portion is disposed at a remaining part of the peripheral region of the end surface. The thickness of the second portion is less than that of the first portion. The thickness of the third portion is less than that of the second portion. The first portion, the second portion, and the third portion are covered with the conductive resin layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 13, 2018
    Assignee: TDK CORPORATION
    Inventors: Norihisa Ando, Atsushi Takeda, Hideki Kaneko, Yui Sugiura, Tatsuo Inagaki, Tomomichi Gunji, Kouhei Yamaguchi
  • Patent number: 9892854
    Abstract: A multilayer ceramic capacitor contains Ni in internal electrodes, and includes a sintered metal layer containing Cu in external electrodes. At a joined portion between each internal electrode and each external electrode, mutual diffusion layers of Cu and Ni extend across the internal and external electrodes. On each internal electrode, a mutual diffusion layer is present with a thickness t1, which is defined by a dimension from a first end surface or a second end surface to an interior end in a longitudinal direction, not smaller than about 0.5 ?m and not greater than about 5 ?m. On each external electrode, a mutual diffusion layer is present with a thickness t2, which is defined by a dimension from the first end surface or the second end surface to an exterior end in the longitudinal direction, not smaller than about 2.5% and not greater than about 33.3% of a thickness t0 of a sintered metal layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: February 13, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Yoshito Saito
  • Patent number: 9853002
    Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: December 26, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Shuuichi Kariyazaki
  • Patent number: 9842700
    Abstract: A capacitor element includes first through sixth surfaces, a first-side outer electrode at a first end portion of the first surface and on portions of the third, fifth, and sixth surfaces, a second-side outer electrode at a second end portion of the first surface and on portions of the fourth, fifth, and sixth surfaces, a center outer electrode at a portion of the first surface between the first-side outer electrode and the second-side outer electrode and on portions of the fifth and sixth surfaces, and two outermost conductor layers of first and second conductor layers are disposed at both outermost ends in the width direction, a first of the two outermost conductor layers next to one of the first conductor layers with an inner dielectric layer therebetween is connected to the center outer electrode, and a second of the pair of outermost conductor layers next to one of the second conductor layers with an inner dielectric layer therebetween is connected to the first-side outer electrode and the second-side ou
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: December 12, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mitsuru Ikeda, Hirobumi Adachi, Hitoaki Kimura
  • Patent number: 9824822
    Abstract: A three-terminal capacitor includes a capacitor element including first through sixth surfaces, first-side and second-side outer electrodes, a center outer electrode between the first-side and second-side outer electrodes, and conductor layers within the capacitor element. A height H2 is greater than a height H3, where the height H2 represents a higher one of a height at a center of a portion of the first-side outer electrode on the fifth surface and a height at a center of a portion of the first-side outer electrode on the sixth surface, and the height H3 represents a height at a center of a portion of the first-side outer electrode on the third surface, wherein the height H2 and the height H3 extend in the thickness direction.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 21, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hirobumi Adachi, Mitsuru Ikeda, Hitoaki Kimura
  • Patent number: 9818538
    Abstract: A multilayer ceramic electronic component may include a ceramic body including an active part in which dielectric layers and internal electrodes are alternately disposed, an upper cover part disposed on the active part, and a lower cover part disposed below the active part, a buffer layer disposed in at least one of the upper and lower cover parts, and external electrodes disposed on end surfaces of the ceramic body. The buffer layer may contain a conductive metal in a content of 1 to 40 vol %.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hong Seok Kim, Chung Eun Lee, Chang Hoon Kim, Doo Young Kim
  • Patent number: 9818655
    Abstract: Flip-chip package reliability monitoring and systems of monitoring using capacitive sensors are disclosed. The monitoring is conducted in situ and in real-time without the need for destructive testing of the packages. The capacitive sensors can be used for flip-chip package reliability monitoring.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Taryn J. Davis, Jonathan R. Fry, Tuhin Sinha
  • Patent number: 9793057
    Abstract: An improved method for forming a capacitor is provided as is a capacitor, or electrical component, formed by the method. The method includes providing an aluminum containing anode with an aluminum oxide dielectric thereon; forming a cathode on a first portion of the aluminum oxide dielectric; bonding an anode lead to the aluminum anode on a second portion of the aluminum oxide by a transient liquid phase sintered conductive material thereby metallurgical bonding the aluminum anode to the anode lead; and bonding a cathode lead to said cathode.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: October 17, 2017
    Assignee: KEMET Electronics Corporation
    Inventors: John E. McConnell, Garry L. Renner, John Bultitude
  • Patent number: 9779874
    Abstract: An method of forming a metal foil coated ceramic and a metal foil capacitor is provided in a method of making a metal foil coated ceramic comprising providing a metal foil; applying a ceramic precursor to the metal foil wherein the ceramic precursor comprises at least one susceptor and a high dielectric constant oxide and an organic binder, and sintering the ceramic precursor with a high intensity, high pulse frequency light energy to form the metal foil ceramic.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 3, 2017
    Assignee: KEMET Electronics Corporation
    Inventors: John E. McConnell, John Bultitude, Abhijit Gurav
  • Patent number: 9773619
    Abstract: In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 26, 2017
    Assignee: Murata Manufacturing Co., LTd.
    Inventors: Sui Uno, Takashi Sawada, Yohei Mukobata
  • Patent number: 9773615
    Abstract: There are provided a multilayer ceramic capacitor and a board having the same. The multilayer ceramic capacitor includes: three external electrodes disposed to be spaced apart from one another on a mounting surface of a ceramic body; first internal electrodes each including first and second lead portions connected to the outermost external electrodes, respectively; and second internal electrodes each including a third lead portion connected to the middle external electrode, in which a first region in which the first internal electrodes are laminated is disposed in a central portion of the ceramic body in a width direction of the ceramic body, and second regions in which the first and second internal electrodes are alternately laminated are disposed on both sides of the intervening first region in the width direction of the ceramic body.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: September 26, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Soo Park, Min Cheol Park
  • Patent number: 9728334
    Abstract: A multilayer ceramic capacitor may include three external electrodes disposed on a mounting surface of a ceramic body so as to be spaced apart from each other. When a height of at least one portion of the external electrode formed on one side surface of the ceramic body in a width direction is defined as d, and a thickness of the ceramic body is defined as T, a ratio of d/T satisfies 0.10?d/T.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: August 8, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyo Kwang Lee, Jin Kim, Young Ghyu Ahn, Byoung Hwa Lee
  • Patent number: 9715964
    Abstract: This disclosure describes methods and systems for minimizing electromagnetic interference (EMI) noise emanating from a ceramic capacitor. The ceramic capacitor may include several terminations are on a bottom portion of the capacitor. The capacitor may be designed to include several capacitors formed from electrode layers. The capacitor may include a conductive coating on an outer peripheral portion. The coating may include conductive materials such as Cu, Ni, Ag, and/or graphite. Alternatively, some regions of the capacitor may include electrode layers built into the capacitor that are not associated with capacitors. In this manner, the ceramic capacitor may be free of the conductive coating to locations proximate to the described electrode layers not associated with capacitors. The conductive coating can act as an electromagnetic shielding to prevent the EMI noise from emanating outside the electromagnetic shielding. Also, the conductive coating can be electrically grounded (e.g.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: July 25, 2017
    Assignee: Apple Inc.
    Inventors: Gang Ning, Pradeep Vengavasi, Linda Y. Dunn, Yonas A. Hartanto, Shawn X. Arnold
  • Patent number: 9706641
    Abstract: A multilayer capacitor includes internal electrodes having a plurality of lead portions exposed in a width direction of a body, and external electrodes connected to the lead portions, the external electrodes including a conducting layer, conductive resin layers, and a plating layer, respectively, and a board having the same.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 11, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Heung Kil Park, Jong Hwan Park, Young Ghyu Ahn
  • Patent number: 9685271
    Abstract: A multilayer ceramic electronic component includes: a ceramic body including dielectric layers; an active part including first and second internal electrodes which are exposed to both end surfaces of the ceramic body in a length direction thereof, and floating electrodes which are partially overlapped with the first and second internal electrodes; upper and lower cover parts including the dielectric layers and disposed above and below the active part; dummy electrodes disposed in the upper and lower cover parts to be overlapped with the floating electrodes; and first and second external electrodes.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: June 20, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sun Cheol Lee, Hyoung Wook Lim, Mi Ok Park, Jae Yeol Choi, Ji Hee Moon
  • Patent number: 9673383
    Abstract: There is provided a multilayer ceramic electronic component including: a ceramic body in which internal electrodes containing a first electrode material and dielectric layers are alternately disposed; external electrodes provided on outer surfaces of the ceramic body and containing a second electrode material; and diffusion parts each disposed to be connected to one end of the internal electrode and the external electrode and containing the first electrode material and the second electrode material mixed with each other, wherein the diffusion part includes an internal diffusion portion disposed within the ceramic body and an external diffusion portion protruding outside of the ceramic body.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyoung No Lee, Kyu Ha Lee, Eun Joo Choi, Jun Hyeong Kim, Byung Jun Jeon
  • Patent number: 9653213
    Abstract: A multilayer ceramic capacitor may include a ceramic body having first to third dielectric layers, first and third internal electrodes disposed to be partially exposed to an upper surface of the ceramic body, second and fourth internal electrodes disposed to be partially exposed to a lower surface of the ceramic body, internal resistance electrodes disposed on the third dielectric layers and partially exposed to the upper surface of the ceramic body, first and third external electrodes disposed on the ceramic body to be connected to the first and third internal electrodes, second and fourth external electrodes disposed to be connected to the second and fourth internal electrodes. The first and third external electrodes are electrically connected to each other by the internal resistance electrodes.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Soo Park, Min Cheol Park
  • Patent number: 9640477
    Abstract: A method of producing a semiconductor package includes planarizing a surface extending from at least part of connection regions to a pair of terminals by disposing a semiconductor element and a capacitor element such that the semiconductor element and the capacitor element do not overlap each other in plan view of the semiconductor element, and by filling a portion between the semiconductor element and the capacitor element with an insulator layer; directly connecting part of the connection regions and one of the pair of terminals to a first metal layer by forming the first metal layer on top of the connection regions, on top of the pair of terminals, and on top of the insulator layer; forming a dielectric layer on top of the first metal layer; and forming a capacitor layer by forming a second metal layer on top of the dielectric layer.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 2, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventor: Daisuke Iguchi
  • Patent number: 9633785
    Abstract: A multilayer ceramic electronic component may includes: a ceramic body including dielectric layers; an active layer including first and second internal electrodes disposed to be exposed to both end surfaces of the ceramic body in a length direction of the ceramic body, respectively, first floating electrodes overlapping the first and second internal electrodes while being spaced apart from each other in the thickness direction of the ceramic body, second floating electrodes each disposed to be spaced apart from the first and second internal electrodes, and first and second dummy electrodes disposed to be spaced apart from the first floating electrodes; upper and lower cover layers disposed upwardly and downwardly of the active layer, respectively; third and fourth dummy electrodes disposed to be exposed to both end surfaces of the ceramic body in the length direction of the ceramic body, respectively; and fifth dummy electrodes.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: April 25, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sun Cheol Lee, Min Hyang Kim, Seung Yul Lee, Kyeong Jun Kim, Jang Hyun Lee
  • Patent number: 9620289
    Abstract: According to an embodiment, first and second internal electrode layers are alternatively interposed between dielectric layers to form a laminated capacitor. The first internal electrode layer have a first base portion connected to a first external electrode, and is extended from the first base portion toward a second external electrode. The second internal electrode layer have a base portion connected to the second external electrode, and is extended from the second external electrode toward the first external electrode. The second internal electrode layer is formed in a deformation pattern which allows a path length greater than a length between the first and the second external electrode so that an open stub producing an open stub resonance is formed.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: April 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuki Torigoshi, Nobuyuki Kasai
  • Patent number: 9613753
    Abstract: An external terminal 30 comprises a terminal electrode connection part 32 connected to the terminal electrode 22 to face to the end surface of the element body 26; a mounting connection part 34 connectable to a mounting surface 62; and a joint part 36 which joins the terminal electrode connection part 32 with the mounting connection part 34 to separate one side surface 26a of the element body 26 closest to the mounting surface 64 therefrom. A width W1 of the joint part 36 along a direction parallel to the mounting surface 62 is smaller than a width W0 of the terminal electrode connection part 32.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 4, 2017
    Assignee: TDK Corporation
    Inventors: Makoto Maeda, Katsumi Kobayashi, Sunao Masuda, Toshihiro Kuroshima
  • Patent number: 9589729
    Abstract: A multilayer ceramic capacitor includes a laminated body including an inner layer portion including ceramic dielectric layers and internal electrodes, and outer layer portions including ceramic dielectric layers. External electrodes connected to the internal electrodes are provided on both ends of the laminated body. The main constituent of the inner layer portion is a perovskite-type compound represented by ABO3. The outer layer portions include first outer layers and second outer layers respectively containing oxides that differ from each other in main constituents, and boundary reaction layers are provided between the first outer layers and the second outer layers. First ceramic dielectric layers outside the boundary reaction layers differ in color from second ceramic dielectric layers inside the boundary reaction layers.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 7, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroyuki Wada, Kohei Shimada, Kenji Takagi, Tomomi Koga, Tomotaka Hirata, Hitoshi Nishimura, Hiroki Awata, Sui Uno