For Multilayer Capacitor Patents (Class 361/306.3)
  • Patent number: 11069479
    Abstract: A multilayer capacitor may include a capacitor body including an active area including a plurality of dielectric layers, and a plurality of first and second internal electrodes, upper and lower cover layers disposed on upper and lower surfaces of the active area, and having first to six external surfaces; first and second external electrodes including first and second connection portions and first and second band portions, respectively; and a plurality of dummy electrodes disposed on the upper and lower cover layers with a dielectric layer interposed therebetween, and exposed through corners of the capacitor body, a portion of the plurality of dummy electrodes being disposed between the upper and lower surfaces of the capacitor body and the first and second band portions.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hee Soo Lee, Ah Young Shin, Dong Hoon Kim, Jong Hoon Kim, Hong Seok Kim, Jong Ho Lee
  • Patent number: 11049651
    Abstract: An electronic component includes a first external electrode disposed on a first end surface and a second external electrode disposed on a second end surface. The first external electrode includes a first conductive layer including ceramic particles. The second external electrode includes a second conductive layer including ceramic particles. An end portion of a first internal electrode is located inside the first conductive layer. The electronic component includes little or no cracks and has a low equivalent series resistance (ESR).
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 29, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomohiro Kageyama, Tetsuo Kawakami, Manabu Sakai, Ryuki Kakuta, Takahiro Hirao, Takashi Ohara
  • Patent number: 11043332
    Abstract: In an embodiment, a multilayer ceramic capacitor 10 includes a capacitor boy 11 which has a sixth face f6 provided with a first tapering face f6a over the entire width direction and at a position adjacent to a first face f1, and which also has a second tapering face f6b over the entire width direction and at a position adjacent to a second face f2. The height-direction dimension of the first tapering face f6a on the sixth face f6 is constituted in a manner accommodating an error in the end height of the first part 12a of the first external electrode 12, while the height-direction dimension of the second tapering face f6b on the sixth face f6 is constituted in a manner accommodating an error in the end height of the first part 13a of the second external electrode 13.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: June 22, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Toru Makino
  • Patent number: 11037871
    Abstract: An improved electronic assembly is provided. The electronic assembly comprises a ceramic interposer comprising multiple layers. The active layers of the multiple layers form an embedded capacitor comprising parallel electrodes with a dielectric between adjacent electrodes wherein adjacent electrodes have opposite polarity. A wide band gap device is also on the multilayered ceramic interposer.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 15, 2021
    Assignee: KEMET Electronics Corporation
    Inventors: Allen Templeton, John Bultitude, Lonnie G. Jones, Philip M. Lessner
  • Patent number: 11024461
    Abstract: A multi-layer ceramic electronic component includes: a ceramic body including a main surface facing in a first direction, an end surface facing in a second direction orthogonal to the first direction, a side surface facing in a third direction orthogonal to the first and second directions, and internal electrodes laminated in the first direction; and an external electrode formed on a surface of the ceramic body, the external electrode including a base film including an end-surface-covering portion that covers the end surface, and a main-surface-covering portion that covers part of the main surface continuously from the end-surface-covering portion, an electrically conductive thin film including a base-covering portion that covers the main-surface-covering portion, and a ceramic-body-covering portion that extends from the base-covering portion in the second direction and covers part of the main surface, and a plating film that covers the electrically conductive thin film and the base film.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Yasutomo Suga, Masataka Watabe, Jun Nishikawa, Sadayoshi Kato
  • Patent number: 11017930
    Abstract: An inductor includes a body structure, a first external electrode and a second external electrode disposed externally on the body structure and spaced apart from each other, and a conductive structure disposed inside the body structure and including a first end portion in contact with the first external electrode and a second end portion in contact with the second external electrode, wherein each of the first and second external electrodes includes an electroless plated layer and an electrolytic plated layer formed of a material different from that of the electroless plated layer and covering the electroless plated layer.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Mi Sun Hwang, Jin Gul Hyun
  • Patent number: 11018068
    Abstract: Described herein are methods and apparatuses for packaging an ultrasound-on-a-chip. An ultrasound-on-a-chip may be coupled to a redistribution layer and to an interposer layer. Encapsulation may encapsulate the ultrasound-on-a-chip device and first metal pillars may extend through the encapsulation and electrically couple to the redistribution layer. Second metal pillars may extend through the interposer layer. The interposer layer may include aluminum nitride. The first metal pillars may be electrically coupled to the second metal pillars. A printed circuit board may be coupled to the interposer layer.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: May 25, 2021
    Assignee: Butterfly Network, Inc.
    Inventors: Jianwei Liu, Keith G. Fife
  • Patent number: 11004605
    Abstract: A multilayer ceramic capacitor includes: a ceramic multilayer structure having a structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the ceramic multilayer structure, a main phase of the plurality of ceramic dielectric layers having a perovskite structure that includes Ca and Zr and is expressed by a general formula ABO3; and a pair of external electrodes that are formed on the two edge faces, wherein 300×TE/TA?12?30 is satisfied when a volume TA is a length CL×a width CW×a thickness CT of the ceramic multilayer structure and a volume TE is a length EL×a width EW×a thickness ET×a stacked number of the plurality of internal electrode layers in a capacity region.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 11, 2021
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Michio Oshima, Atsuhiro Yanagisawa, Yoshinori Shibata, Daisuke Iwai, Hiroyuki Moteki
  • Patent number: 10998132
    Abstract: A capacitor includes an electrically insulating housing that encloses an interior volume, first and second conductive connection pads that are each configured as externally accessible points of electrical contact to internal electrodes of the capacitor that are disposed within the housing, and an active capacitor dielectric material disposed within the housing and being configured as a dielectric medium between the internal electrodes, the first conductive connection pad having a first planar contact surface that is substantially parallel to a first sidewall of the housing, the second conductive connection pad having a second planar contact surface that is substantially parallel to the first sidewall, the first and second planar contact surfaces being offset from one another in a direction that is orthogonal to the first sidewall.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 4, 2021
    Assignees: Infineon Technologies AG, TDK Electronics AG
    Inventors: Tomas Manuel Reiter, Karl Niklas
  • Patent number: 10957486
    Abstract: An electronic component includes a capacitor body having alternately stacked first and second internal electrodes with dielectric layers therebetween, the capacitor body having first to sixth surfaces and the first internal electrodes and the second internal electrodes being exposed through the third surface and the fourth surface, respectively. First and second external electrodes are disposed respectively on the third and fourth surfaces of the body and respectively connected to the first and second internal electrodes. A shielding layer includes a cap portion disposed on the second surface of the capacitor body and a side wall portion disposed on the third, fourth, fifth, and sixth surfaces of the capacitor body, and an insulating layer is disposed between the capacitor body and the shielding layer. The shielding layer consists of first and second shielding layers offset from each other in a direction connecting the third and fourth surfaces.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: March 23, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chan Yoon, Sang Soo Park, Hwi Dae Kim, Woo Chul Shin, Ji Hong Jo
  • Patent number: 10944399
    Abstract: Described is an apparatus which comprises: a 4-state input magnet; a first spin channel region adjacent to the 4-state input magnet; a 4-state output magnet; a second spin channel region adjacent to the 4-state input and output magnets; and a third spin channel region adjacent to the 4-state output magnet. Described in an apparatus which comprises: a 4-state input magnet; a first filter layer adjacent to the 4-state input magnet; a first spin channel region adjacent to the first filter layer; a 4-state output magnet; a second filter layer adjacent to the 4-state output magnet; a second spin channel region adjacent to the first and second filter layers; and a third spin channel region adjacent to the second filter layer.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Ian A. Young, Dmitri E. Nikonov, Uygar E. Avci, Patrick Morrow, Anurag Chaudhry
  • Patent number: 10916493
    Abstract: A direct current (DC) blocking capacitor can be used with an integrated circuit (IC) package. The DC blocking capacitor can include a first electrically conductive planar surface having a first area and a second electrically conductive planar surface having a second area greater than the first area. The second planar surface is in a parallel planar orientation to the first planar surface. The DC blocking capacitor can also include a first set of electrically conductive plates electrically connected to the first planar surface and a second set of electrically conductive plates electrically connected to the second planar surface. The second set of electrically conductive plates is interleaved with and electrically insulated from the first set of electrically conductive plates by a dielectric material.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Darryl Becker, Mark J. Jeanson, Gerald Bartley, Matthew Doyle
  • Patent number: 10910163
    Abstract: A multilayer electronic component include a multilayer capacitor including a capacitor body and first and second external electrodes disposed on ends of the capacitor body, respectively; an alumina chip including a chip body and first and second external terminals disposed on ends of the chip body, respectively, the first and second external terminals being in contact with the first and second external electrodes, respectively; a first plating layer covering the first external electrode and the first external terminal; and a second plating layer covering the second external electrode and the second external terminal. The first and second plating layers each include a nickel plating layer a tin plating layer disposed on the first external electrode and the first external terminal and on the second external electrode and the second external terminal, respectively.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dae Heon Jeong, Kyung Hwa Yu, Man Su Byun, Min Kyoung Cheon, Soo Hwan Son, Ho Yoon Kim
  • Patent number: 10903005
    Abstract: A composite electronic component includes a capacitor including a capacitor body including a dielectric layer and first and second internal electrodes alternately stacked with the dielectric layer interposed therebetween, and first and second electrodes disposed on the capacitor body, and a varistor including a varistor body including ZnO and third and fourth electrodes disposed on the varistor body, wherein the first electrode is electrically connected to the third electrode and the second electrode is electrically connected to the fourth electrode.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hae In Kim, Eun Ju Oh, Yong Sung Kim
  • Patent number: 10879003
    Abstract: An electronic component includes a body in which external electrodes are disposed on opposing surfaces of the body in a first direction thereof, respectively; and a pair of metal frames connected to the external electrodes, respectively, wherein the metal frame includes a support portion bonded to the external electrodes, and a mounting portion extending in the first direction from a lower end of the support portion and spaced apart from the body and the external electrodes, and a length of the mounting portion in a second direction perpendicular to the first direction is smaller than a length of the body in the second direction.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Beom Joon Cho, Sang Soo Park, Ki Young Kim, Woo Chul Shin
  • Patent number: 10861648
    Abstract: An electronic component includes: a capacitor array including a plurality of multilayer capacitors which are sequentially arranged in a first direction, and first and second metal frames disposed on both side surfaces of the capacitor array and connected to first and second external electrodes of the plurality of multilayer capacitors, respectively; the first and second metal frames include first and second support portions, and first and second mounting portions, respectively; and the first and second mounting portions include first and second portions opposing each other toward the center of the capacitor array, and third and fourth portions positioned outside the first and second portions, respectively, and a length of each of the first and second portions is shorter than a length of each of the third and fourth portions.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Beom Joon Cho, Sang Soo Park, Ki Young Kim, Woo Chul Shin
  • Patent number: 10840018
    Abstract: A method is disclosed for making a multilayer electronic device. The method includes placing a screen printing mask on a layer of support material and printing a conductive pattern on a layer of support material using the screen printing mask. The conductive pattern includes a plurality of electrode shapes including respective central enlarged portions. The method includes cutting the layer of support material and conductive pattern along a plurality of cutting lines intersecting the central enlarged portions such that at least one of the plurality of electrode shapes is divided into a pair of electrodes along a cutting width. The cutting width is indicative of a cutting accuracy associated with at least one of the cutting lines.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: November 17, 2020
    Assignee: AVX Corporation
    Inventors: Marianne Berolini, Michael Kirk, Palaniappan Ravindranathan
  • Patent number: 10818432
    Abstract: An electronic device includes a chip component and a metal terminal. The metal terminal is connected with the chip component. The metal terminal includes an electrode facing portion and a holding portion. The electrode facing portion is arranged correspondingly with an end surface of the terminal electrode of the chip component. The holding portion holds the chip component. A space region between the electrode facing portion and the end surface of the terminal electrode includes a joint region and a non-joint region. In the joint region, a connection member connects the electrode facing portion and the end surface of the terminal electrode. The non-joint region is formed without the connection member between a periphery of the joint region and the holding portion.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: October 27, 2020
    Assignee: TDK CORPORATION
    Inventors: Norihisa Ando, Sunao Masuda, Masahiro Mori, Kayou Matsunaga, Kosuke Yazawa
  • Patent number: 10796990
    Abstract: A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chen, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10784048
    Abstract: A capacitor component includes a body including a dielectric layer and first and second internal electrodes, alternately disposed in a first direction, and first and second external electrodes, respectively disposed on opposite end surfaces of the body in a second direction, perpendicular to the first direction in the body. An amorphous second phase is disposed at an interface between the first and second internal electrodes and the dielectric layer, and ls/le is between 0.02 and 0.07, where ls is a total length of the amorphous second phase disposed in a boundary line between the first or second internal electrode and the dielectric layer in the second direction and le is a length of the first or second internal electrode in the second direction.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: September 22, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10777360
    Abstract: A chip capacitor and a method for manufacturing the chip capacitor, where the chip capacitor includes a substrate, a first external electrode disposed on the substrate, a second external electrode disposed on the substrate, capacitor elements formed on the substrate and connected between the first external electrode and the second external electrode, and fuses that are formed on the substrate, are each interposed between the capacitor elements and the first external electrode or the second external electrode, and are capable of disconnecting each of the capacitor elements.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 15, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Hiroyuki Okada, Yasuhiro Fuwa
  • Patent number: 10777359
    Abstract: A multilayer ceramic capacitor and a manufacturing method thereof are disclosed. The multilayer ceramic capacitor includes a base part including ceramic dielectrics, and inner electrodes formed in the ceramic dielectrics and arranged in interval by a staggered manner; two first outer electrodes of outer electrode layers are sintered and formed on two sides of the base part, and in electrical contact with the inner electrode terminals of the inner electrodes. Second outer electrodes are formed on outer parts of the two first outer electrodes. The inner electrodes and the first outer electrodes have barium titanate powder and nickel powder with average particle diameters in range of 0.2 ?m to 0.4 ?m, so that the inner electrodes are in good electrical contact with the first outer electrodes, to improve binding strength and reduce peeling of the first outer electrodes from the inner electrodes.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 15, 2020
    Assignee: Holy Stone Enterprise Co., Ltd.
    Inventors: Atsuo Nagai, Keisuke Seino, Sheng-Yi Chen
  • Patent number: 10770236
    Abstract: A multilayer ceramic electronic component array includes: a plurality of multilayer ceramic electronic components; a first terminal structure electrically connected to first external electrodes of each of the plurality of multilayer ceramic electronic components; a second terminal structure electrically connected to second external electrodes of each of the plurality of multilayer ceramic electronic components; a first conductive bonding member bonding the first external electrodes of each of the plurality of multilayer ceramic electronic components and the first terminal structure; a second conductive bonding member bonding the second external electrodes of each of the plurality of multilayer ceramic electronic components and the second terminal structure; and a ceramic bonding member contacting first surfaces of each of the ceramic bodies of each of the plurality of multilayer ceramic electronic components and disposed to extend to second surfaces of each of the ceramic bodies.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ki Young Kim, Beom Joon Cho, Sang Soo Park, Woo Chul Shin
  • Patent number: 10763043
    Abstract: An electronic device includes a chip component and a metal terminal. The chip component includes an element body containing laminated internal electrodes and a terminal electrode formed outside the element body to connect with ends of the internal electrodes. The metal terminal is connectable with the terminal electrode of the chip component. The metal terminal includes an electrode facing portion, a holding portion, and a mount portion. A connection member connecting between the electrode facing portion and the end surface of the terminal electrode exists in a joint region in a predetermined range. A non-joint region is formed between an edge of the joint region and the holding portion. A non-joint gap between the electrode facing portion and the end surface of the terminal electrode becomes larger toward the holding portion in the non-joint region.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK CORPORATION
    Inventors: Norihisa Ando, Sunao Masuda, Masahiro Mori, Kayou Matsunaga, Kosuke Yazawa
  • Patent number: 10720278
    Abstract: A multilayer ceramic capacitor with decreased high voltage stress defects and a board having the same may include a body formed by stacking a plurality of dielectric layers and a plurality of first and second internal electrodes in a width direction, the first and second internal electrodes including body portions overlapping each other and lead portions exposed to a mounting surface of the body and disposed to be spaced apart from each other, respectively; and first to third external electrodes disposed on the mounting surface of the capacitor body to be connected to the lead portions, respectively, wherein the body portions of the first and second internal electrodes have different areas from each other.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Young Heon Oh, Se Hwan Bong, Young Ha Kim, Dong Gun Kim
  • Patent number: 10672563
    Abstract: The present invention is directed to a surface mount coupling capacitor and a circuit board containing a surface mount coupling capacitor. The coupling capacitor includes a main body containing at least two sets of alternating dielectric layers and internal electrode layers. The coupling capacitor includes external terminals electrically connected to the internal electrode layers wherein the external terminals are formed on a top surface of the coupling capacitor and a bottom surface of the coupling capacitor opposing the top surface of the coupling capacitor.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 2, 2020
    Assignee: AVX Corporation
    Inventor: Jeffrey Cain
  • Patent number: 10658115
    Abstract: A method for manufacturing a capacitor component includes an operation of sintering under a moderately-or-more reducing atmosphere for hydrogen, a body in which a plurality of dielectric layers having internal electrodes printed thereon are laminated; a first reoxidation operation of subjecting the sintered body to a first reoxidation heat treatment under an oxidizing atmosphere; and a second reoxidation operation of subjecting the body having undergone the first reoxidation heat treatment to a second reoxidation heat treatment under an oxidizing atmosphere.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hye Won Ryoo, Ji Hong Jo, Ho In Jun, Seok Keun Ahn, Ji Hye Yu, A Reum Jun, Gi Seok Jeong, Seon Young Yoo
  • Patent number: 10658112
    Abstract: A multilayer capacitor includes a capacitor body including first and second internal electrodes disposed alternately in a width direction; first and second external electrodes spaced apart from each other on a mounting surface; and a first insulating layer disposed between the first and second external electrodes, in which the first and second internal electrodes each include a body portion, a first lead portion extending from the body portion toward the mounting surface and electrically connected to the first and second external electrodes, and a second lead portion extending from the body portion toward a surface of the capacitor body opposing the mounting surface, and the first and second lead portions extend from each body portion in a diagonal direction relative to each other.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Heung Kil Park, Jong Hwan Park
  • Patent number: 10622295
    Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Brunschwiler, Sebastian Gerke, Stefano Sergio Oggioni
  • Patent number: 10622438
    Abstract: A multi-layer electronic device is disclosed that comprises a ceramic layer, a first electrode layer, and a second electrode layer. The first electrode layer contains a first tab portion extending to the first lateral edge of the ceramic layer, the first electrode layer further defining a first cut-out region. The second electrode layer contains a second tab portion extending to the first lateral edge of the ceramic layer, the second electrode layer further defining a second cut-out region. The first tab portion of the first electrode layer is offset from the second tab portion of the second electrode layer in the longitudinal direction so that a first gap region is formed within which the first tab portion does not overlap the second tab portion. Further, the first cut-out region at least partially overlaps the second cut-out region.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 14, 2020
    Assignee: AVX Corporation
    Inventors: Andrew P. Ritter, Marianne Berolini
  • Patent number: 10622296
    Abstract: A circuitized substrate for mounting at least one electronic component having a plurality of terminals. The circuitized substrate includes a first portion of electrical insulating material embedding a first electric circuit for coupling a first subset of the terminals. The first electric circuit including one or more patterned conductive layers of electrically conductive material extending parallel to a plane of the circuitized substrate. The circuitized substrate further includes a second portion of electrically conductive material. One or more insulating elements of electrical insulating material cross the second portion transversally to the plane to insulate a plurality of conductive elements thereof for coupling a second subset of the terminals. One or more auxiliary components of the electronic component are mounted on the second portion. Each auxiliary component having a first terminal and a second terminal coupled with a first one and a second one, respectively, of a pair of the conductive elements.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas J. Brunschwiler, Sebastian Gerke, Stefano Sergio Oggioni
  • Patent number: 10601335
    Abstract: A power inverter circuit includes a capacitor and a power module. The capacitor includes a positive plate and a negative plate that are spaced apart along opposing sides of the capacitor and extend toward each other along a common side of the capacitor. The power module includes a positive connector and a negative connector that are connected to the positive plate and the negative plate, respectively, and are spaced apart and extend parallel across from each other.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: March 24, 2020
    Assignee: Apple Inc.
    Inventors: Javier Ruiz, Paul M. White
  • Patent number: 10580574
    Abstract: An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The pair of external terminals include bonding portions disposed on a top surface of the interposer body, mounting portions disposed on a bottom surface of the interposer body, and connection portions disposed on end surfaces of the interposer to connect the bonding portions and the mounting portions to each other. The mounting portions have lengths greater than lengths of the bonding portions in a direction of connection of the pair of external terminals.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Yoon Kim, Sang Soo Park, Woo Chul Shin
  • Patent number: 10580582
    Abstract: A multilayer electronic component includes a multilayer capacitor including a pair of external electrodes respectively formed on both ends opposing each other, and a pair of frame terminals having coupling holes allowing the external electrodes of the multilayer capacitor to be inserted, and separating the multilayer capacitor from a mounting surface, wherein band portions of the external electrodes are bonded to inner surfaces of the coupling holes.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyeong Jun Kim, Se Hwan Bong, Mi Ok Park, Jeong Bong Park, Hang Kyu Cho
  • Patent number: 10581166
    Abstract: There is disclosed a multi-band reconfigurable antenna device having at least one radiating element. The radiating element is connected to a single port by way of at least first and second matching circuits arranged in parallel. A high pass filter is provided between the first matching circuit and the radiating element so as to allow passage of a first, higher frequency RF signal through the first matching circuit. A low pass filter is provided between the second matching circuit and the at least one radiating element so as to allow passage of a second, lower frequency RF signal through the second matching circuit. The high pass filter blocks passage of the second, lower frequency RF signal through the first matching circuit, and the low pass filter blocks passage of the first, higher frequency RF signal through the second matching circuit. The first and second matching circuits are adjustable independently of each other so as to allow the first and second RF signals to be tuned independently of each other.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 3, 2020
    Assignee: Smart Antenna Technologies Ltd.
    Inventor: Sampson Hu
  • Patent number: 10575395
    Abstract: A galvanic isolator includes a multi-layer printed circuit board (PCB) including a dielectric material having a top side and a bottom side. An RF transmission line is embedded within the PCB including a plurality of conductor traces spaced apart from one another to include a plurality of gaps (G1 and G2) in a path of the RF transmission line to provide an inline distributed capacitor that together with an impedance of the RF transmission line forms a bandpass (BP) filter. A top metal layer is on the top side and a bottom metal layer on the bottom side connected to one another by a plurality of metal filled vias on respective sides of the RF transmission line. The top metal layer and bottom metal layer each also include at least one gap.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 25, 2020
    Assignee: Honeywell International Inc.
    Inventor: Fouad Nusseibeh
  • Patent number: 10566139
    Abstract: A ceramic electronic device includes a chip component, a metal terminal, and a conductive connection member. The component includes a terminal electrode surface on which a terminal electrode is formed. The metal terminal includes an opposing surface to the electrode surface. The connection member contains at least Sn and Sb and connects the terminal electrode surface and the opposing surface. The connection member includes a first part and a second part. In the first part, a distance between the terminal electrode surface and the opposing surface is a first distance, and Sb/Sn is a first value. In the second part, a distance between the terminal electrode surface and the opposing surface is a second distance being smaller than the first distance, and Sb/Sn is a second value being larger than the first value.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: February 18, 2020
    Assignee: TDK CORPORATION
    Inventors: Norihisa Ando, Sunao Masuda, Masahiro Mori, Kayou Matsunaga, Kosuke Yazawa
  • Patent number: 10566137
    Abstract: A multilayer electronic component includes: a capacitor body including an active region including first and second internal electrodes and upper and lower cover regions; first and second external electrodes including first and second connected portions connected to the first and second internal electrodes and first and second band portions, respectively; and first and second bump terminals having conductive layers and disposed on the first and second band portions, respectively, wherein BW/3?G?BW and T/5<ET<T/2, where BW is a width of each of the first and second band portions, T is a thickness of each of the first and second connected portions, G is a width of each of the first and second bump terminals, and ET is a thickness of each of the first and second bump terminals.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Se Hun Park, Gu Won Ji, Heung Kil Park
  • Patent number: 10546693
    Abstract: In an embodiment, a multilayer ceramic capacitor 10 is constituted in such a way that its capacitor body 11 houses a capacitance part which is halved in the third direction d3, along a shared internal electrode layer 11a3 serving as a boundary, into a high-capacitance part HC and a low-capacitance part LC. When the capacitor body 11 is cut along a surface crossing at right angles with the first direction d1, the revealed cross-sectional shape of the shared internal electrode layer 11a3 has a cross-sectional shape where a curved part CP that projects toward the dielectric layer 11b2 on low-capacitance part LC side adjoining the shared internal electrode layer 11a3, is present on both sides in the second direction d2, and also in between.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 28, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Atsushi Imai
  • Patent number: 10541221
    Abstract: A fan-out semiconductor package includes a core member having a through-hole in which a semiconductor chip is disposed. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. An encapsulant encapsulates at least a portion of the semiconductor chip. A connection member is disposed on the active surface of the semiconductor chip and includes a redistribution layer electrically connected to the connection pads of the semiconductor chip. A passivation layer is disposed on the connection member. The fan-out semiconductor package further has a slot spaced part from the through-hole and penetrating through at least a portion of the core member or the passivation layer.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Jin Seol, Myung Sam Kang, Young Gwan Ko
  • Patent number: 10529492
    Abstract: A ceramic electronic component includes a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, first and second external electrodes each including a connection portion disposed on a side surface of the body and a band portion extending from the connection portion to portions of upper/lower and front/rear surfaces of the body, first and second resin layers each disposed between the band portion and the body and extending from an end of the band portion towards each side surface by a predetermined length, in which the predetermined length is within a range of 3 ?m to 200 ?m.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 7, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Eui Hyun Jo, Hyun Hee Gu, Jang Yeol Lee, Jong Ho Lee
  • Patent number: 10522286
    Abstract: A dielectric film for a film capacitor includes a center portion made of a polymer and composite oxide particles and end portions made of only a polymer. The end portions are provided on both sides of the center portion.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: December 31, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Takahiro Saito
  • Patent number: 10504651
    Abstract: A multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrodes are alternately stacked, and a pair of external electrodes provided on the corresponding surfaces of the laminate. The laminate includes first and second principal surfaces facing each other in its thickness direction, first and second end surfaces facing each other in its lengthwise direction, and first and second side surfaces facing each other in its width direction. The external electrodes each include a metal layer covering the internal electrodes extended to the corresponding one of the end surfaces, a baked layer including glass and metal covering the metal layer, and a plated film covering the baked layer.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 10, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasuhiro Nishisaka, Akito Mori
  • Patent number: 10505099
    Abstract: A multi-layer component having a main body including a stack of alternately arranged dielectric layers and internal electrode layers. In an insulation region on the outer sides of the main body a length of a connecting line between adjacent internal electrode layers of unlike polarity is greater than a direct distance between the adjacent electrode layers. A method for producing a multi-layer component is also provided. The method includes providing a main body including a stack of alternately arranged dielectric layers and internal electrode layers. The method also includes extending the connecting line between adjacent internal electrode layers of unlike polarity on the outer sides of the main body.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 10, 2019
    Assignee: Epcos AG
    Inventor: Martin Galler
  • Patent number: 10497516
    Abstract: An electronic component includes a laminated body including first and second end surfaces, first and second side surfaces, and first and second principal surfaces, a first fired electrode layer on the first end surface, and a second fired electrode layer on the second end surface; a first external electrode on the first end surface; and a second external electrode on the second end surface. The first external electrode includes a first fired electrode layer, the second external electrode includes a second fired electrode layer, each of the first and second fired electrode layers includes a first region on the laminated body and a second region covering the first region, the first region includes voids and glass, and the second region includes less voids and glass than in the first region.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shuichi Ito, Hirokazu Yamaoka
  • Patent number: 10497653
    Abstract: A decoupling capacitor includes: two capacitor cells sharing the same well; a first trench isolation passing through the well between the two cells without reaching the bottom of the well; and a contact with the well formed in each cell.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: December 3, 2019
    Assignees: STMICROELECTRONICS (CROLLES 2) SAS, STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Mathieu Lisart, Benoit Froment
  • Patent number: 10497517
    Abstract: A multilayer ceramic capacitor that includes a multilayer body with dielectric layers and inner electrode layers and having a first main surface, a second main surface, a first side surface, a second side surface, a first end surface, and a second end surface; and an outer electrode on at least one of the end surfaces. The outer electrode includes a resistor layer on the at least one end surface of the multilayer body, a conductive layer on the resistor layer, and a plating layer on the conductive layer. The resistor layer contains a metallic phase, glass, and an oxide, and the resistor layer has a metallic phase content of 7.5 vol % to 15.6 vol % relative to an area of a section of the resistor layer, and the metallic phase has an average particle size of 1.6 ?m or less.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 3, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Toshikazu Makino, Hidehiko Tanaka
  • Patent number: 10483041
    Abstract: A first outer electrode and first inner electrodes are supplied with an anode potential and a second outer electrode and second inner electrodes are supplied with a cathode potential when a monolithic ceramic capacitor is mounted and in use. The first outer electrode supplied with the anode potential has a thickness that is greater than a thickness of the second outer electrode supplied with the cathode potential.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshito Saito, Satoshi Matsuno, Shinji Otani, Tomochika Miyazaki, Yasuhiro Nishisaka
  • Patent number: 10483048
    Abstract: A capacitor-type power supply unit including: a positive bus to which a plurality of capacitor is connected in parallel at each positive-electrode terminal thereof with maintaining equal intervals therebetween, and extends in a parallel direction; and an negative bus to which the plurality of capacitor is connected in parallel, at each negative-electrode terminal thereof with maintaining equal intervals therebetween, and extends in the parallel direction, in which the positive bus has a positive-electrode-side external connection part that is set at a position (SD) separated from the positive-electrode first end by a range of 20% to 30% of the total length in the longitudinal direction thereof, and the negative bus has an negative-electrode-side external connection part that is set at a position (SD) separated from the negative-electrode second end by a range of 20% to 30% of the total length in the longitudinal direction thereof.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: November 19, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Shogo Nagayoshi, Shinya Watanabe, Yasuhisa Saito, Hitoshi Saito, Shinyu Hirayama, Hironori Sawamura
  • Patent number: 10485103
    Abstract: An item may include fabric having insulating and conductive yarns or other strands of material. The conductive strands may form signal paths. Electrical components can be mounted to the fabric. Each electrical component may have an electrical device such as a semiconductor die that is mounted on an interposer substrate. The interposer may have contacts that are soldered to the conductive strands. A protective cover may encapsulate portions of the electrical component. To create a robust connection between the electrical component and the fabric, the conductive strands may be threaded through recesses in the electrical component. The recesses may be formed in the interposer or may be formed in a protective cover on the interposer. Conductive material in the recess may be used to electrically and/or mechanically connect the conductive strand to a bond pad in the recess. Thermoplastic material may be used to seal the solder joint.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 19, 2019
    Assignee: Apple Inc.
    Inventors: Daniel D. Sunshine, David M. Kindlon, Michael B. Nussbaum, Andrew L. Rosenberg, Andrew Sterian, Breton M. Saunders, Christopher A. Schultz, David A. Bolt, Mark J. Beesley, Peter W. Mash, Steven Keating, Chang Liu, Lan Hoang