Abstract: A semiconductor device including a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a semiconductor material causing an increased ON current and/or a reduced OFF current as compared to Si.

Abstract: A process of forming a gate insulating film in a silicon carbide semiconductor device. The process includes performing a first stage of a nitriding heat treatment by a gas containing oxygen and nitrogen, followed by depositing an oxide film, and then performing a second stage of the nitriding heat treatment by a gas containing nitric oxide and nitrogen. The amount of nitrogen at the treatment starting point of the first stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment starting point of the second stage of the nitriding heat treatment. The amount of nitrogen at the treatment ending point of the second stage of the nitriding heat treatment is greater than the amount of nitrogen at the treatment ending point of the first stage of the nitriding heat treatment.

Abstract: A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

Abstract: Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Abstract: One embodiment provides a semiconductor device. The device comprises a substrate having a first face and a second face, a well region, a source region disposed in the well region, a contact region contacting the well region and the source region, a Schottky region, and a source metal layer. A first part of the source metal layer contacts the Schottky region to form a Schottky diode. The Schottky region is surrounded by the contact region and the well region in a first plane perpendicular to a direction from the first face toward the second face.

Abstract: A semiconductor device includes a region of semiconductor material comprising a shielded-gate trench structure. The shielded-gate trench structure includes an active trench, an insulated shield electrode in the lower portion of the active trench, an insulated gate electrode adjacent to the gate dielectric in an upper portion of the active trench, and an inter-pad dielectric (IPD) interposed between the gate electrode and the shield electrode. A conductive region is within the active trench and extends through the gate electrode and the IPD and is electrically connected to the shield electrode. The conductive region is electrically isolated from the gate electrode. The gate electrode comprises a shape that is uninterrupted on at least one side the conductive region in a top view so that the gate electrode.

Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Abstract: A memory device, a memory system, and/or a method of operating a memory system includes measuring, using processing circuitry, an erase program interval (EPI) of a memory group included in a non-volatile memory (NVM), the EPI being a time period from an erase time point to a program time point of the memory group, determining, using the processing circuitry, a plurality of program modes based on a number of data bits stored in each memory cell of the memory group, selecting, using the processing circuitry, a program mode for the memory group from the plurality of program modes, based on the measured EPI of the memory group, and performing, using the processing circuitry, a program operation on the memory group corresponding to the selected program mode.

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

Abstract: According to the embodiment of the invention, the semiconductor device includes a semiconductor member, a first electrode, a second electrode, a third electrode, a first conductive member, and a first insulating member. The first semiconductor member includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region includes one of a first material and a second material. The third semiconductor region is provided between at least a part of the first semiconductor region and the second semiconductor region. The first electrode is electrically connected with the first semiconductor region. The second electrode is electrically connected with the second semiconductor region. At least a part of the third semiconductor region is between an other portion of the third electrode and the first conductive member. At least a part of the first insulating member is between the third electrode and the semiconductor member.

Abstract: A semiconductor device includes a junction field effect transistor (JFET) on a silicon-on-insulator (SOI) substrate. The JFET includes a gate with a first gate segment contacting the channel on a first lateral side of the channel, and a second gate segment contacting the channel on a second, opposite, lateral side of the channel. The first gate segment and the second gate segment extend deeper in the semiconductor layer than the channel. The JFET further includes a drift region contacting the channel, and may include a buried layer having the same conductivity type as the channel, extending at least partway under the drift region.

Abstract: A method for fabricating an electronic device includes providing an engineered substrate structure comprising a III-nitride seed layer, forming GaN-based functional layers coupled to the III-nitride seed layer, and forming a first electrode structure electrically coupled to at least a portion of the GaN-based functional layers. The method also includes joining a carrier substrate opposing the GaN-based functional layers and removing at least a portion of the engineered substrate structure. The method further includes forming a second electrode structure electrically coupled to at least another portion of the GaN-based functional layers and removing the carrier substrate.

Abstract: A silicon carbide substrate has a first conductivity type. The silicon carbide substrate has a first surface provided with a first electrode and a second surface provided with first trenches arranged to be spaced from one another. A gate layer covers an inner surface of each of the first trenches. The gate layer has a second conductivity type different from the first conductivity type. A filling portion fills each of the first trenches covered with the gate layer. A second electrode is separated from the gate layer and provided on the second surface of the silicon carbide substrate. A gate electrode is electrically insulated from the silicon carbide substrate and electrically connected to the gate layer. Thereby, a silicon carbide semiconductor device capable of being easily manufactured can be provided.

Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.

Abstract: According to one embodiment, a junction type field effect transistor includes a first conductive type semiconductor substrate, a first conductive type drift layer, a second conductive type gate region, a first conductive type channel layer, a first conductive type source region, a source electrode, a drain electrode, a second conductive type gate contact layer, and a gate electrode. The drift layer is provided on a first main surface of the semiconductor substrate. The gate region is provided on a surface of the drift layer. The channel layer is provided on the drift layer and the gate region. The source region is provided on a surface of the channel layer to face the gate region, and has an impurity concentration higher than the channel layer. The source electrode is provided on the channel layer with Schottky contact and on the source region with ohmic contact.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: An electrical circuit includes first and second transistors. Each transistor includes a substrate and, positioned thereon, a first electrically conductive material layer including a reentrant profile functioning as a gate. First and second discrete portions of a second electrically conductive material layer are in contact with first and second portions, respectively, of a semiconductor material layer in contact with an electrically insulating material layer, both of which conform to the reentrant profile. The first and second discrete portions are source/drain and drain/source electrodes of the first and second transistors, respectively. A third electrically conductive material layer, in contact with a third portion of the semiconductor material layer, is positioned over the gate, but is not in electrical contact with it.

Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

Abstract: A wide band gap semiconductor device having a JFET, a MESFET, or a MOSFET mainly includes a semiconductor substrate, a first conductivity type semiconductor layer, and a first conductivity type channel layer. The semiconductor layer is formed on a main surface of the substrate. A recess is formed in the semiconductor layer in such a manner that the semiconductor layer is divided into a source region and a drain region. The recess has a bottom defined by the main surface of the substrate and a side wall defined by the semiconductor layer. The channel layer has an impurity concentration lower than an impurity concentration of the semiconductor layer. The channel layer is formed on the bottom and the side wall of the recess by epitaxial growth.

Abstract: A semiconductor device includes a III-nitride substrate and a channel structure coupled to the III-nitride substrate. The channel structure comprises a first III-nitride epitaxial material and is characterized by one or more channel sidewalls. The semiconductor device also includes a source region coupled to the channel structure. The source region comprises a second III-nitride epitaxial material. The semiconductor device further includes a III-nitride gate structure coupled to the one or more channel sidewalls, a gate metal structure in electrical contact with the III-nitride gate structure, and a dielectric layer overlying at least a portion of the gate metal structure. A top surface of the dielectric layer is substantially co-planar with a top surface of the source region.

Abstract: Embodiments of the invention relate to field effect transistors. The field effect transistor includes a gate electrode for providing a gate field, a first electrode including a conductive material having a low carrier density and a low density of electronic states, a second electrode, and a semiconductor. Contact barrier modulation includes barrier height lowering of a Schottky contact between the first electrode and the semiconductor. In some embodiments of the invention, a vertical field effect transistor employs an electrode comprising a conductive material with a low density of states such that the transistors contact barrier modulation comprises barrier height lowering of the Schottky contact between the electrode with a low density of states and the adjacent semiconductor by a Fermi level shift.

Abstract: Described herein are embodiments of a vertical power transistor having drain and gate terminals located on the same side of a semiconductor body and capable of withstanding high voltages in the off-state, in particular voltages of more than 100V.

Abstract: A vertical transistor comprises a semiconductor region, a pillar region formed on the semiconductor region, a gate insulating film formed so as to cover a side surface of the pillar region, a gate electrode formed on the gate insulating film, a first impurity diffusion region formed in an upper portion of the pillar region, and a second impurity diffusion region formed in the semiconductor region so as to surround the pillar region. The first impurity diffusion region is formed so as to be spaced from the side surface of the pillar region.

Abstract: A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.

Abstract: A semiconductor device includes a first insulating film formed between a gate electrode and a first flat semiconductor layer, and a sidewall-shaped second insulating film formed to surround an upper sidewall of a first columnar silicon layer while contacting an upper surface of the gate electrode and to surround a sidewall of the gate electrode and the first insulating film. The semiconductor device further includes a metal-semiconductor compound formed on each of an upper surface of a first semiconductor layer of the second conductive type formed in the entirety or the upper portion of the first flat semiconductor layer, and an upper surface of the second semiconductor layer of the second conductive type formed in the upper portion of the first columnar semiconductor layer.

Abstract: A semiconductor device includes a III-nitride substrate, a first III-nitride epitaxial layer coupled to the III-nitride substrate and having a mesa, and a second III-nitride epitaxial layer coupled to a top surface of the mesa. The semiconductor device further includes a III-nitride gate structure coupled to a side surface of the mesa, and a spacer configured to provide electrical insulation between the second III-nitride epitaxial layer and the III-nitride gate structure.

Abstract: A semiconductor structure includes a GaN substrate with a first surface and a second surface. The GaN substrate is characterized by a first conductivity type and a first dopant concentration. A first electrode is electrically coupled to the second surface of the GaN substrate. The semiconductor structure further includes a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the GaN substrate and a second GaN layer of a second conductivity type coupled to the first GaN epitaxial layer. The first GaN epitaxial layer comprises a channel region. The second GaN epitaxial layer comprises a gate region and an edge termination structure. A second electrode coupled to the gate region and a third electrode coupled to the channel region are both disposed within the edge termination structure.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Abstract: A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction, a gate region at least partially surrounding the channel region, having a first surface coupled to the drift region and a second surface on a side of the gate region opposing the first surface, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source.

Abstract: A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region and a source contact electrically coupled to the source. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.

Abstract: A structure and method for fabricating a light emitting diode and a light detecting diode on a silicon-on-insulator (SOI) wafer is provided. Specifically, the structure and method involves forming a light emitting diode and light detecting diode on the SOI wafer's backside and utilizing a deep trench formed in the wafer as an alignment marker. The alignment marker can be detected by x-ray diffraction, reflectivity, or diffraction grating techniques. Moreover, the alignment marker can be utilized to pattern openings and perform ion implantation to create p-n junctions for the light emitting diode and light detecting diode. By utilizing the SOI wafer's backside, the structure and method increases the number of light emitting diodes and light detecting diodes that can be formed on a SOI wafer, enables an increase in overall device density for an integrated circuit, and reduces attenuation of light signals being emitted and detected by the diodes.

Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.

Abstract: Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

Abstract: A normally-off JFET is provided. The normally-off JFET includes a channel region of a first conductivity type, a floating semiconductor region of a second conductivity type adjoining the channel region, and a contact region of the first conductivity type adjoining the floating semiconductor region. The floating semiconductor region is arranged between the contact region and the channel region. Further, a normally-off semiconductor switch is provided.

Abstract: A semiconductor device 100 includes: a first silicon carbide layer 120 arranged on the principal surface of a semiconductor substrate 101; a first impurity region 103 of a first conductivity type arranged in the first silicon carbide layer; a body region 104 of a second conductivity type; a contact region 131 of the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity region 103 and which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift region 102 of the first conductivity type; and a first ohmic electrode 122 in ohmic contact with the first impurity region 103 and the contact region 131, wherein: a contact trench 121, which penetrates through the first impurity region 103, is provided in the first silicon carbide layer 120; and the first ohmic electrode 122 is arranged in the contact trench 121 and is in contact with the contact region 131 on at least a portion of a side wall lower portio

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A trench IGBT is disclosed. One embodiment includes an embedded structure arranged above a collector region and selected from a group consisting of a porous semiconductor region, a cavity, and a semiconductor region including additional scattering centers for holes, the embedded structure being arranged below the body contact region such that the embedded structure and the body contact region overlap in a horizontal projection.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: A semiconductor device formed on a semiconductor substrate may include a component formed in a contact trench located in an active cell region. The component may comprise a barrier metal deposited on a bottom and portions of sidewalls of the contact trench and a tungsten plug deposited in a remaining portion of the contact trench. The barrier metal may comprise first and second metal layers. The first metal layer may be proximate to the sidewall and the bottom of the contact trench. The first metal layer may include a nitride. The second metal layer may be between the first metal layer and the tungsten plug and between the tungsten plug and the sidewall. The second metal layer covers portions of the sidewalls of not covered by the first metal layer.

Abstract: A bipolar semiconductor device with a hole current redistributing structure and an n-channel IGBT are provided. The n-channel IGBT has a p-doped body region with a first hole mobility and a sub region which is completely embedded within the body region and has a second hole mobility which is lower than the first hole mobility. Further, a method for forming a bipolar semiconductor device is provided.

Abstract: A junction field effect transistor includes a channel region, a gate region coupled to the channel region, a well tap region coupled to the gate region and the channel region, and a well region coupled to the well tap region and the channel region. A double gate operation is achieved by this structure as a voltage applied to the gate region is also applied to the well region through the well tap region in order to open the channel from both the gate region and the well region.

Abstract: A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 ?m to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of <5° from vertical. The devices can be made using normal (i.e., 0°) or near normal incident ion implantation. The devices have relatively uniform sidewall doping and can be made without angled implantation.

Abstract: Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.

Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Abstract: Provided are a semiconductor device having an MTJ element capable of intentionally shifting the variation, at the time of manufacture, of a switching current of an MRAM memory element in one direction; and a manufacturing method of the device. The semiconductor device has a lower electrode having a horizontally-long rectangular planar shape; an MTJ element having a vertically-long oval planar shape formed on the right side of the lower electrode; and an MTJ's upper insulating film having a horizontally-long rectangular planar shape similar to that of the lower electrode and covering the MTJ element therewith. As the MTJ's upper insulating film, a compressive stress insulating film or a tensile stress insulating film for applying a compressive stress or a tensile stress to the MTJ element is employed.

Abstract: A MOS transistor having an increased gate-drain capacitance is described. One embodiment provides a drift zone of a first conduction type. At least one transistor cell has a body zone, a source zone separated from the drift zone by the body zone, and a gate electrode, which is arranged adjacent to the body zone and which is dielectrically insulated from the body zone by a gate dielectric. At least one compensation zone of the first conduction type is arranged in the drift zone. At least one feedback electrode is arranged at a distance from the body zone, which is dielectrically insulated from the drift zone by a feedback dielectric and which is electrically conductively connected to the gate electrode.