Coupling well structure for improving HVMOS performance
A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
This application claims the benefit of U.S. Provisional Application No. 60/852,183, filed on Oct. 17, 2006, entitled “Coupling Well Structure for Improving HVMOS Performance,” which application is hereby incorporated herein by reference.
TECHNICAL FIELDThis invention relates generally to semiconductor devices, and more particularly to metal-oxide-semiconductor (MOS) devices, and even more particularly to the structure and manufacturing methods of high-voltage MOS devices.
BACKGROUNDHigh-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, AC/DC converters, etc. HVMOS devices typically include drain regions and laterally-diffused drain regions enclosing drain regions. Laterally-diffused drain regions are typically well regions having lower doping concentrations than the drain regions, thus having high breakdown electrical fields.
It is known that high electrical fields are typically generated at interface regions. For HVNMOS device 2, when a high voltage is applied between drain region 6 and source region 8, a high electrical field is generated at a region proximate p-n junction 16, which becomes the weak point of the HVNMOS device 2. The generation of the high electrical field causes the reduction in breakdown voltage of HVNMOS device 2. This problem worsens when the device dimensions become smaller, and thus the electrical fields become higher.
Novel methods for reducing electrical fields at p-n junctions are thus needed to improve breakdown voltages of high-voltage MOS devices.
SUMMARY OF THE INVENTIONIn accordance with one aspect of the present invention, a semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.
In accordance with another aspect of the present invention, a semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have an overlap region, an insulation region extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region, and a gate electrode on the gate dielectric.
In accordance with yet another aspect of the present invention, a semiconductor structure includes a substrate, a first well region having a first impurity of a first conductivity type overlying the substrate, a second well region having a second impurity of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have a space therebetween, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region, and a gate electrode on the gate dielectric.
In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes providing a substrate, forming a first well region of a first conductivity type overlying the substrate, forming a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, wherein a cushion region is formed adjoining the first and the second well regions, forming an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, forming a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and forming a gate electrode on the gate dielectric.
In accordance with yet another aspect of the present invention, a method of forming a semiconductor structure includes proving a substrate, forming a first well region of a first conductivity type overlying the substrate, forming a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have an overlap region, forming an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, forming a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region, and forming a gate electrode on the gate dielectric.
The cushion region between the p-well region and the n-well region increases the breakdown electrical field at the interface region of the p-well region and the n-well region. The breakdown voltage of the respective high-voltage device is thus increased.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The preferred embodiments of the present invention are described with reference to
Referring to
Referring to
In the embodiments discussed in preceding paragraphs, p-well regions 28 and 30 and n-well region 24 are formed by implanting substrate 20. In alternative embodiments, the well regions are formed by epitaxial growth. In an exemplary embodiment, as shown in
An epitaxial layer 25 is then epitaxially grown on NBL 23. Epitaxial layer 25 preferably comprises a semiconductor such as silicon, and more preferably the same material as substrate 20, and is preferably doped with one of the p-type and n-type impurities. Assuming p-type impurities are doped, the impurity concentration is then equal to the desired concentration of p-well regions 28 and 30. A photoresist (not shown) is then formed and patterned, exposing region 24. An n-type impurity implantation is then performed. The implanted n-type impurity neutralizes the p-type impurities in epitaxial layer 25 and convert the implanted region to n-well region 24. Un-implanted epitaxial regions thus form p-well regions 28 and 30. Alternatively, the epitaxial layer 25 may be doped with n-type impurities when grown, and implanted with p-type impurities.
In both
Referring to
Referring to
Alternatively, N+ regions 56 and 58 may be formed before the formation of P+ region 52, or formed after the formation of gate dielectric, gate electrode and gate spacers. One skilled in the art will realize the respective process steps.
A second embodiment of the present invention is illustrated in
The previously illustrated embodiments have asymmetric structures, wherein source and drain regions are in well regions with different conductivity types.
Although the preferred embodiments illustrate the formation of HVNMOS devices, one skilled in the art will realize the respective formation steps for forming HVPMOS devices, with the conductivity type of n-well region 24, p-well regions 28 and 30, and N+ regions 56 and 58, etc., reversed (refer to
Besides forming HVMOS devices, the concept of forming a cushion region to affect the distribution of electrical fields may be applied to the formation of other devices, such as diodes. By forming cushion regions between p-type and n-type regions of p-n junctions, the breakdown voltage of diodes can be improved.
An advantageous feature of the present invention is that n-well region 24 and p-well region 28 are separated from each other by cushion region 32. Inside cushion region 32, the net impurity concentration is low. In the embodiment shown in
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A semiconductor structure comprising:
- a substrate;
- a first well region of a first conductivity type overlying the substrate;
- a second well region of a second conductivity type opposite the first conductivity type overlying the substrate;
- a cushion region between and adjoining the first and the second well regions;
- an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;
- a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region; and
- a gate electrode on the gate dielectric.
2. The semiconductor structure of claim 1, wherein the cushion region is an overlap region of the first and the second well regions.
3. The semiconductor structure of claim 1, wherein the cushion region is a space between the first and the second well regions.
4. The semiconductor structure of claim 1 further comprising a third well region of the first conductivity type overlying the substrate, wherein the third well region is on an opposite side of the second well region than the first well region, and wherein the gate dielectric extends over the third well region.
5. The semiconductor structure of claim 4 further comprising a second cushion region between the second and the third well regions.
6. The semiconductor structure of claim 5, wherein one of the first and the second cushion regions is an overlap region, and the other is a spacing between neighboring well regions.
7. The semiconductor structure of claim 1, wherein the cushion region has a width of between about 10 Å and about 3 μm.
8. The semiconductor structure of claim 7, wherein the width is between about 0.3 μm and about 0.5 μm.
9. The semiconductor structure of claim 1, wherein the first conductivity type is selected from the group consisting of p-type and n-type.
10. The semiconductor structure of claim 1 further comprising:
- a drain region in the first well region and adjoining the insulation region; and
- a source region in the second well region and adjacent an edge of the gate electrode, wherein the source region and the drain region are of the first conductivity type.
11. A semiconductor structure comprising:
- a substrate;
- a first well region of a first conductivity type overlying the substrate;
- a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have an overlap region;
- an insulation region extending from a top surface of the first well region into the first well region;
- a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region; and
- a gate electrode on the gate dielectric.
12. The semiconductor structure of claim 11, wherein the overlap region has a width of between about 10 Å and about 3 μm.
13. The semiconductor structure of claim 12, wherein the width is between about 0.3 μm and about 0.5 μm.
14. A semiconductor structure comprising:
- a substrate;
- a first well region having a first impurity of a first conductivity type overlying the substrate;
- a second well region having a second impurity of a second conductivity type opposite the first conductivity type overlying the substrate, wherein the first and the second well regions have a space therebetween;
- an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region;
- a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has an edge directly over the insulation region; and
- a gate electrode on the gate dielectric.
15. The semiconductor structure of claim 14, wherein the space has a width of between about 10 Å and about 3 μm.
16. The semiconductor structure of claim 15, wherein the width is between about 0.3 μm and about 0.5 μm.
Type: Application
Filed: Nov 8, 2006
Publication Date: Sep 4, 2008
Inventors: Hsueh-Liang Chou (Jhubei City), Chen-Bau Wu (Zhubei City), Weng-Chu Chu (Qionglin Shiang), Tsung-Yi Huang (Hsin-Chu), Fu-Jier Fan (Hsinchu City)
Application Number: 11/594,508
International Classification: H01L 23/62 (20060101);