With Overvoltage Protective Means Patents (Class 257/355)
  • Patent number: 11127734
    Abstract: An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 11114429
    Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventor: James Karp
  • Patent number: 11107737
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 11088132
    Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 10, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Guangyang Wang
  • Patent number: 11088135
    Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 10, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hua Chung, Tai-Jui Wang, Chieh-Wei Feng
  • Patent number: 11088133
    Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Joung Cheul Choi, Chang Seok Song
  • Patent number: 11081881
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Divya Agarwal, Radhakrishnan Sithanandam
  • Patent number: 11069675
    Abstract: An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 20, 2021
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Hailian Liang, Qiang Xu, Xiaofeng Gu
  • Patent number: 11063429
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 13, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Ghislain Troussier, Jean Jimenez, Malathi Kar
  • Patent number: 11043554
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a plurality of ring-shaped regions, and a semi-insulating layer. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region surrounds the second semiconductor region, and is provided on the first semiconductor region. The ring-shaped regions surround the second semiconductor region. The second electrode is provided on the second semiconductor region. The third electrode is provided on the third semiconductor region. The semi-insulating layer contacts the first semiconductor region, the second electrode, the ring-shaped regions, and the third electrode. The ring-shaped regions include first and second ring-shaped regions provided between the first ring-shaped region and the third semiconductor region.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 22, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Daiki Yoshikawa
  • Patent number: 11043520
    Abstract: Provided is a light-receiving device including: a photoelectric conversion layer including a Group III-V semiconductor; a plurality of first electrically-conductive type regions in signal charges generated in the photoelectric conversion layer move; and a second electrically-conductive type region penetrating through the photoelectric conversion layer and provided between adjacent ones of the first electrically-conductive type regions.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 22, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Yoshigiwa
  • Patent number: 11044798
    Abstract: An ESD protection composite structure includes a link layer, a progressive layer, and a composite layer. The link layer is used for disposing the ESD protection composite structure on a substrate, wherein a material of the link layer includes a metal material. The progressive layer is disposed on the link layer, wherein the material of the progressive layer includes a non-stoichiometric metal oxide material, and an oxygen concentration in the non-stoichiometric metal oxide material is increased gradually away from the substrate in a thickness direction of the progressive layer. The composite layer is disposed on the progressive layer, wherein the composite layer includes a stoichiometric metal oxide material and a non-stoichiometric metal oxide material, and a ratio of the non-stoichiometric metal oxide material and the stoichiometric metal oxide material in the composite layer may make a sheet resistance value of the composite layer 1×107 ?/sq to 1×108 ?/sq.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 22, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Ding-Shiang Wang, Jia-Jen Chang, Ming-Sheng Leu, Tai-Sheng Chen, Chin-Te Shih
  • Patent number: 11037886
    Abstract: A semiconductor structure of a work unit module includes an encircling noise-resistance structure and a P-type substrate being defined with a chip region and a surrounding region surrounding the chip region. The surrounding area includes two first strip regions and two second strip regions. Each of the first strip regions is located between the second strip regions, and each of the second strip regions is located between the first strip regions. The encircling noise-resistance structure is located on the surrounding area, and includes first arrangement units and second arrangement units. The first arrangement unit is arranged in one of the first strip regions in a single row. The second arrangement unit is arranged in one of the second strip regions in a single row, and the long axis direction of the second arrangement unit is different from the long axis direction of the first arrangement unit.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 15, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ya Tseng, Wei-Cheng Yu, Bo-Yan Li, Wen-Tai Wang
  • Patent number: 11024625
    Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Ting Chen
  • Patent number: 11018128
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conducting type. A pad is provided on the semiconductor substrate. An internal circuit is provided on the semiconductor substrate. An electrostatic discharge protection element is provided between the pad and the internal circuit. The electrostatic discharge protection element comprises a first well of a second conducting type, a second well of a first conducting type, and a first electrode layer of a second conducting type. The first well of a second conducting type is provided in a surface region of the semiconductor substrate. The second well of a first conducting type is provided inside the first well in the surface region of the semiconductor substrate. The first electrode layer of a second conducting type is provided inside the second well in the surface region of the semiconductor substrate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Kutsukake
  • Patent number: 11011509
    Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 18, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jie Zeng, Raunak Kumar, Kyong Jin Hwang
  • Patent number: 11004812
    Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Hsin-Yu Pan, Ming-che Ho, Tzu Yun Huang, Yen-Fu Su
  • Patent number: 11004849
    Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 11, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Andrew Lewine
  • Patent number: 10985157
    Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 20, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chien-Shao Tang, Ting-Jui Lin, Hsiang-Ming Chou, Fang-Yu Chang
  • Patent number: 10978445
    Abstract: The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fang Lai, Liang-Yu Su, Hang Fan
  • Patent number: 10957773
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 10937781
    Abstract: An electronic device can include a source terminal, a gate terminal, and a protection circuit. The protection circuit can include a gate section including a first electrode and a second electrode, wherein the first electrode of the gate section is coupled to the gate terminal; and a source section including a first electrode and a second electrode, wherein the first electrode of the source section is coupled to the source terminal. The protection switch can include a control electrode, a first current-carrying electrode coupled to the gate terminal, and a second current-carrying electrode coupled to the source terminal. The second electrode of the gate section, the second electrode of the source section, and the control electrode of the protection switch can be coupled to one another. In an embodiment, the electronic device can further include an electronic component that is protected by the protection circuit.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Herbert De Vleeschouwer, Pierre Gassot, Piet Vanmeerbeek, Frederick Johan G Declercq, Aarnout Wieers, Woochul Jeon
  • Patent number: 10930637
    Abstract: A transient voltage suppressor is provided, comprising a heavily doped substrate connected to a first node, a first doped layer formed on the heavily doped substrate, a second doped layer formed on the first doped layer, a first heavily doped region and a second heavily doped region formed in the second doped layer and coupled to a second node, and a plurality of trenches arranged in the heavily doped substrate, having a depth not less than that of the first doped layer for electrical isolation. The heavily doped substrate, the second doped layer, and the second heavily doped region belong to a first conductivity type. The first doped layer and the first heavily doped region belong to a second conductivity type. By employing the proposed present invention, pn junctions of the transient voltage suppressor can be controlled beneath the surface, thereby reducing the junction capacitance effectively.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 23, 2021
    Assignee: Amazing Microelectronic Corp.
    Inventors: Yu-Shu Shen, Mei-Lian Fan
  • Patent number: 10930643
    Abstract: Some embodiments of the application provide a filter circuit that is based on a MOS field effect transistor and a chip including the same. The filter circuit includes a first MOS field effect transistor and an electrostatic discharge unit; a gate of the first MOS field effect transistor and a substrate form a filter capacitance during normal operation; the electrostatic discharge unit and the first MOS field effect transistor form a discharge path that transfers aggregated electrostatic charges to ground when an ESD event occurs.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 23, 2021
    Inventor: Jianxing Chen
  • Patent number: 10930641
    Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 2A) for an integrated circuit is disclosed. The circuit is formed on a substrate (P-EPI) having a first conductivity type. A buried layer (NBL 240) having a second conductivity type is formed below a face of the substrate. A first terminal (206) and a second terminal (204) are formed at a face of the substrate. A first ESD protection device (232) has a first current path between the first terminal and the buried layer. A second ESD protection device (216) has a second current path in series with the first current path and between the second terminal and the buried layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Akram A. Salman, Md Iqbal Mahmud
  • Patent number: 10910371
    Abstract: A method for detecting heat generated by a semiconductor device including a first MOS device and an active device on a substrate is provided. The method includes obtaining a first curve of a performance parameter of the first MOS device as a function of temperature when the active device is not operating, obtaining a second curve of the performance parameter of the first MOS device as a function of temperature when the active device is operating, and obtaining a heat generating condition of the active device according to a degree of deviation between the first curve and the second curve.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: February 2, 2021
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10903204
    Abstract: A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 26, 2021
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventors: Che-Hao Chuang, Chih-Ting Yeh, Kun-Hsien Lin
  • Patent number: 10892259
    Abstract: Apparatus having an array of memory cells might include a first transistor having a control gate, a first source/drain connected to a first contact for connection to peripheral circuitry, and a second source/drain connected to a second contact for connection to a data line selectively connected to a respective set of strings of series-connected memory cells of the array of memory cells; and a second transistor having a control gate, a first source/drain connected to the second contact, and a second source/drain connected to a third contact for connection to a common source selectively connected to each string of series-connected memory cells of the respective set of strings of series-connected memory cells for the data line.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Smith
  • Patent number: 10892258
    Abstract: An integrated “pull-down” driver circuit (210) is formed with a combination device consisting of an output driver transistor (N1) electrically coupled between a current source circuit (Ns) and the conductive pad, and an ESD bypass transistor (N3) electrically coupled in series with the output driver transistor, where one or more conductive interconnect layers connect the ESD bypass transistor in parallel with the current source circuit so that the ESD bypass transistor is in an off-state during normal operation and is activated to form a parasitic bipolar junction transistor with the output driver transistor to conduct ESD current between a first power supply conductor and the conductive pad during ESD events, and where a complementary integrated “pull-up” driver circuit may be formed with three corresponding PMOS transistors (P1, PS, P3) connected as shown between a second power supply conductor and the conductive pad.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: January 12, 2021
    Assignee: NXP B.V.
    Inventors: Marcin Grad, Paul H. Cappon, Taede Smedes
  • Patent number: 10886395
    Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: January 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: An-Chi Liu, Chun-Hsien Lin
  • Patent number: 10879231
    Abstract: An ESD protection SCR device includes an epitaxial layer provided on a P-type semiconductor substrate, the epitaxial layer having the P-type conductivity, element isolation layers provided on the epitaxial layer, the element isolation layers dividing the epitaxial layer into an anode region and a cathode region, a first well of an N-type conductivity, provided in a portion of the epitaxial layer corresponding to the anode region, a first impurity region provided on a surface of the first well, the first impurity region being connected to an anode terminal and having a high concentration P-type conductivity, a second well of the P-type conductivity, provided in a portion of the epitaxial layer corresponding to the cathode region, a second impurity region provided on a surface of the second well, the second impurity region being connected to a cathode terminal and having a high concentration N-type conductivity, and a floating well of the N-type conductivity, buried in the epitaxial layer.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: December 29, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Seok Soon Noh, Joon Tae Jang, Joon Hyeok Byeon, Young Chul Kim
  • Patent number: 10867991
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, James E. Davis, Warren L. Boyer, Jeffrey P. Wright
  • Patent number: 10868081
    Abstract: According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Wei Chang, Eng Huat Toh, Shyue Seng Tan, Ruchil Kumar Jain
  • Patent number: 10867988
    Abstract: The present disclosure relates to an integrated circuit. The integrated circuit comprises a silicon on insulator (SOI) device separated from a SOI substrate by an insulation layer. The SOI device comprises a power supply terminal, a ground terminal, a first I/O terminal and a second I/O terminal. An electrostatic discharge (ESD) protection circuit is integrated with the SOI device. The ESD protection circuit is configured to shunt current between two terminals of the SOI device during an ESD surge event. An electrostatic discharge (ESD) enhancement circuit is integrated with the SOI device. The ESD enhancement circuit is configured to clamping the SOI substrate to a lower potential of the two terminals of the SOI device.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Sheng-Fu Hsu
  • Patent number: 10854639
    Abstract: Provided is an active matrix substrate that includes a thin film transistor that has a first semiconductor layer and an ESD protection circuit. The ESD protection circuit includes a diode element. The diode element has a first electrode in a gate metal layer, a second semiconductor layer that overlaps a first electrode, and a second electrode and a third electrode electrically connected to a second semiconductor layer in a source metal layer. First and second electrodes of the diode element are electrically connected. The ESD protection circuit further includes a reserve diode structure. The reserve diode structure includes a fourth electrode in the gate metal layer and is in an electrically floating state, and a third semiconductor layer that is formed in the same layer as the first and second semiconductor layers and overlaps the fourth electrode with an insulation layer in between.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 1, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masakatsu Tominaga, Masahiro Yoshida, Yasuhiro Mimura, Akane Sugisaka
  • Patent number: 10825805
    Abstract: A transient voltage suppressor (TVS) device uses a punch-through silicon controlled rectifier (SCR) structure for the high-side steering diode and/or the low-side steering diode where the punch-through SCR structure realizes low capacitance at the protected node. In some embodiments, the breakdown voltage of the TVS device is tailored by connecting two or more forward biased diodes in series. The low capacitance TVS device can be configured for unidirectional or bidirectional applications. In some embodiments, the TVS device includes a MOS-triggered silicon controlled rectifier as the high-side steering diode. The breakdown voltage of the TVS device can be adjusted by adjusting the threshold voltage of the MOS transistor.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: November 3, 2020
    Assignee: Alpha & Omega Semiconductor (Cayman) Ltd.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 10818786
    Abstract: We disclose a III-nitride semiconductor based heterojunction power device, comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas of second conductivity type; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first gate terminal formed over the first III-nitride semiconductor region between the first terminal and the second terminal.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 27, 2020
    Assignee: CAMBRIDGE GAN DEVICES LIMITED
    Inventors: Florin Udrea, Loizos Efthymiou, Giorgia Longobardi, Martin Arnold
  • Patent number: 10818763
    Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Steven M. Shank, Michel J. Abou-Khalil, Siva P. Adusumilli
  • Patent number: 10811873
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit formed by an ESD event actuated transistor device. A bias current is generated in response to operation of a voltage independent current generator circuit. The bias current is sourced to ensure that the transistor device is deactuated after the ESD event is dissipated.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: October 20, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Vicky Batra, Radhakrishnan Sithanandam
  • Patent number: 10797171
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused MOSFET (LDMOS) and methods of manufacture. The structure includes: a gate structure having a drain region and a source region; and an oxidation extending from the gate structure to the drain region of the gate structure, the oxidation comprising a thinner oxide portion and a thicker oxide portion.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • Patent number: 10797044
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region. The device also includes a first gate structure on the semiconductor fin between the first doped region and the second doped region, and a first conductive structure electrically connecting the gate structure and the first doped region to a same potential. The ESD protection device can also have a third doped region and a second gate structure coupled to the same potential. The device also has a second conductive structure for connecting to a point between an external signal and a circuit to be protected.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 6, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10777956
    Abstract: Oscillation mitigation circuits are implemented in a system for supplying electric power to load circuit boards, for example, load circuit boards entirely immersed into a bath of dielectric heat transfer fluid. The oscillation mitigation circuits can be used to protect the load circuit boards, including the connectors mounted on these load circuit boards, from an anomalous behavior of the electric power. The oscillation mitigation circuits are coupled between wire bundles forming a portion of the electric power supply and the connectors mounted on the load circuit boards.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 15, 2020
    Assignee: TAS ENERGY, INC.
    Inventors: Abhishek Banerjee, William J. Bongers, Randall Erskine
  • Patent number: 10770577
    Abstract: A rectifier has a rectification circuit configured to rectify multi-phase alternating current generated by a rotating electric machine into direct current. The rectifier includes upper-arm semiconductor switching elements included in an upper arm of the rectification circuit, upper-arm protection diodes included in the upper arm and each being electrically connected in parallel with one of the upper-arm semiconductor switching elements, lower-arm semiconductor switching elements included in a lower arm of the rectification circuit, and lower-arm protection diodes included in the lower arm and each being electrically connected in parallel with one of the lower-arm semiconductor switching elements.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 8, 2020
    Assignee: DENSO CORPORATION
    Inventor: Toshinori Maruyama
  • Patent number: 10763393
    Abstract: A micro light emitting diode chip having a plurality of light-emitting regions, including a semiconductor epitaxial structure, a first electrode and a plurality of second electrodes disposed at interval is provided. The semiconductor epitaxial structure includes a first-type doped semiconductor layer, a plurality of second-type doped semiconductor layers and a plurality of light-emitting layers disposed at interval. The light-emitting layers are located between the first-type doped semiconductor layer and the second-type doped semiconductor layer. The light-emitting layers are located in the light-emitting regions respectively and electrically contact to the first-type doped semiconductor layer. The first electrode is electrically connected and contacts to the first-type doped semiconductor layers. The second electrodes are electrically connected to the second-type doped semiconductor layers. Furthermore, a display panel is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 1, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Yu-Yun Lo, Tzu-Yang Lin
  • Patent number: 10755949
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 25, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert R. Robison
  • Patent number: 10748862
    Abstract: A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 10748899
    Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 10749337
    Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alan Erik Segervall, Ross Anthony Pimentel, Sumantra Seth
  • Patent number: 10741637
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 11, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10741653
    Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Chun-Li Liu