With Overvoltage Protective Means Patents (Class 257/355)
  • Patent number: 10777956
    Abstract: Oscillation mitigation circuits are implemented in a system for supplying electric power to load circuit boards, for example, load circuit boards entirely immersed into a bath of dielectric heat transfer fluid. The oscillation mitigation circuits can be used to protect the load circuit boards, including the connectors mounted on these load circuit boards, from an anomalous behavior of the electric power. The oscillation mitigation circuits are coupled between wire bundles forming a portion of the electric power supply and the connectors mounted on the load circuit boards.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 15, 2020
    Assignee: TAS ENERGY, INC.
    Inventors: Abhishek Banerjee, William J. Bongers, Randall Erskine
  • Patent number: 10770577
    Abstract: A rectifier has a rectification circuit configured to rectify multi-phase alternating current generated by a rotating electric machine into direct current. The rectifier includes upper-arm semiconductor switching elements included in an upper arm of the rectification circuit, upper-arm protection diodes included in the upper arm and each being electrically connected in parallel with one of the upper-arm semiconductor switching elements, lower-arm semiconductor switching elements included in a lower arm of the rectification circuit, and lower-arm protection diodes included in the lower arm and each being electrically connected in parallel with one of the lower-arm semiconductor switching elements.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 8, 2020
    Assignee: DENSO CORPORATION
    Inventor: Toshinori Maruyama
  • Patent number: 10763393
    Abstract: A micro light emitting diode chip having a plurality of light-emitting regions, including a semiconductor epitaxial structure, a first electrode and a plurality of second electrodes disposed at interval is provided. The semiconductor epitaxial structure includes a first-type doped semiconductor layer, a plurality of second-type doped semiconductor layers and a plurality of light-emitting layers disposed at interval. The light-emitting layers are located between the first-type doped semiconductor layer and the second-type doped semiconductor layer. The light-emitting layers are located in the light-emitting regions respectively and electrically contact to the first-type doped semiconductor layer. The first electrode is electrically connected and contacts to the first-type doped semiconductor layers. The second electrodes are electrically connected to the second-type doped semiconductor layers. Furthermore, a display panel is also provided.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: September 1, 2020
    Assignee: PlayNitride Inc.
    Inventors: Yu-Hung Lai, Yu-Yun Lo, Tzu-Yang Lin
  • Patent number: 10755949
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 25, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam, Robert R. Robison
  • Patent number: 10749337
    Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alan Erik Segervall, Ross Anthony Pimentel, Sumantra Seth
  • Patent number: 10748899
    Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Kong-Beng Thei
  • Patent number: 10748862
    Abstract: A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 18, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Katsunori Misaki
  • Patent number: 10741653
    Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 11, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Chun-Li Liu
  • Patent number: 10741543
    Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Heng Chang, Kuo-Ji Chen, Ming-Hsiang Song
  • Patent number: 10741637
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a device forming region and an outside region, an impurity region of a second conductivity type formed in a surface layer portion of a first main surface in the device forming region, a field limiting region of a second conductivity type formed in the surface layer portion in the outside region and having a impurity concentration higher than that of the impurity region, and a well region of a second conductivity type formed in a region between the device forming region and the field limiting region in the surface layer portion in the outside region, having a bottom portion positioned at a second main surface side with respect to bottom portions of the impurity region and the field limiting region, and having a impurity concentration higher than that of the impurity region.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: August 11, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10714468
    Abstract: An optical integrated circuit device includes a semiconductor substrate and a first waveguide made of a first material and disposed over the semiconductor substrate. The first waveguide includes a parallel region and a tapered region. The optical integrated circuit device further includes a first cladding structure disposed over and surrounding the parallel region of the first waveguide, a first extension made of the first material and disposed over the semiconductor substrate, and an electrostatic discharge (ESD) protection structure electrically coupled to the first extension. The first extension physically contacts the parallel region of the first waveguide. The first extension includes a first portion within the first cladding structure and a second portion outside the first cladding structure.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 14, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Luca Maggi, Piero Orlandi
  • Patent number: 10714583
    Abstract: A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 14, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara, Julien Delalleau
  • Patent number: 10705766
    Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jean-Pierre Colinge, Carlos H. Diaz, Ta-Pen Guo
  • Patent number: 10692855
    Abstract: An ESD protection device structure compatible with CMOS process is disclosed. In the ESD protection device structure, a power source I/O unit or a signal I/O unit of an I/O circuit is electrically connected to an electrostatic discharge clamp circuit including multiple low-voltage PMOS structure are formed in the P-type substrate and connected in series. Source and gate on low voltage N-type well of first low-voltage PMOS structure are electrically connected to a high-voltage power terminal pad through a first power line, or electrically connected to a signal transmission terminal pad through a signal transmission line, and drain of final low-voltage PMOS structure is electrically connected to a high voltage ground terminal pad through second power line. The ESD protection device structure using the serially-connected low-voltage PMOS structures only, can use the circuit layout area more efficiently and provide high ESD tolerance.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 23, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Po-Chuan Lin, Shr-Hau Shiue
  • Patent number: 10691849
    Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheok-Kei Lei, Chi-Lin Liu, Hui-Zhong Zhuang, Zhe-Wei Jiang, Chi-Yu Lu, Yi-Hsin Ko
  • Patent number: 10685956
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, and first and second doped regions. The substrate has heavily doped and lightly doped regions. The lightly doped region is disposed over the heavily doped region. The first well is disposed in the lightly doped region. The first well has a conductive type complementary to a conductive type of the heavily doped and lightly doped regions. The second well is disposed in the substrate over the lightly doped region. A location of the first well overlaps a location of the second well. The first and the second doped regions are located in the second well within the active region, and spaced apart from each other. The first and the second doped regions have a same conductive type complementary to a conductive type of the second well.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsi-Yu Kuo, Yu-Lin Chu
  • Patent number: 10685611
    Abstract: A display driving apparatus applied to a panel is disclosed. The panel displays a first image with a first refresh rate. A first refresh cycle corresponding to the first refresh rate includes a refresh period and at least one non-refresh period. The display driving apparatus includes a real-time determination module and a data processing module. The real-time determination module is coupled to the panel and used to immediately determine whether the panel wants to replace the originally displayed first image with a second image during the first refresh cycle. The data processing module is coupled to the real-time determination module and the panel. If a determination result of the real-time determination module is yes, the data processing module immediately controls the panel to start to display the second image at a first time during the first refresh cycle.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 16, 2020
    Assignee: Raydium Semiconductor Corporation
    Inventors: Po-Cheng Lin, Hua-Ming Lu
  • Patent number: 10679982
    Abstract: Circuit-protection devices may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Michael Smith
  • Patent number: 10679939
    Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 10643989
    Abstract: An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping region, a fourth doping region and at least one junction formed by different conductivities. The first well and the second well respectively having a first conductivity and a second conductivity are disposed in the semiconductor substrate. The first doping region having the first conductivity is disposed in the first well. The second doping region having the second conductivity is disposed in the first well. The third doping region and the fourth doping region respectively having the first conductivity and the second conductivity are disposed in the second well. The at least one junction is formed by the first doping region and the second doping region, or formed by the third doping region and the fourth doping region.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 5, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shih-Yu Wang, Ming-Yin Lee
  • Patent number: 10643725
    Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ping Zheng, Eng Huat Toh, Elgin Kiok Boone Quek
  • Patent number: 10636872
    Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shunhua T. Chang, Ephrem G. Gebreselasie, Mujahid Muhammad, Xiangxiang Lu, Mickey H. Yu
  • Patent number: 10629586
    Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 21, 2020
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Milova Paul, Mayank Shrivastava, B. Sampath Kumar, Christian Russ, Harald Gossner
  • Patent number: 10629583
    Abstract: A transient voltage suppression device including a substrate and a first transient voltage suppressor is provided. The substrate includes a device region and a seal-ring region. The seal-ring region surrounds the device region. A first transient voltage suppressor is located in the device region. The first transient voltage suppressor includes a first well region having a first conductivity type, a first doped region having a second conductivity type, and a second doped region having the second conductivity type. The first well region is located in the substrate of the device region. The first doped region is located in the first well region. The second doped region is located in the first well region. A third doped region having the second conductivity type is located in the substrate of the seal-ring region, and the third doped region is electrically connected to the first doped region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: April 21, 2020
    Assignee: uPI Semiconductor Corp.
    Inventors: Yu-Hsuan Liu, Chih-Hao Chen
  • Patent number: 10629715
    Abstract: An electrostatic discharge protection device includes a substrate, first and second emitter regions disposed in the substrate, laterally spaced from one another on a side of the substrate, and having opposite conductivity types, and first and second base regions having opposite conductivity types and in which the first and second emitter regions are disposed in a thyristor arrangement, respectively. The first base region includes a buried doped layer that extends under the second base region. Each of the buried doped layer and the second base region includes a respective non-uniformity in dopant concentration profile. A spacing between the buried doped layer and the second base region at the respective non-uniformities establishes a breakdown trigger voltage for the thyristor arrangement.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP USA, Inc.
    Inventor: Evgueniy Nikolov Stefanov
  • Patent number: 10622348
    Abstract: A method for fabricating a protection device includes forming a doped well with a first-type impurity in a substrate. A first semiconductor terminal with a second-type impurity is formed on the doped well. A second semiconductor terminal with a second-type impurity is formed on the doped well separating from the first semiconductor terminal. The first semiconductor terminal is connected to a voltage level and a second semiconductor terminal is connected to a ground voltage.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Huei Dai, Tzung-Lin Li
  • Patent number: 10622912
    Abstract: A rectifier device includes a first transistor having a load current path and a diode connected in parallel to the load current path between an anode terminal and a cathode terminal. An alternating input voltage is operably applied between the anode terminal and the cathode terminal. A control circuit is coupled to a gate terminal of the first transistor and configured to switch the first transistor on for an on-time period, during which the diode is forward biased. A clamping circuit is coupled to the gate terminal of the first transistor and configured to at least partly switch on the first transistor while the diode is reverse biased and when the level of the alternating input voltage reaches a clamping voltage. The clamping circuit includes an additional circuit coupled between the cathode terminal and the gate terminal and configured to provide a voltage dependent on a load current.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Albino Pidutti, Damiano Gadler, Ioannis Pachnis
  • Patent number: 10598713
    Abstract: An ESD failure early warning circuit for an integrated circuit is disclosed, including a positive voltage stress generation module, a negative voltage stress generation module, a buck module, a warning output module, capacitors C006, C007, and diodes D001, D002, D003, D004 and D005. The ESD failure early warning circuit can report a warning timely when there is an ESD event in the monitored integrated circuit, to improve the reliability of the device effectively. Moreover, the stress voltage generated by the positive voltage stress generation module and the negative voltage stress generation module is adjustable, so the stress voltage can be set flexibly by a user according to actual condition of the monitored integrated circuit. The present invention has high flexibility and wide application prospect.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 24, 2020
    Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
    Inventors: Yiqiang Chen, Ang Li, Dengyun Lei, Yunfei En, Lichao Hao, Wenxiao Fang, Bo Hou
  • Patent number: 10601221
    Abstract: An electrostatic protection circuit of a display panel includes a first P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a high potential electrostatic output line, a second P-type thin film transistor having a gate connected to a high potential electrostatic output line and a drain connected to a source of the first P-type thin film transistor, and a source connected to the electrostatic signal input line; a first N-type thin film transistor having a gate connected to the low potential electrostatic output line, and a drain connected to the low potential electrostatic output line; a second N-type thin film transistor having a gate connected to the low potential electrostatic output line and a drain connected to the source of the first N-type thin film transistor, and a source connected to the electrostatic signal input line.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 24, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Pinquan Xu, Yuanfu Liu
  • Patent number: 10600650
    Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 24, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dae Sub Jung, De Yan Chen, Guang Li Yang
  • Patent number: 10600866
    Abstract: According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xiangdong Chen, Venugopal Boynapalli, Hyeokjin Lim
  • Patent number: 10586713
    Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 10, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10586772
    Abstract: A sensor device for use in harsh media, comprising a silicon die comprises a lowly doped region, and a contact layer, contacting the silicon die. The contact layer comprises a refractory metal and an ohmic contact to the silicon die via a silicide of the refractory metal. A noble metal layer is provided over the contact layer such that the contact layer is completely covered by the noble metal layer. The noble metal layer comprises palladium, platinum or a metal alloy of palladium and/or platinum. The noble metal layer is patterned to form an interconnect structure and a contact connecting via the contact layer to the ohmic contact. The noble metal layer is adapted for providing a shield to prevent modulation of the lowly doped region by surface charges. The noble metal layer may advantageously protect the contact layer against harsh media in an external environment of the sensor device.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 10, 2020
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventor: Appolonius Jacobus Van Der Wiel
  • Patent number: 10580705
    Abstract: Devices and methods related to radio-frequency (RF) switches having improved on-resistance performance. In some embodiments, a switching device can include a first terminal and a second terminal, and a plurality of switching elements connected in series to form a stack between the first terminal and the second terminal. The switching elements can have a non-uniform distribution of a parameter that results in the stack having a first ON-resistance (Ron) value that is less than a second Ron value corresponding to a similar stack having a substantially uniform distribution of the parameter.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 3, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Guillaume Alexandre Blin, Christophe Masse, Aniruddha B. Joshi
  • Patent number: 10580767
    Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: James E. Davis, John B. Pusey, Zhiping Yin, Kevin G. Duesman
  • Patent number: 10580722
    Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 3, 2020
    Assignee: TEXAS INSTRUMENTS INCOPORATED
    Inventors: Anindya Poddar, Thomas Dyer Bonifield, Woochan Kim, Vivek Kishorechand Arora
  • Patent number: 10573595
    Abstract: An array substrate, a fabricating method thereof, and a related display device are provided. The method for forming an array substrate can comprises: forming a plurality of signal lines over a base substrate; forming a conductive line over the base substrate, the conductive line connecting at least two of the plurality of signal lines; forming an insulating layer over the base substrate, the plurality of signal lines, and the conductive line; forming a via hole through the insulating layer at a position over the conductive line and between the at least two of the plurality of signal lines; and removing a portion of the conductive line through the via hole to disconnect the conductive line.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: February 25, 2020
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventor: Jingang Hao
  • Patent number: 10573638
    Abstract: An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: February 25, 2020
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventors: Po-Chuan Lin, Shr-Hau Shiue
  • Patent number: 10559560
    Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 11, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10541236
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Souvick Mitra, Mickey Yu, Alain F. Loiseau, You Li, Robert J. Gauthier, Jr., Tsung-Che Tsai
  • Patent number: 10535782
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 10535583
    Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a device region and an ESD protection structure formed on the substrate in the device region. The device region includes a center region and edge regions separated by the center region, while the ESD protection structure includes a plurality of gate structures. The ESD protection device also includes a dielectric layer formed to cover the plurality of gate structures and a plurality of heat dissipation structures formed on the dielectric layer with each heat dissipation structure aligned with a corresponding gate structure along a direction perpendicular to a surface of the substrate. The area size of each heat dissipation structure aligned with a corresponding gate structure in the center region is larger than the area size of each heat dissipation structure aligned with a corresponding gate structure in the edge region.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: January 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jun Hong Feng, Zheng Hao Gan
  • Patent number: 10529703
    Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: January 7, 2020
    Assignee: STMicroelectronics (Tours) SAS
    Inventor: Aurelie Arnaud
  • Patent number: 10529704
    Abstract: One illustrative embodiment disclosed herein relates to a semiconductor device that includes, among other things, a semiconductor substrate including a base semiconductor layer, an active semiconductor layer, and a buried insulating layer positioned between the base semiconductor layer and the active semiconductor layer. The device further includes a set of functional gate structures including at least one functional gate structure formed above the active semiconductor layer, a first source/drain region positioned in the active semiconductor layer adjacent a first functional gate structure in the set, a first auxiliary gate structure positioned adjacent the first source/drain region, and a discharge device coupled to the base semiconductor layer and the first auxiliary gate structure.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Salvatore Cimino, David Pritchard, Lixia Lei, Heng Yang, Manjunatha Prabhu
  • Patent number: 10522668
    Abstract: A semiconductor device, including a semiconductor substrate, an active region formed on the semiconductor substrate, and a gate runner disposed to surround the active region. The active region includes a first cell group in which a gate electrode of each cell is directly connected to the gate runner, and a second cell group in which a gate electrode of each cell is connected to the gate runner via a di/dt mitigating element. The di/dt mitigating element is a capacitor, a resistor connected in parallel to a capacitor, or an inverse-parallel-connected diode.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigeki Sato
  • Patent number: 10523206
    Abstract: One illustrative method disclosed herein includes forming a first transistor for an inverter and forming asymmetrically spaced first and second conductive contact structures that are conductively coupled to the source region and the drain region, respectively, of the transistor. In this example, the first conductive contact structure (for the source region) is positioned a first predetermined target distance from a first side of the gate structure of the transistor, and the second conductive contact structure (for the drain region) is positioned a second predetermined target distance from a second side of the gate structure, wherein the second predetermined target distance is less than the first predetermined target distance.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kong Boon Yeap, Yang Liu, Tian Shen, Anjum Mehta
  • Patent number: 10510746
    Abstract: A semiconductor device can include a front-end-of-line region at least a portion of which is disposed on a substrate, where the front-end-of-line region can include an electrostatic discharge protection circuit and an integrated circuit electrically connected to the electrostatic discharge protection circuit. A back-end-of-line region can be on the front-end-of-line region and an electrostatic discharge protection pattern can be on a scribe region of the substrate. The electrostatic discharge protection pattern can include a lower pattern extending horizontally and a side cross-sectional surface defined by a height and a width of the lower pattern, where the side cross-sectional surface can be exposed through a side surface of the back-end-of-line region. A via can be electrically connected to the lower pattern and extend perpendicularly to the substrate and an upper pattern can be electrically connected to the via.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Junghyun Roh
  • Patent number: 10510742
    Abstract: An IC structure includes a substrate, a deep n-well (DNW), a first device, a second device, a first electrical path and a second electrical path. The DNW is in the substrate. The first device is formed inside the DNW and connected to a first lower reference voltage and a first higher reference voltage. The second device is formed in the substrate and outside the DNW, and connected to a second lower reference voltage and a second higher reference voltage. The first electrical path is electrically connected between the first device and the second device. The second electrical path is electrically connected between the first lower reference voltage and the second lower reference voltage. A second metal layer that includes the second electrical path is located in an area outside of an area above a first metal layer in which the first electrical path is located.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Lin Chu, Hsi-Yu Kuo
  • Patent number: 10510749
    Abstract: A resistor for an integrated circuit (IC), an IC and a related method are disclosed. The resistor may include a metal alloy resistor body positioned within a single diffusion break (SDB). The SDB provides an isolation region in a semiconductor fin between a pair of fin-type field effect transistors (finFETs). The resistor in the SDB allows for the resistor to be built at front-end-of-line (FEOL) layers, which saves on space and expense, and allows for precise dimensions for the resistor.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos, Garo J. Derderian
  • Patent number: 10504886
    Abstract: An Electro-Static-Discharge (ESD) input-protection device has an NPNP structure of a N+ cathode formed in a FINFET fin or highly-doped region over a floating P-well, and a P+ fin or highly-doped region anode formed over a floating N-well that touches the floating P-well. The floating P-well is surrounded by an isolating N-well and has a deep N-well underneath to completely isolate the floating P-well from the p-type substrate. No well taps are formed in the floating wells or in the isolating N-wells. The floating P-well and the floating N-well are thus truly floating at all times. Since the wells are floating, the NPNP structure appears as three junction diodes in series, which has a lower capacitance than a single diode that the NPNP structure would appear as when one of the wells was shorted or biased. During an ESD event the NPNP structure behaves as a single diode.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: December 10, 2019
    Assignee: Hong Kong Applied Science and Technology Research Institute Company, Limited
    Inventors: Chun-Kit Yam, Chenyue Ma, Shuli Pan