With Overvoltage Protective Means Patents (Class 257/355)
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Patent number: 12100946Abstract: An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.Type: GrantFiled: July 1, 2022Date of Patent: September 24, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Ling Zhu, Kai Tian
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Patent number: 12080611Abstract: A display device is disclosed. In one aspect, the display device includes a display area configured to display an image, a peripheral area neighboring the display area, and at least one test element group (TEG) including a test thin film transistor (TFT) formed in the peripheral area and a plurality of test pads electrically connected to the test TFT. The display device also includes first to third dummy circuits separated from the test TFT, each of the first to third dummy circuits including a plurality of first dummy semiconductor layers and a plurality of first dummy gate electrodes overlapping at least a portion of the first dummy semiconductor layers in the depth dimension of the display device.Type: GrantFiled: May 17, 2021Date of Patent: September 3, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Moo Soon Ko, Jeong-Soo Lee, Jung Hwa Kim
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Patent number: 12080658Abstract: An integrated circuit (IC) device includes a first substrate, a through substrate via (TSV) in the first substrate, and a first antenna effect protection circuit over the first substrate and electrically coupled to the TSV. The first antenna effect protection circuit includes at least one first transistor of a first type, and at least one second transistor of a second type different from the first type. A gate terminal, a first terminal and a second terminal of each of the at least one first transistor and the at least one second transistor are electrically coupled together, and to the TSV.Type: GrantFiled: November 9, 2021Date of Patent: September 3, 2024Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITEDInventors: CunCun Chen, XinYong Wang, Yaqi Ma, Lei Pan, MingJian Wang, JiaLiang Zhong
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Patent number: 12002800Abstract: A semiconductor device includes first to fifth regions, first and second resistive loads. The first region is coupled to a first reference voltage terminal. The first to third regions operate as a first transistor. The fourth region is coupled to a second reference voltage terminal. The fourth to fifth regions operate as a second transistor. The first resistive load couples the second region to the second reference voltage terminal. The second resistive load couples the fifth region to the first reference voltage terminal. The first, third, second, fifth and fourth regions are arranged in order, each of the first, second and third regions corresponds to a first conductive type, and each of the fourth and fifth regions corresponds to a second conductive type.Type: GrantFiled: July 11, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Chien-Yao Huang
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Patent number: 11973075Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.Type: GrantFiled: February 22, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tao Yi Hung, Yu-Xuan Huang, Kuo-Ji Chen
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Patent number: 11901353Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.Type: GrantFiled: March 12, 2021Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Min Wu, Ming-Dou Ker, Chun-Yu Lin, Li-Wei Chu
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Patent number: 11887980Abstract: A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.Type: GrantFiled: August 4, 2022Date of Patent: January 30, 2024Assignee: Japan Display Inc.Inventor: Toshinari Sasaki
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Patent number: 11876091Abstract: An electrostatic discharge protection wiring is provided, and the electrostatic discharge protection wiring includes a gate signal line, a driving circuit, a gate connection line, and a source/drain. By disposing the bent gate connection line at an end of the gate signal line, the electrostatic discharge passes through the bent gate connection line to lose a part of current, thus reducing an effect of the electrostatic discharge to prevent bright spots at edges of panels caused by the weak electrostatic discharge.Type: GrantFiled: June 17, 2020Date of Patent: January 16, 2024Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.Inventor: Li Xu
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Patent number: 11810910Abstract: A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.Type: GrantFiled: March 3, 2022Date of Patent: November 7, 2023Assignee: SUZHOU INSTITUTE OF NANO-TECH AND NANO-BIONICS (SINANO) , CHINESE ACADEMY OF SCIENCESInventors: Xing Wei, Xiaodong Zhang, Desheng Zhao, Baoshun Zhang
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Patent number: 11798882Abstract: A semiconductor package comprises a lead frame, a low side metal-oxide-semiconductor field-effect transistor (MOSFET), an E-fuse MOSFET, a high side MOSFET, a metal connection, a gate driver, an E-fuse IC, and a molding encapsulation. A buck converter comprises a smart power stage (SPS) network and an E-fuse solution network. The SPS network comprises a high side switch, a low side switch, and a gate driver. A drain of the low side switch is coupled to a source of the high side switch via a switch node. The gate driver is coupled to a gate of the high side switch and a gate of the low side switch. The E-fuse solution network comprises a sense resistor, an E-fuse switch, an E-fuse integrated circuit (IC), and an SD circuit.Type: GrantFiled: December 28, 2020Date of Patent: October 24, 2023Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LPInventor: Prabal Upadhyaya
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Patent number: 11791331Abstract: Disclosed herein are integrated circuit (IC) structures including backside vias, as well as related methods and devices. In some embodiments, an IC structure may include: a device layer, wherein the device layer includes a plurality of active devices; a first metallization layer over the device layer, wherein the first metallization layer includes a first conductive pathway in conductive contact with at least one of the active devices in the device layer; a second metallization layer under the device layer, wherein the second metallization layer includes a second conductive pathway; and a conductive via in the device layer, wherein the conductive via is in conductive contact with at least one of the active devices in the device layer and also in conductive contact with the second conductive pathway.Type: GrantFiled: November 15, 2021Date of Patent: October 17, 2023Assignee: Intel CorporationInventors: Nicholas A. Thomson, Kalyan C. Kolluru, Adam Clay Faust, Frank Patrick O'Mahony, Ayan Kar, Rui Ma
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Patent number: 11769767Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.Type: GrantFiled: March 25, 2022Date of Patent: September 26, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Souvick Mitra, Robert J. Gauthier, Jr., Alain F. Loiseau, You Li, Tsung-Che Tsai
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Patent number: 11749684Abstract: A circuit device includes an N-type well on a P-type substrate, a P-type well provided in the N-type well, a circuit element provided in the P-type well, a P-type well provided in an N-type well, and a circuit element provided in the P-type well. A ground power supply voltage is supplied to a P-type well. A power supply voltage different from the ground power supply voltage is supplied to a P-type well. The ground power supply voltage or a first potential that is greater than or equal to the potential of the ground power supply voltage and less than the potential of a high potential-side power supply voltage is supplied to an N-type well.Type: GrantFiled: July 30, 2020Date of Patent: September 5, 2023Inventors: Kei Ishimaru, Atsushi Yamada
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Patent number: 11741630Abstract: There is provided a vehicle system including a sensing unit, a processing unit, a control unit and a display unit. The sensing unit is configured to capture an image frame containing an eyeball image from a predetermined distance. The processing unit is configured to calculate a pupil position of the eyeball image in the image frame and generate a drive signal corresponding to the pupil position. The control unit is configured to trigger a vehicle device associated with the pupil position according to the drive signal. The display unit is configured to show information of the vehicle device.Type: GrantFiled: March 4, 2022Date of Patent: August 29, 2023Assignee: PIXART IMAGING INC.Inventors: Chun-Wei Chen, Shih-Wei Kuo
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Patent number: 11722129Abstract: An automotive vehicle includes an electric machine, a traction battery, and a power converter. The power converter transfers power between the electric machine and traction battery. The power convert includes a switch that defines a portion of a phase leg, a gate driver circuit that provides provide power to a gate of the switch, and a clamping circuit. The clamping circuit includes a clamping switch that, responsive to the gate driver circuit being de-energized and a voltage of the gate exceeding a predetermined threshold value, conducts current from the gate to dissipate the voltage and clamp the gate to an emitter of the switch.Type: GrantFiled: April 1, 2022Date of Patent: August 8, 2023Assignee: FORD GLOBAL TECHNOLOGIES, LLCInventors: Yantao Song, Baoming Ge, Lihua Chen, Serdar Hakki Yonak
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Patent number: 11722065Abstract: A power converter includes a transformer including first and second windings, a switching circuit switching voltages applied to the first winding, a power supply circuit rectifying and smoothing a current in the second winding and generating a DC voltage, an adjustment circuit adjusting the DC voltage according to an operation mode including first and second modes in which the DC voltage is adjusted to first and second voltages, the second voltage less than the first voltage, and a protection circuit including first and second Zener diodes and a switch and stopping output of the adjusted voltage. A cathode of the first diode is connected to the supply circuit, and an anode of the first diode is connected to a cathode of the second diode and the switch, and the switch is connected in parallel to the second diode and is turned on in the second mode.Type: GrantFiled: July 21, 2021Date of Patent: August 8, 2023Assignee: Toshiba Tec Kabushiki KaishaInventor: Yoshiaki Hosokawa
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Patent number: 11670536Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.Type: GrantFiled: December 31, 2022Date of Patent: June 6, 2023Assignee: Monolithic 3D Inc.Inventors: Zvi Or-Bach, Brian Cronquist, Deepak Sekar
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Patent number: 11630973Abstract: A computing device accesses a machine learning model trained on training data of first bonding operations (e.g., a ball and/or stitch bond). The first bonding operations comprise operations to bond a first set of multiple wires to a first set of surfaces. The machine learning model is trained by supervised learning. The device receives input data indicating process data generated from measurements of second bonding operations. The second bonding operations comprise operations to bond a second set of multiple wires to a second set of surfaces. The device weights the input data according to the machine learning model. The device generates an anomaly predictor indicating a risk for an anomaly occurrence in the second bonding operations based on weighting the input data according to the machine learning model. The device outputs the anomaly predictor to control the second bonding operations.Type: GrantFiled: September 14, 2022Date of Patent: April 18, 2023Assignee: SAS Institute Inc.Inventors: Deovrat Vijay Kakde, Haoyu Wang, Anya Mary McGuirk
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Patent number: 11618671Abstract: A device includes a readout circuit coupled between an input node and an output node; a microelectromechanical systems (MEMS) device coupled to the input node; and a first charge controlled clamp circuit coupled between the input node and a first bias node.Type: GrantFiled: August 10, 2020Date of Patent: April 4, 2023Assignee: Infineon Technologies AGInventors: Hong Chen, Michael Reinhold, Juergen Roeber, Andreas Wiesbauer
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Patent number: 11621262Abstract: A dual-directional silicon-controlled rectifier includes: a substrate, a well region, a shallow trench isolation structure, heavily doped regions of a first conductive type, heavily doped regions of a second conductive type, and ESD implantations of the first conductive type. Four active regions are provided side by side in the well region. Forward and reverse SCRs and the ESD implantations are provided in the middle active regions. Forward and reverse diodes are provided in the active regions on both sides. One of the heavily doped regions of the first conductive type in contact with the ESD implantations is disposed between the SCRs and the diodes, so as to be electrically connected to a heavily doped region of the second conductive type of the diodes.Type: GrantFiled: March 24, 2021Date of Patent: April 4, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventors: Juin Jei Liou, Feibo Du, Ching-Sung Ho
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Patent number: 11621238Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first substrate including a center region and an edge region distal from the center region, a first circuit layer positioned on the first substrate, a center power pad positioned in the first circuit layer and above the center region, an edge power pad positioned in the first circuit layer, above the edge region, and electrically coupled to the center power pad, a redistribution power pattern positioned above the first circuit layer and electrically coupled to the center power pad, and an edge power via positioned between the edge power pad and the redistribution power pattern, and electrically connecting the edge power pad and the redistribution power pattern. The first substrate, the center power pad, the edge power pad, the redistribution power pattern, and the edge power via together configure a first semiconductor die.Type: GrantFiled: April 20, 2021Date of Patent: April 4, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Wu-Der Yang
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Patent number: 11616121Abstract: The present disclosure provides a silicon controlled rectifier and a manufacturing method thereof. The silicon controlled rectifier comprises: an N-type well 60, an upper portion of which is provided with a P-type heavily doped region 20 and an N-type heavily doped region 28; an N-type well 62, an upper portion of which is provided with a P-type heavily doped region 22 and an N-type heavily doped region 26; and a P-type well 70 connecting the N-type well 60 and 62, an upper portion of which is provided with a P-type heavily doped region 24; wherein a first electrode structure is in mirror symmetry with a second electrode structure with respect to the P-type heavily doped region 24, and active regions of the N-type well 60 and 62 are respectively provided between the P-type heavily doped region 24 and each of the N-type heavily doped region 28 and 26.Type: GrantFiled: April 26, 2021Date of Patent: March 28, 2023Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventor: Tianzhi Zhu
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Patent number: 11600730Abstract: A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.Type: GrantFiled: December 3, 2020Date of Patent: March 7, 2023Assignee: MICROSS CORPUS CHRISTI CORPORATIONInventor: David Francis Courtney
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Patent number: 11508716Abstract: An integrated circuit includes a load circuit and an electrostatic discharge (ESD) circuit. The load circuit includes a first and a second I/O terminal. The ESD circuit is coupled to the first and the second I/O terminal. The ESD circuit includes a first protection circuit configured to conduct a first ESD current from the first to the second I/O terminal. The first protection circuit includes a first, a second, a third doped region, and a well. The first doped region is coupled to the first I/O terminal, and has a first conductive type. The well is coupled to the first doped region, and has a second conductive type different from the first conductive type. The second doped region is coupled to the well, and has the first conductive type. The third doped region couples the second doped region to the second I/O terminal, and has the second conductive type.Type: GrantFiled: April 1, 2020Date of Patent: November 22, 2022Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Tay-Her Tsaur, Cheng-Cheng Yen
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Patent number: 11501116Abstract: A computing device accesses a machine learning model trained on training data of first bonding operations (e.g., a ball and/or stitch bond). The first bonding operations comprise operations to bond a first set of multiple wires to a first set of surfaces. The machine learning model is trained by supervised learning. The device receives input data indicating process data generated from measurements of second bonding operations. The second bonding operations comprise operations to bond a second set of multiple wires to a second set of surfaces. The device weights the input data according to the machine learning model. The device generates an anomaly predictor indicating a risk for an anomaly occurrence in the second bonding operations based on weighting the input data according to the machine learning model. The device outputs the anomaly predictor to control the second bonding operations.Type: GrantFiled: January 21, 2022Date of Patent: November 15, 2022Assignee: SAS Institute Inc.Inventors: Deovrat Vijay Kakde, Haoyu Wang, Anya Mary McGuirk
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Patent number: 11495955Abstract: Various implementations described herein are related to a device having switching circuitry that provides a rectified voltage when triggered. The device may include diode circuitry coupled in series with charge storage circuitry. The diode circuitry and the charge storage circuitry may operate to trigger the switching circuitry. The diode circuitry may include one or more diodes, and the charge storage circuitry may include at least one charge storage component.Type: GrantFiled: February 7, 2020Date of Patent: November 8, 2022Assignee: Arm LimitedInventors: Seshagiri Rao Bogi, Fabrice Blanc
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Patent number: 11482857Abstract: Disclosed are a surge protection device and a chip constituted thereby, and a communication terminal. The surge protection device comprises an input pad and an output pad. The input pad is connected to a power supply voltage, and the output pad is connected to a ground wire. NMOS transistor groups are provided between the input pad and the output pad. The NMOS transistor groups are connected to the input pad and the output pad respectively by means of metal wires. The structures of the metal wires between the NMOS transistor groups and the input pad and the output pad respectively and/or the structures of the NMOS transistor groups are changed to reduce or cancel non-uniform turn-on of the NMOS transistor groups caused by metal wires having different lengths from the NMOS transistor groups to the input pad and the output pad respectively along a power supply voltage wire direction.Type: GrantFiled: December 30, 2020Date of Patent: October 25, 2022Assignee: VANCHIP (TIANJIN) TECHNOLOGY CO., LTD.Inventor: Sheng Lin
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Patent number: 11462535Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit.Type: GrantFiled: May 3, 2021Date of Patent: October 4, 2022Assignee: ANALOG DEVICES, INC.Inventors: Javier A. Salcedo, Andrew Lewine
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Patent number: 11456300Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.Type: GrantFiled: March 2, 2021Date of Patent: September 27, 2022Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.Inventor: Chao-Chun Lu
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Patent number: 11444074Abstract: A semiconductor device including a protected element, an element isolation region, a contact region, and a shield region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. A periphery of the diode is surrounded by the element isolation region. The contact region is arranged at a portion on a main face of the anode region, is set with a same conductivity type as the anode region, and is set with a higher impurity concentration than the anode region. The shield region is arranged between the cathode region and the contact region so as to extend from the main face of the anode region as far as a region deeper than a depth of the contact region and shallower than the anode region. The shield region is configured including a semiconductor region with an opposite conductivity type to the anode region.Type: GrantFiled: July 8, 2019Date of Patent: September 13, 2022Assignee: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHOInventor: Yoshikazu Kataoka
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Patent number: 11444455Abstract: In certain aspects of the disclosure, a protection circuit includes a first input/output (I/O) pin, a second I/O pad, a shunt clamp coupled to the first I/O pad, and a resistor coupled between the shunt clamp and the second I/O pad. The resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, and the second dynamic resistance is at least five times greater than the first dynamic resistance.Type: GrantFiled: February 3, 2020Date of Patent: September 13, 2022Inventor: Eugene Robert Worley
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Patent number: 11424339Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.Type: GrantFiled: October 27, 2020Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Meng-Han Lin, Chia-En Huang
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Patent number: 11381078Abstract: An electronic circuit is disclosed. The circuit includes a power transistor having a gate terminal, a source terminal and a drain terminal. The electronic circuit also has a driver to generate which selectively changes a voltage at the gate terminal. The driver circuit includes a pull-down switch configured to change the voltage on the gate terminal such that the resistance between the source terminal and the drain terminal increases. The electronic circuit also has an overvoltage protection circuit coupled to the gate terminal. The overvoltage protection circuit includes a selectively conductive device configured to become conductive while reverse biased in response to an overvoltage potential. While conductive, the selectively conductive device causes the resistance between the source terminal and the drain terminal to decrease. The overvoltage protection circuit is also causes the pull-down switch to be non-conductive by applying a signal to the pull-down switch.Type: GrantFiled: June 18, 2019Date of Patent: July 5, 2022Assignee: Navitas Semiconductor LimitedInventor: Daniel M. Kinzer
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Patent number: 11374002Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.Type: GrantFiled: July 24, 2020Date of Patent: June 28, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Wenjun Li, Man Gu
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Patent number: 11346879Abstract: An increased accuracy in detecting deterioration of a semiconductor device can be achieved. A first metal pattern and a second metal pattern are connected to a controller. A bonding wire connects the first metal pattern and an emitter electrode. A linear conductor is connected between a first electrode pad and a second electrode pad. First bonding wires connect the first electrode pad and the second metal pattern. Second bonding wires connect the second electrode pad and the second metal pattern. The controller detects the deterioration of the semiconductor device when a potential difference between the first metal pattern and the second metal pattern is above a threshold.Type: GrantFiled: January 4, 2018Date of Patent: May 31, 2022Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Chihiro Kawahara, Takeshi Horiguchi, Yoshiko Tamada, Yasushi Nakayama
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Patent number: 11335675Abstract: Circuit-protection devices might include first and second circuit-protection units each comprising a first node and a second node, a first field-effect transistor having a first source/drain connected to the first node of the first circuit-protection unit, and a second field-effect transistor having a first source/drain connected to the first node of the second circuit-protection unit, wherein a second source/drain of the first field-effect transistor merges with a second source/drain of the second field-effect transistor.Type: GrantFiled: December 21, 2020Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventor: Michael Smith
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Patent number: 11335674Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.Type: GrantFiled: June 27, 2019Date of Patent: May 17, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Souvick Mitra, Robert J. Gauthier, Jr., Alain F. Loiseau, You Li, Tsung-Che Tsai
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Patent number: 11328946Abstract: A manufacturing method of the ESD protection device includes the following steps. A surface treatment is performed on the substrate. A link layer is formed on the substrate after the surface treatment, wherein a material of the link layer includes a metal material. A progressive layer is formed on the link layer, wherein a material of the progressive layer includes a non-stoichiometric metal oxide material, and an oxygen concentration in the non-stoichiometric metal oxide material is increased gradually away from the substrate in a thickness direction of the progressive layer. A composite layer is formed on the progressive layer, wherein the composite layer includes a stoichiometric metal oxide material and a non-stoichiometric metal oxide material, and a ratio of the non-stoichiometric metal oxide material and the stoichiometric metal oxide material in the composite layer may make a sheet resistance value of the composite layer 1×107 to 1×108 ?/sq.Type: GrantFiled: May 24, 2021Date of Patent: May 10, 2022Assignee: Industrial Technology Research InstituteInventors: Ding-Shiang Wang, Jia-Jen Chang, Ming-Sheng Leu, Tai-Sheng Chen, Chin-Te Shih
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Patent number: 11309881Abstract: An automotive vehicle includes an electric machine, a traction battery, and a power converter. The power converter transfers power between the electric machine and traction battery. The power convert includes a switch that defines a portion of a phase leg, a gate driver circuit that provides provide power to a gate of the switch, and a clamping circuit. The clamping circuit includes a clamping switch that, responsive to the gate driver circuit being de-energized and a voltage of the gate exceeding a predetermined threshold value, conducts current from the gate to dissipate the voltage and clamp the gate to an emitter of the switch.Type: GrantFiled: January 24, 2020Date of Patent: April 19, 2022Assignee: Ford Global Technologies, LLCInventors: Yantao Song, Baoming Ge, Lihua Chen, Serdar Hakki Yonak
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Patent number: 11302686Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.Type: GrantFiled: November 18, 2019Date of Patent: April 12, 2022Assignee: Nuvoton Technology CorporationInventors: Yi-Hao Chen, Tsu-Yi Wu, Chih-Hsun Lu, Po-An Chen, Chun-Chieh Liu
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Patent number: 11302689Abstract: An Electro-Static-Discharge (ESD) protection circuit has a Silicon-Controlled Rectifier (SCR) with a discharge current path in a first direction. A triggering transistor has a trigger current flowing in a second direction that is perpendicular to the first direction. Triggering transistors can be Fin Field-Effect Transistor (FinFET) transistors with current flowing along the long direction of the fins. The trigger current flows into a connecting N+ drain and into an N-Well under a center portion of the connecting N+ drain to inject carriers into the N-base of a PNPN SCR. The injected current flows through the base to generate a voltage gradient that turns on the PN junction in a P+ emitter that is parallel to but spaced apart from the FinFET transistors, causing a discharge current to flow perpendicular to the fins. The perpendicular discharge current flows through the substrate which can handle a larger current than the small fins.Type: GrantFiled: January 13, 2021Date of Patent: April 12, 2022Assignee: Hong Kong Applied Science and Technology Research Institute Company LimitedInventor: Chun-Kit Yam
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Patent number: 11303188Abstract: An electromagnetic interference (EMI) circuit assembly includes a first, second, and third conductive layer. A protection component disposed between the first and second conductive layers. A dielectric layer is disposed between the second and the third conductive layers. The protection component is configured to protect a load from one or both of an overcurrent condition and an over temperature condition, and the third layer define a capacitor configured to suppress EMI signals.Type: GrantFiled: August 20, 2019Date of Patent: April 12, 2022Assignees: LITTELFUSE ELECTRONICS (SHANGHAI) CO., LTD., LITTELFUSE FRANCE SASInventors: Werner Johler, Philippe Di Fulvio
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Patent number: 11302687Abstract: A semiconductor device includes a substrate; a collector including a buried layer within the substrate, a first well region over a first portion of the buried layer, and a first conductivity region at least partially within the first well region; a base including a second well region over a second portion of the buried layer and laterally adjacent to the first well region, and a second conductivity region at least partially within the second well region; an emitter including a third conductivity region at least partially within the second conductivity region; an isolation element between the first and the third conductivity regions; a conductive plate on the isolation element and electrically connected with the first conductivity region. The buried layer, the first well region, the first and the third conductivity regions have a first conductivity type; the second well region and the second conductivity region have a second conductivity type.Type: GrantFiled: October 30, 2019Date of Patent: April 12, 2022Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Jie Zeng, Raunak Kumar
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Patent number: 11290018Abstract: A power converter includes an insulating transformer including primary and secondary windings, a switching circuit configured to switch voltages applied to the primary winding, a power supply circuit connected to the secondary winding and configured to rectify and smooth a current flowing in the secondary winding and generate a DC voltage, an adjustment circuit configured to adjust the voltage and output the adjusted voltage that is a first voltage in a first mode and a second voltage that is less than the first voltage in a second mode, and a protection circuit including a first Zener diode and a second Zener diode and configured to stop output of the adjusted voltage. A cathode of the first diode is electrically connected to the power supply circuit. The second diode is connected in series to the first diode in the first mode and being short-circuited in the second mode.Type: GrantFiled: March 24, 2020Date of Patent: March 29, 2022Assignee: TOSHIBA TEC KABUSHIKI KAISHAInventor: Yoshiaki Hosokawa
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Patent number: 11265607Abstract: Embodiments of the invention relate generally to the field of content distribution platforms, and more particularly, to systems, methods, and apparatuses for implementing a broadcast integration platform with real-time interactive content synchronization.Type: GrantFiled: October 1, 2020Date of Patent: March 1, 2022Assignee: Synchronicity Finance LLCInventors: John Robert Armstrong, Reese Armstrong, Rondee Quinton Businger
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Patent number: 11257811Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.Type: GrantFiled: July 2, 2020Date of Patent: February 22, 2022Assignee: Cambridge Enterprise LimitedInventors: Martin Arnold, Loizos Efthymiou, David Bruce Vail, John William Findlay, Giorgia Longobardi, Florin Udrea
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Patent number: 11222893Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.Type: GrantFiled: July 29, 2019Date of Patent: January 11, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
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Patent number: 11217690Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.Type: GrantFiled: September 16, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies Austria AGInventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
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Patent number: 11201146Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.Type: GrantFiled: October 23, 2019Date of Patent: December 14, 2021Assignee: Vanguard International Semiconductor CorporationInventors: Jian-Hsing Lee, Yeh-Jen Huang, Wen-Hsin Lin, Chun-Jung Chiu
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Patent number: 11195920Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.Type: GrantFiled: October 10, 2019Date of Patent: December 7, 2021Assignee: Newport Fab, LLCInventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli