With Overvoltage Protective Means Patents (Class 257/355)
  • Patent number: 11456300
    Abstract: An unified IC system includes a base memory chip, a plurality of stacked memory chips, and a logic chip. The base memory chip includes a memory region and a bridge area, the memory region includes a plurality of memory cells, and the bridge area includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The plurality of stacked memory chips is positioned above the base memory chip. The logic chip includes a logic bridge area and a plurality of second transistors, the logic bridge includes a plurality of logic I/O pads, wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: September 27, 2022
    Assignees: Etron Technology, Inc., Invention And Collaboration Laboratory Pte. Ltd.
    Inventor: Chao-Chun Lu
  • Patent number: 11444074
    Abstract: A semiconductor device including a protected element, an element isolation region, a contact region, and a shield region. The protected element is configured including a p-n junction diode between an anode region and a cathode region, and is arranged in an active layer of a substrate. A periphery of the diode is surrounded by the element isolation region. The contact region is arranged at a portion on a main face of the anode region, is set with a same conductivity type as the anode region, and is set with a higher impurity concentration than the anode region. The shield region is arranged between the cathode region and the contact region so as to extend from the main face of the anode region as far as a region deeper than a depth of the contact region and shallower than the anode region. The shield region is configured including a semiconductor region with an opposite conductivity type to the anode region.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: September 13, 2022
    Assignee: KABUSHIKI KAISHA TOKAI-RIKA-DENKI-SEISAKUSHO
    Inventor: Yoshikazu Kataoka
  • Patent number: 11444455
    Abstract: In certain aspects of the disclosure, a protection circuit includes a first input/output (I/O) pin, a second I/O pad, a shunt clamp coupled to the first I/O pad, and a resistor coupled between the shunt clamp and the second I/O pad. The resistor has a first dynamic resistance at a voltage of 100 millivolts across the resistor, the resistor has a second dynamic resistance at a voltage of three volts across the resistor, and the second dynamic resistance is at least five times greater than the first dynamic resistance.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 13, 2022
    Inventor: Eugene Robert Worley
  • Patent number: 11424339
    Abstract: An integrated chip includes a substrate, an isolation structure and a poly gate structure. The isolation structure includes dielectric materials within the substrate and having sidewalls defining an active region. The active region has a channel region, a source region, and a drain region separated from the source region by the channel region along a first direction. The source region has a first width along a second direction perpendicular to the first direction, the drain region has a second width along the second direction, and the channel region has a third width along the second direction and larger than the first and second widths. The poly gate structure extends over the channel region. The poly gate structure includes a first doped region having a first type of dopants and a second doped region having a second type of dopants. The second type is different from the first type.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chia-En Huang
  • Patent number: 11381078
    Abstract: An electronic circuit is disclosed. The circuit includes a power transistor having a gate terminal, a source terminal and a drain terminal. The electronic circuit also has a driver to generate which selectively changes a voltage at the gate terminal. The driver circuit includes a pull-down switch configured to change the voltage on the gate terminal such that the resistance between the source terminal and the drain terminal increases. The electronic circuit also has an overvoltage protection circuit coupled to the gate terminal. The overvoltage protection circuit includes a selectively conductive device configured to become conductive while reverse biased in response to an overvoltage potential. While conductive, the selectively conductive device causes the resistance between the source terminal and the drain terminal to decrease. The overvoltage protection circuit is also causes the pull-down switch to be non-conductive by applying a signal to the pull-down switch.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 5, 2022
    Assignee: Navitas Semiconductor Limited
    Inventor: Daniel M. Kinzer
  • Patent number: 11374002
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A semiconductor substrate includes a first region, a second region, and a first source/drain region in the first region. A semiconductor fin is located over the second region of the semiconductor substrate. The semiconductor fin extends laterally along a longitudinal axis to connect to the first region of the semiconductor substrate. The structure includes a second source/drain region including an epitaxial semiconductor layer coupled to the first semiconductor fin, and a gate structure that extends over the semiconductor fin. The gate structure includes a first sidewall and a second sidewall opposite the first sidewall, the first source/drain region is positioned adjacent to the first sidewall of the gate structure, and the second source/drain region is positioned adjacent to the second sidewall of the gate structure.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: June 28, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Wenjun Li, Man Gu
  • Patent number: 11346879
    Abstract: An increased accuracy in detecting deterioration of a semiconductor device can be achieved. A first metal pattern and a second metal pattern are connected to a controller. A bonding wire connects the first metal pattern and an emitter electrode. A linear conductor is connected between a first electrode pad and a second electrode pad. First bonding wires connect the first electrode pad and the second metal pattern. Second bonding wires connect the second electrode pad and the second metal pattern. The controller detects the deterioration of the semiconductor device when a potential difference between the first metal pattern and the second metal pattern is above a threshold.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: May 31, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Chihiro Kawahara, Takeshi Horiguchi, Yoshiko Tamada, Yasushi Nakayama
  • Patent number: 11335674
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 17, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Souvick Mitra, Robert J. Gauthier, Jr., Alain F. Loiseau, You Li, Tsung-Che Tsai
  • Patent number: 11335675
    Abstract: Circuit-protection devices might include first and second circuit-protection units each comprising a first node and a second node, a first field-effect transistor having a first source/drain connected to the first node of the first circuit-protection unit, and a second field-effect transistor having a first source/drain connected to the first node of the second circuit-protection unit, wherein a second source/drain of the first field-effect transistor merges with a second source/drain of the second field-effect transistor.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Michael Smith
  • Patent number: 11328946
    Abstract: A manufacturing method of the ESD protection device includes the following steps. A surface treatment is performed on the substrate. A link layer is formed on the substrate after the surface treatment, wherein a material of the link layer includes a metal material. A progressive layer is formed on the link layer, wherein a material of the progressive layer includes a non-stoichiometric metal oxide material, and an oxygen concentration in the non-stoichiometric metal oxide material is increased gradually away from the substrate in a thickness direction of the progressive layer. A composite layer is formed on the progressive layer, wherein the composite layer includes a stoichiometric metal oxide material and a non-stoichiometric metal oxide material, and a ratio of the non-stoichiometric metal oxide material and the stoichiometric metal oxide material in the composite layer may make a sheet resistance value of the composite layer 1×107 to 1×108 ?/sq.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 10, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Ding-Shiang Wang, Jia-Jen Chang, Ming-Sheng Leu, Tai-Sheng Chen, Chin-Te Shih
  • Patent number: 11309881
    Abstract: An automotive vehicle includes an electric machine, a traction battery, and a power converter. The power converter transfers power between the electric machine and traction battery. The power convert includes a switch that defines a portion of a phase leg, a gate driver circuit that provides provide power to a gate of the switch, and a clamping circuit. The clamping circuit includes a clamping switch that, responsive to the gate driver circuit being de-energized and a voltage of the gate exceeding a predetermined threshold value, conducts current from the gate to dissipate the voltage and clamp the gate to an emitter of the switch.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 19, 2022
    Assignee: Ford Global Technologies, LLC
    Inventors: Yantao Song, Baoming Ge, Lihua Chen, Serdar Hakki Yonak
  • Patent number: 11302689
    Abstract: An Electro-Static-Discharge (ESD) protection circuit has a Silicon-Controlled Rectifier (SCR) with a discharge current path in a first direction. A triggering transistor has a trigger current flowing in a second direction that is perpendicular to the first direction. Triggering transistors can be Fin Field-Effect Transistor (FinFET) transistors with current flowing along the long direction of the fins. The trigger current flows into a connecting N+ drain and into an N-Well under a center portion of the connecting N+ drain to inject carriers into the N-base of a PNPN SCR. The injected current flows through the base to generate a voltage gradient that turns on the PN junction in a P+ emitter that is parallel to but spaced apart from the FinFET transistors, causing a discharge current to flow perpendicular to the fins. The perpendicular discharge current flows through the substrate which can handle a larger current than the small fins.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: April 12, 2022
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventor: Chun-Kit Yam
  • Patent number: 11302687
    Abstract: A semiconductor device includes a substrate; a collector including a buried layer within the substrate, a first well region over a first portion of the buried layer, and a first conductivity region at least partially within the first well region; a base including a second well region over a second portion of the buried layer and laterally adjacent to the first well region, and a second conductivity region at least partially within the second well region; an emitter including a third conductivity region at least partially within the second conductivity region; an isolation element between the first and the third conductivity regions; a conductive plate on the isolation element and electrically connected with the first conductivity region. The buried layer, the first well region, the first and the third conductivity regions have a first conductivity type; the second well region and the second conductivity region have a second conductivity type.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 12, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jie Zeng, Raunak Kumar
  • Patent number: 11302686
    Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: April 12, 2022
    Assignee: Nuvoton Technology Corporation
    Inventors: Yi-Hao Chen, Tsu-Yi Wu, Chih-Hsun Lu, Po-An Chen, Chun-Chieh Liu
  • Patent number: 11303188
    Abstract: An electromagnetic interference (EMI) circuit assembly includes a first, second, and third conductive layer. A protection component disposed between the first and second conductive layers. A dielectric layer is disposed between the second and the third conductive layers. The protection component is configured to protect a load from one or both of an overcurrent condition and an over temperature condition, and the third layer define a capacitor configured to suppress EMI signals.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 12, 2022
    Assignees: LITTELFUSE ELECTRONICS (SHANGHAI) CO., LTD., LITTELFUSE FRANCE SAS
    Inventors: Werner Johler, Philippe Di Fulvio
  • Patent number: 11290018
    Abstract: A power converter includes an insulating transformer including primary and secondary windings, a switching circuit configured to switch voltages applied to the primary winding, a power supply circuit connected to the secondary winding and configured to rectify and smooth a current flowing in the secondary winding and generate a DC voltage, an adjustment circuit configured to adjust the voltage and output the adjusted voltage that is a first voltage in a first mode and a second voltage that is less than the first voltage in a second mode, and a protection circuit including a first Zener diode and a second Zener diode and configured to stop output of the adjusted voltage. A cathode of the first diode is electrically connected to the power supply circuit. The second diode is connected in series to the first diode in the first mode and being short-circuited in the second mode.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 29, 2022
    Assignee: TOSHIBA TEC KABUSHIKI KAISHA
    Inventor: Yoshiaki Hosokawa
  • Patent number: 11265607
    Abstract: Embodiments of the invention relate generally to the field of content distribution platforms, and more particularly, to systems, methods, and apparatuses for implementing a broadcast integration platform with real-time interactive content synchronization.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: March 1, 2022
    Assignee: Synchronicity Finance LLC
    Inventors: John Robert Armstrong, Reese Armstrong, Rondee Quinton Businger
  • Patent number: 11257811
    Abstract: The disclosure relates to a III-nitride power semiconductor based heterojunction device including a low voltage terminal, a high voltage terminal, a control terminal and an active heterojunction transistor formed on a substrate, and further including the following monolithically integrated components: voltage clamp circuit configured to limit a maximum potential that can be applied to the internal gate terminal, an on-state circuit configured to control the internal gate terminal of the active heterojunction transistor during an on-state operation, a turn-off circuit configured to control the internal gate terminal of the active heterojunction transistor during a turn-off operation and during an off-state.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: February 22, 2022
    Assignee: Cambridge Enterprise Limited
    Inventors: Martin Arnold, Loizos Efthymiou, David Bruce Vail, John William Findlay, Giorgia Longobardi, Florin Udrea
  • Patent number: 11222893
    Abstract: A method includes the following operations: disconnecting at least one of drain regions that are formed on a first active area, of first transistors, from a first voltage; and disconnecting at least one of drain regions that are formed on a second active area, of second transistors coupled to the first transistors from a second voltage. The at least one of drain regions of the second transistors corresponds to the at least one of drain regions of the first transistors.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Feng Chang, Po-Lin Peng, Jam-Wem Lee
  • Patent number: 11217690
    Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: January 4, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
  • Patent number: 11201146
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first well region that has first conductive type therein. The semiconductor device structure also includes a first doped region embedded in the first well region, and having a second conductive type that is different from the first conductive type. The semiconductor device structure further includes a second well region that has the second conductive type. In addition, the semiconductor device structure includes a first metal electrode disposed on the first doped region of the semiconductor substrate and a second metal electrode disposed on the second well region of the semiconductor substrate.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jian-Hsing Lee, Yeh-Jen Huang, Wen-Hsin Lin, Chun-Jung Chiu
  • Patent number: 11195947
    Abstract: A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: December 7, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Jagar Singh, Luigi Pantisano, Anvitha Shampur, Frank Scott Johnson, Srikanth Balaji Samavedam
  • Patent number: 11195827
    Abstract: A semiconductor integrated circuit device may include a pad, a first voltage protection circuit and a second voltage protection circuit. The first voltage protection circuit may be connected with the pad. The second voltage protecting circuit may be connected between the first voltage protection circuit and a ground terminal. The first voltage protection circuit may include a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor. The second voltage protection circuit may include serially connected GPPMOS transistors.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Hwi Lee, Jin Woo Kim, Hyun Duck Lee, Seung Yeop Lee, Ju Hyeong Lee
  • Patent number: 11195920
    Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: December 7, 2021
    Assignee: Newport Fab, LLC
    Inventors: Paul D. Hurwitz, Edward Preisler, David J. Howard, Marco Racanelli
  • Patent number: 11183837
    Abstract: Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: James Davis, Michael Chaine
  • Patent number: 11164971
    Abstract: A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: November 2, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Thomas Jacke, Wolfgang Feiler
  • Patent number: 11133391
    Abstract: A transistor device includes, in a semiconductor body, a drift region, a body region, and a source region separated from the drift region by the body region and connected to a source node. The transistor device further includes a gate electrode dielectrically insulated from the body region by a gate dielectric, and a field electrode structure. The field electrode structure includes: a first field electrode connected to the source node and dielectrically insulated from the drift region by a first field electrode dielectric; a second field electrode dielectrically insulated from the drift region by a second field electrode dielectric; and a coupling circuit connected between the second field electrode and the source node and configured to connect the second field electrode to the source node dependent on a voltage between the source node and the second field electrode.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Cesar Augusto Braz, Gerhard Noebauer, Martin Henning Vielemeyer
  • Patent number: 11127734
    Abstract: An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 11114429
    Abstract: Disclosed herein are integrated circuit devices and methods for fabricating the same that include at least one non-I/O die having ESD protection circuitry. The ESD protection circuitry disclosed herein may also be utilized in I/O dies. In one example, an integrated circuit device includes a die having a first body. First and second contact pads are exposed to a surface of the first body. The first contact pad is configured to connect to a first supply voltage. The second contact pad is configured to connect to a second supply voltage or ground. A first charge-sensitive circuitry formed in the first body is coupled between the first and second contact pads. A first RC clamp formed in the first body is coupled between the first and second contact pads. The first RC clamp includes at least two BigFETs coupled between the first and second contact pads, and a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventor: James Karp
  • Patent number: 11107737
    Abstract: A method for fabricating a semiconductor device includes at least the following steps. First, a substrate having a first conductivity type is provided and the substrate is doped with a second conductivity type dopant to form a first well region and a second well region in the substrate, wherein the first conductivity type is opposite to the second conductivity type. An inverter is formed in the first well region. A control transistor and a reference transistor are formed in the second well region, wherein the inverter is electrically connected to the control transistor. An electrical connection path is formed between the inverter and a gate of the control transistor. A difference between electrical parameters of the control transistor and the reference transistor in the control wafer is measured to obtain a measuring result. The semiconductor device having a layout design is fabricated based on the measuring result.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Liao, Chu-Fu Chen, Jui-Yean Chiu
  • Patent number: 11088133
    Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: August 10, 2021
    Assignee: SK hynix Inc.
    Inventors: Joung Cheul Choi, Chang Seok Song
  • Patent number: 11088132
    Abstract: A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 10, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Guangyang Wang
  • Patent number: 11088135
    Abstract: An electrostatic discharge (ESD) protection apparatus and an integrated passive device (IPD) with capacitor(s) are provided. The ESD protection apparatus includes a transistor, an impedance, and a capacitor disposed in a redistribution layer (RDL) structure of a package. The first terminal and the second terminal of the transistor are respectively coupled to a first power rail and a second power rail of the RDL structure. A first terminal of the impedance is coupled to the first power rail. A second terminal of the impedance is coupled to a control terminal of the transistor. A first terminal of the capacitor is coupled to the second terminal of the impedance. A second terminal of the capacitor is coupled to the second power rail.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 10, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Hua Chung, Tai-Jui Wang, Chieh-Wei Feng
  • Patent number: 11081881
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit including a trigger actuated MOSFET device. Triggering of the MOSFET device is made in response to detection of either a positive ESD event or a negative ESD event.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 3, 2021
    Assignee: STMicroelectronics International N.V.
    Inventors: Divya Agarwal, Radhakrishnan Sithanandam
  • Patent number: 11069675
    Abstract: An ESD protection device for bidirectional diode string triggering SCR structure belongs to the field of electro-static discharge of an integrated circuit. A deep N well is arranged on a P substrate, and a first P well, a first N well, a second P well and a second N well are successively arranged from left to right on a surface region of the deep N well. In a second N well region, a mask preparing plate is used to insert the P wells at intervals. The circumference of each P well is isolated by the N well. Each P well is respectively provided with a pair of P+ implantation region and N+ implantation region. The metal wire is connected with the implantation region, and a positive electrode and a negative electrode are led out from the metal wire for forward conduction and reverse conduction.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 20, 2021
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Hailian Liang, Qiang Xu, Xiaofeng Gu
  • Patent number: 11063429
    Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: July 13, 2021
    Assignees: STMicroelectronics International N.V., STMicroelectronics SA
    Inventors: Radhakrishnan Sithanandam, Divya Agarwal, Ghislain Troussier, Jean Jimenez, Malathi Kar
  • Patent number: 11043554
    Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a plurality of ring-shaped regions, and a semi-insulating layer. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region surrounds the second semiconductor region, and is provided on the first semiconductor region. The ring-shaped regions surround the second semiconductor region. The second electrode is provided on the second semiconductor region. The third electrode is provided on the third semiconductor region. The semi-insulating layer contacts the first semiconductor region, the second electrode, the ring-shaped regions, and the third electrode. The ring-shaped regions include first and second ring-shaped regions provided between the first ring-shaped region and the third semiconductor region.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 22, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Daiki Yoshikawa
  • Patent number: 11044798
    Abstract: An ESD protection composite structure includes a link layer, a progressive layer, and a composite layer. The link layer is used for disposing the ESD protection composite structure on a substrate, wherein a material of the link layer includes a metal material. The progressive layer is disposed on the link layer, wherein the material of the progressive layer includes a non-stoichiometric metal oxide material, and an oxygen concentration in the non-stoichiometric metal oxide material is increased gradually away from the substrate in a thickness direction of the progressive layer. The composite layer is disposed on the progressive layer, wherein the composite layer includes a stoichiometric metal oxide material and a non-stoichiometric metal oxide material, and a ratio of the non-stoichiometric metal oxide material and the stoichiometric metal oxide material in the composite layer may make a sheet resistance value of the composite layer 1×107 ?/sq to 1×108 ?/sq.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: June 22, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Ding-Shiang Wang, Jia-Jen Chang, Ming-Sheng Leu, Tai-Sheng Chen, Chin-Te Shih
  • Patent number: 11043520
    Abstract: Provided is a light-receiving device including: a photoelectric conversion layer including a Group III-V semiconductor; a plurality of first electrically-conductive type regions in signal charges generated in the photoelectric conversion layer move; and a second electrically-conductive type region penetrating through the photoelectric conversion layer and provided between adjacent ones of the first electrically-conductive type regions.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: June 22, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Yoshigiwa
  • Patent number: 11037886
    Abstract: A semiconductor structure of a work unit module includes an encircling noise-resistance structure and a P-type substrate being defined with a chip region and a surrounding region surrounding the chip region. The surrounding area includes two first strip regions and two second strip regions. Each of the first strip regions is located between the second strip regions, and each of the second strip regions is located between the first strip regions. The encircling noise-resistance structure is located on the surrounding area, and includes first arrangement units and second arrangement units. The first arrangement unit is arranged in one of the first strip regions in a single row. The second arrangement unit is arranged in one of the second strip regions in a single row, and the long axis direction of the second arrangement unit is different from the long axis direction of the first arrangement unit.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 15, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ya Tseng, Wei-Cheng Yu, Bo-Yan Li, Wen-Tai Wang
  • Patent number: 11024625
    Abstract: A protection cell for a cell library. The protection cell defines a protection circuit for an IC having a driving device with a first supply voltage Vdd1 and an output, and a driven device having an input and a second supply voltage Vdd2. The protection circuit includes a first device from the group consisting of a P-diode and a gate-Vdd PMOS. The first device is coupled between a first power bus connected to Vdd2 and the input of the driven device. The input of the driven device is coupled by way of a resistor to the output of the driving device. A second device corresponding to the first device is provided, from the group consisting of an N-diode and a grounded gate NMOS. The second device is coupled between the input of the driven device and a ground bus.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Bo-Ting Chen
  • Patent number: 11018128
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate of a first conducting type. A pad is provided on the semiconductor substrate. An internal circuit is provided on the semiconductor substrate. An electrostatic discharge protection element is provided between the pad and the internal circuit. The electrostatic discharge protection element comprises a first well of a second conducting type, a second well of a first conducting type, and a first electrode layer of a second conducting type. The first well of a second conducting type is provided in a surface region of the semiconductor substrate. The second well of a first conducting type is provided inside the first well in the surface region of the semiconductor substrate. The first electrode layer of a second conducting type is provided inside the second well in the surface region of the semiconductor substrate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 25, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyuki Kutsukake
  • Patent number: 11011509
    Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 18, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Jie Zeng, Raunak Kumar, Kyong Jin Hwang
  • Patent number: 11004812
    Abstract: A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tuan-Yu Hung, Hung-Jui Kuo, Hsin-Yu Pan, Ming-che Ho, Tzu Yun Huang, Yen-Fu Su
  • Patent number: 11004849
    Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 11, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Javier A. Salcedo, Andrew Lewine
  • Patent number: 10985157
    Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: April 20, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventors: Chien-Shao Tang, Ting-Jui Lin, Hsiang-Ming Chou, Fang-Yu Chang
  • Patent number: 10978445
    Abstract: The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fang Lai, Liang-Yu Su, Hang Fan
  • Patent number: 10957773
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a first ring-shaped region, a second ring-shaped region, a second electrode, a third electrode, a first conductive layer, and a semi-insulating layer. The first ring-shaped region surrounds the second semiconductor region, and is provided between the second and third semiconductor regions. The second ring-shaped region surrounds the first ring-shaped region, and is provided between the first ring-shaped region and the third semiconductor region. The first conductive layer surrounds the second electrode, and is provided on the first ring-shaped region, the second ring-shaped region, and a first region of the first semiconductor region with an insulating layer interposed. The first region is positioned between the first and second ring-shaped regions.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 23, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenichi Matsushita
  • Patent number: 10937781
    Abstract: An electronic device can include a source terminal, a gate terminal, and a protection circuit. The protection circuit can include a gate section including a first electrode and a second electrode, wherein the first electrode of the gate section is coupled to the gate terminal; and a source section including a first electrode and a second electrode, wherein the first electrode of the source section is coupled to the source terminal. The protection switch can include a control electrode, a first current-carrying electrode coupled to the gate terminal, and a second current-carrying electrode coupled to the source terminal. The second electrode of the gate section, the second electrode of the source section, and the control electrode of the protection switch can be coupled to one another. In an embodiment, the electronic device can further include an electronic component that is protected by the protection circuit.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 2, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Herbert De Vleeschouwer, Pierre Gassot, Piet Vanmeerbeek, Frederick Johan G Declercq, Aarnout Wieers, Woochul Jeon
  • Patent number: 10930637
    Abstract: A transient voltage suppressor is provided, comprising a heavily doped substrate connected to a first node, a first doped layer formed on the heavily doped substrate, a second doped layer formed on the first doped layer, a first heavily doped region and a second heavily doped region formed in the second doped layer and coupled to a second node, and a plurality of trenches arranged in the heavily doped substrate, having a depth not less than that of the first doped layer for electrical isolation. The heavily doped substrate, the second doped layer, and the second heavily doped region belong to a first conductivity type. The first doped layer and the first heavily doped region belong to a second conductivity type. By employing the proposed present invention, pn junctions of the transient voltage suppressor can be controlled beneath the surface, thereby reducing the junction capacitance effectively.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 23, 2021
    Assignee: Amazing Microelectronic Corp.
    Inventors: Yu-Shu Shen, Mei-Lian Fan