Integrated Fin-Local Interconnect Structure
Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.
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This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 11/770,783, filed Jun. 29, 2007, which is herein incorporated by reference.
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention generally relates to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices.
2. Description of the Related Art
Over the past few decades, the speed and density of transistors in integrated circuits has continued to increase in accordance with Moore's law, which predicts exponential growth. Consequently, integrated circuits such as microprocessors have delivered greater functionality and performance at a lower cost. As devices on integrated circuits, for example, transistors have become smaller, faster, and cheaper, the use of integrated circuits has become more widespread. Furthermore, the demand for better, faster, cheaper, and improved integrated circuits continues to grow. As a result, innovative technologies for constructing faster and smaller transistors continue to be developed and adopted.
Fin Field Effect Transistor (FinFET) technology is one such innovative approach used to construct high performance, densely packed transistors on integrated circuits. A FinFET is a double gate structure that is easily manufactured using current fabrication techniques. In a FinFET, a vertical fin is defined to form the body of a transistor. Gates can be formed on one or both sides of the vertical fin. When both sides of the vertical fin have a gate formed thereon, the transistor is generally referred to as a double-gate FinFET. A double-gate FinFET helps suppress short channel effects (SCE), reduce leakage, and enhance switching behavior. Also, a double gate FinFET can increase the electrical width of the transistor, which can in turn increase on-current without increasing the length of the gate conductor.
A gate structure 160 is formed over each of the fin structures 130 and 150 as shown in
As illustrated in
Furthermore, each contact is typically coupled with a metal layer to connect a semiconductor device to other devices. For example, contacts 111 and 112 may be coupled with a metal layer 171, contacts 141 and 142 may be coupled with a metal layer 172, and contact 121 may be coupled with a metal layer 173. Metal layers 171, 172, and 173 may be associated with signals VDD, VSS, and Vout respectively, as illustrated in
Accordingly, what is needed are improved methods, systems and articles of manufacture for interconnecting semiconductor devices.
SUMMARY OF THE INVENTIONThe present invention generally relates to semiconductor devices, and more specifically to interconnecting semiconductor devices.
One embodiment of the invention provides a transistor, generally comprising a source region, a drain region, and a channel region coupled with the source region and the drain region. At least one of the source region and the drain region is a semiconductor fin structure, wherein at least a portion of the fin structure comprises a silicide material, the portion of the fin structure comprising the silicide material being configured to electrically couple one of the respective source region and drain region of the transistor with an associated circuit component of an electric circuit.
Another embodiment of the invention provides a method for connecting components of an electrical circuit. The method generally comprises forming a fin structure coupled with a first circuit component and at least one second circuit component of the electrical circuit, masking one or more areas of the electrical circuit wherein formation of silicide material is not desired, and forming a silicide layer on at least a portion of the fin structure, wherein the silicide material is configured to electrically connect the first circuit component to the at least one second circuit component.
Yet another embodiment of the invention provides an electrical circuit, generally comprising a first circuit component, a second circuit component, and a fin structure coupled with the first circuit component and the second circuit component. At least a portion of the semiconductor fin structure comprises a silicide material, wherein the portion of the semiconductor fin structure comprising the silicide material being configured to electrically connect the first circuit component to the second circuit component.
Yet another embodiment of the invention provides a design structure embodied in a machine readable medium for at least one of designing, manufacturing, and testing a design. The design structure generally includes a transistor, generally having a source region, a drain region, and a channel region coupled with the source region and the drain region. At least one of the source region and the drain region is a semiconductor fin structure, wherein at least a portion of the fin structure comprises a silicide material, the portion of the fin structure comprising the silicide material being configured to electrically couple one of the respective source region and drain region of the transistor with an associated circuit component of an electric circuit.
Yet another embodiment of the invention provides a design structure embodied in a machine readable medium for at least one of designing, manufacturing, and testing a design where the design structure generally includes an electrical circuit, generally having a first circuit component, a second circuit component, and a fin structure coupled with the first circuit component and the second circuit component. At least a portion of the semiconductor fin structure comprises a silicide material, wherein the portion of the semiconductor fin structure comprising the silicide material being configured to electrically connect the first circuit component to the second circuit component.
So that the manner in which the above recited features, advantages and objects of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The present invention generally relates to semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more devices or device components. By providing silicided fin structures to locally interconnect devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller and less complex circuits.
In the following, reference is made to embodiments of the invention. However, it should be understood that the invention is not limited to specific described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the invention. Furthermore, in various embodiments the invention provides numerous advantages over the prior art. However, although embodiments of the invention may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the invention. Thus, the following aspects, features, embodiments and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the invention” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Exemplary Local Interconnect StructuresGate structure 260 may be disposed along at least one face of the fin structures 230 and 250. For example, the gate structure may be disposed along the three faces, i.e., the top face and the side faces of fin structure 230. It is noteworthy that the gate structure 260 may be disposed on any number of faces of fin structure 230. For example, gate structure 260 may surround ails faces of fin structure 230 or, alternatively, in some embodiments, gate structure 260 may be disposed on the two side faces of fin structure 230.
In one embodiment of the invention, gate structure 260 may be made from one of polysilicon or amorphous silicon. Gate structure 260 may be formed by a suitable process known in the art, for example, Low Pressure Chemical Vapor Deposition (LPCVD).
The narrowness of fin structure 230 and the gating of fin structure 230 with gate structure 260 on at least two faces of fin structure 110 may provide greatly reduced short channel sensitivity and improved scalability of channel length. Furthermore, gate structure 260 may maintain a strong control of semiconductor potential and may screen a transistor source from penetrating into a transistor drain electric field. Such strong gate control may enable near ideal sub-threshold (Vt) swing, as well as reduced sensitivity of threshold (Vt) to drain voltage and channel length variations.
Source regions 210 and 240, and drain region 220 in
In one embodiment of the invention, the source regions, for example source regions 210 and 240 in
While a CMOS FinFET transistor structure is described herein to illustrate the use of local interconnect structures, one skilled in the art will recognize that embodiments of the invention may be used to provide local interconnects for any semiconductor device for example, n-type MOSFETs, p-type MOSFETS, pn junctions, bipolar transistors, and the like.
In one embodiment of the invention, it may be necessary to interconnect one or more components of a semiconductor device. For example, in a depletion mode MOSFET, it may be necessary to connect a drain region of the depletion mode MOSFET to the gate structure of the depletion mode MOSFET. Accordingly, a silicide layer may be formed on the drain region and a fin structure connecting the source region to the gate structure. For example, referring to
Alternatively, substrate 330 may be a Silicon-On-Insulator (SOI) substrate including an insulator layer 331 disposed on a semiconductor layer 332.
The fin structure 230 may be formed on the insulator layer 331, as illustrated in
Silicide cladding layer 310 may be formed with a semiconductor material and one or more electropositive elements. For example, in one embodiment, silicide cladding layer may be formed with silicon and one or more metals. Exemplary metals used to form the silicide cladding layer 310 may include tungsten, tantalum, cobalt, nickel, titanium, and the like. Silicide cladding layer 310 may be highly conductive. For example, in one embodiment, the silicide cladding layer 310 may be more conductive than polysilicon. Therefore, the silicide cladding layer 310 may electrically connect one or more components of a semiconductor device. For example, referring back to
Another advantage of using a silicide layer 310 to interconnect semiconductor device components may be that a silicide layer is capable of withstanding greater temperatures than metal interconnects while providing low resistance connections.
One reason for including a core region 320 may be to reduce the contact resistance due to the transition from a silicided interconnect region, for example, a silicided cladding layer 310, to a device component, for example, a transistor drain or source. The contact resistance from a silicided interconnect region to a device component may depend on the surface area at the interface of the silicided and unsilicided regions. By providing an unsilicided core, the surface area at the interface of silicided and unsilicided regions may be greatly increased, thereby reducing contact resistance.
In one embodiment of the invention, fin structure 230 may be fully silicided. In other words, a core region 320 may not be provided.
For example, the series resistance of the silicided interconnect may depend on the cross sectional area of the fully silicided core 410. In other words, because electrons may flow in a direction normal to the cross sectional area of the silicided region 410 illustrated in
Semiconductor core region 520 may be similar to the semiconductor core region 320 illustrated in
A relatively thick silicide cladding layer 510 may be provided to reduce series resistance. The thickness t of the silicide cladding layer may be sufficiently large to achieve a desired low series resistance value. Therefore, in the embodiment illustrated in
Forming a silicide interconnect may begin by first forming one or more other structures of a semiconductor device. For example, a source region, a drain region, a fin structure connecting the source and drain regions, and a gate structure of a transistor may first be formed before forming silicide interconnects. In one embodiment of the invention, one or more regions of the semiconductor device may be masked selectively to form the silicide interconnects in particular desired areas. For example, the gate structure of a transistor may be masked to prevent formation of silicide on the gate structure.
In one embodiment of the invention, a nitride layer may be formed on the top of the fin structure 630 as illustrated in
Silicidation of an exposed fin structure may begin by depositing a layer of metal over the exposed fin structure. Exemplary metals may include, for example, tungsten, tantalum, cobalt, nickel, titanium, and the like. Following deposition of metal on the exposed fin structure, an annealing procedure may be performed to incorporate the deposited metal in the fin structure to form a silicide layer on the fin structure. Annealing may be performed in a furnace under predetermined temperatures for a predetermined amount of time. Alternatively, LASER annealing, rapid thermal processing, and like annealing procedures may also be used.
In one embodiment of the invention, the annealing procedure may result in the formation of the silicide cladding layer 310 illustrated in
A selective metal etch may be performed after the annealing procedure to remove excess unreacted metal that may be left over on the surface of the fin. In one embodiment, the metal etch may be performed via wet etch procedures using, for example, a mixture comprised of H2SO4-H2O2-HCl-NHOH4-H3PO4-HNO3-CH3COOH.sup.-, and the like. In some embodiments, a second annealing procedure may be performed after removal of the unreacted metal to lower the silicide resistance.
In one embodiment of the invention, additional silicide material may be deposited on the fin structure to form a thick silicide cladding layer. For example, the annealing procedure described above may be used to form a silicide cladding layer 310 in a fin structure. Following formation of the silicide cladding layer additional silicide material may be deposited on the fin structure to form a thick silicide layer 510, as illustrated in
In step 708 a metal selective etch may be performed to remove unreacted metal. In step 710, additional silicide material may be disposed on the fin structure to form a thick silicide layer, such as, for example, a thick silicide layer 510 illustrated in
In some embodiments, the local interconnect structures described herein may be used to interconnect one or more components of one or more devices of a circuit. For example, in some embodiments, fin local interconnect structures may be used to connect circuit components such as for example, transistors, capacitors, resistors, inductors, and the like. In other embodiments, fin local interconnect structures may act as a bus line to carry one or more signals, such as for example, a power signal to one or more circuit components. By providing local interconnect structures that obviate the need for metal contacts and metal layers, embodiments of the invention allow smaller and cheaper integrated circuits to be built.
Each current mirror device 810-840 of IDAC circuit 800 may receive a digital input. For example, in
Exemplary crystallographic etchants may include, for example, Ammonium Hydroxide (NH4OH), Potassium Hydroxide (KOH), Tetramethylammonium Hydroxide (TMAH), Hydrazine, Ethylene Diamine Pyrocatechol (EDP), and the like. Crystallographic dependent etching is dependent etching is described in greater detail in copending, commonly assigned U.S. patent application Ser. No. 11/680,221, Attorney Docket No. ROC920060072US1, entitled FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY, filed Feb. 28, 2007, by Cheng et al. The aforementioned patent application is incorporated herein by reference in its entirety.
Referring back to
Current mirror device 820 may comprise two pairs of transistors similar to the pair of transistors in current mirror device 810, wherein, for each pair, the gate of the first transistor of the pair of transistors is couple with Vref, and the gate of the second transistor of the pair of transistors is coupled with the digital input S2. Current mirror devices 830 and 840 may be similarly constructed, wherein current mirror device 830 comprises 4 pairs of transistors, and current mirror device 840 comprises 8 pairs of transistors, as illustrated in
Each pair of transistors may be connected using silicided local interconnect structures. For example, a portion of one or more fins illustrated in
While an IDAC circuit is disclosed herein for illustrative purposes, one skilled in the art will recognize that embodiments of the invention may be implemented in any semiconductor circuit. Furthermore, any combination of silicided and unsilicided interconnects may be implemented. For example, in one embodiment, the Vss buses 910 may be formed with metal contacts and metal layers 1110, as illustrated in
Design process 1210 may include using a variety of inputs; for example, inputs from library elements 1230 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 1240, characterization data 1250, verification data 1260, design rules 1270, and test data files 1285 (which may include test patterns and other testing information). Design process 1210 may further include, for example, standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 1210 without deviating from the scope and spirit of the invention. The design structure of the invention is not limited to any specific design flow.
Design process 1210 preferably translates an embodiment of the invention as described above and shown in
By providing silicided local interconnect structures, embodiments of the invention allow the formation of smaller and cheaper circuits. Furthermore, because the need for metal contacts and metal layers is obviated, circuit complexity is also reduced.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims
1. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
- a transistor, comprising: a source region; a drain region; and a channel region coupled with the source region and the drain region, wherein at least one of the source region and the drain region is a semiconductor fin structure, and wherein at least a portion of the fin structure comprises a silicide material, the portion of the fin structure comprising the silicide material being configured to electrically couple one of the respective source region and drain region of the transistor with an associated circuit component of an electric circuit.
2. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the transistor.
3. The design structure of claim 1, wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits.
4. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
5. A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:
- an electrical circuit, comprising: a first circuit component; a second circuit component; and a fin structure coupled with the first circuit component and the second circuit component, wherein at least a portion of the semiconductor fin structure comprises a silicide material, the portion of the semiconductor fin structure comprising the silicide material being configured to electrically connect the first circuit component to the second circuit component.
6. The design structure of claim 5, wherein the design structure comprises a netlist, which describes the electrical circuit.
7. The design structure of claim 5, wherein the design structure resides on the storage medium as a data format used for the exchange of layout data of integrated circuits.
8. The design structure of claim 5, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.
Type: Application
Filed: Oct 26, 2007
Publication Date: Jan 1, 2009
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Kangguo Cheng (Guilderland, NY), Louis Lu-Chen Hsu (Fishkill, NY), Jack Allan Mandelman (Flat Rock, NC), William Robert Tonti (Essex Junction, VT)
Application Number: 11/925,387
International Classification: G06F 9/45 (20060101);