HERMETIC PACAKGING AND METHOD OF MANUFACTURE AND USE THEREFORE
An embodiment of the present invention provides a method of manufacturing hermetic packaging for devices on a substrate wafer, comprising forming a plurality of adhesive rings on a cap wafer or the substrate wafer, bonding the cap wafer to the substrate wafer with an adhesive layer, forming trenches in the cap wafer and the adhesive rings along outer rim of the adhesive rings, and covering sidewall of the trenches by at least one deposited film to provide a diffusion barrier to moisture or gas.
This application is a divisional of application Ser. No. 11/113,545, filed Apr. 25, 2005 claiming This claims the benefit of the following provisional patents: attorney's docket number JSF02-0009 filed Jun. 1, 2004 (APPL No. 60/575,586), attorney's docket number JSF02-0010 filed Sep. 7, 2004 (APPL No. 60/607,723), and attorney's docket number JSF02-0011 filed Nov. 8, 2004 entitled, “METHOD OF MANUFACTURING HERMETIC PACKAGING” (APPL NO TBD).BACKGROUND
Hermetic packaging, which provides tightly sealed cavities, has been used to protect many MEMS (micorelectromechnaical systems), such as optical, RF (radio frequency) and sensor devices, against moisture and other corrosive gases from seeping in, or to keep under controlled atmosphere. Specific examples include DLP™, bolometer, accelerometers and gyroscope. Wafer-level packaging offers advantages for packaging of cavities brings the cost advantage of simultaneously sealing an entire wafer of cavities. This eliminates the manufacturing inefficiencies and the costs of individual “pump down and pinch off” for archaic metal or ceramic packages. These potential cavity package advantages have sparked many development efforts for wafer-scale hermetic cavity packaging. The earliest cavity wafer-level packaging to be produced in large quantities were for protecting MEMS devices with moving surface elements. Millions of automotive airbag systems are today controlled by MEMS accelerometers residing in hermetic cavity wafer-level packages. More recently, cavity non-hermetic wafer-level packaging support high-volume consumer applications, such as digital cameras. Controlled-atmosphere hermetic cavity wafer-level packaging are currently being offered for MEMS RF switches. Further developments aim at size, weight and cost reductions for limited-lifetime products, or at economically meeting the more stringent requirements of high-performance, long-lifetime MEMS, optical devices and sensors.
Since cavity wafer-level packaging by their nature are generally precluded from adding layers over the active devices on the wafer surface, cavity packages are created either by bonding a second wafer with pre-formed cavities over the device wafer (wafer stacking) or by dicing the second wafer and bonding the individual cavity chips onto the device wafer (chip-on-wafer).
The present invention relates to manufacturing hermetic packaging cavities at the wafer level by wafer bonding and forming enclosures that is impervious to moisture or ambient gas. One approach to fabricating a wafer-level cavity package is to use epoxy to bond a cap wafer with a stenciled wafer for forming open cavities on one side first. Then this wafer is likewise bonded and sealed to the substrate wafer that contains MEMS devices (such as DLP™, accelerometers), thereby sealing numerous MEMS devices on the substrate wafer in enclosure cavities. This approach is very simple and cost effective. However, because of the permeability and possible out-gassing of the epoxy seals, the package is classified as non-hermetic. Another approach is to enclose the MEMS devices in deposited film using a sacrificial layer as temporary support, which is subsequently removed by etching through small holes in the deposited films, which is in turn sealed with deposited film. This approach is only suitable for very small devices because the films are much thinner than the cap wafers made from bulk material.SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method for manufacturing hermetic packages on wafer scale. It may use surface micromachining technique to fabricate the packaging. The technique may employ polymer bonding and thin film deposition to package MEMS or other devices under controlled atmosphere. They are impervious to moisture and gases and may be fabricated at low temperatures.
A method and system for cavity packaging MEMS devices, such as the DLP™ (digital light processor) on wafer scale in hermetic or vacuum seal is described herein. The processes of the wafer-level packaging begin during or after the final phase of the MEMS device fabrication process, and before the wafer are diced into separate chips. Referring now to
Referring to cross sectional view of
Reference is now made to cross sectional view of
Notches 144 may be formed in the cap wafer 100 between cavities along the gap 118 prior to bonding, as shown in
Formation of trench 104 is preferably done by sawing or etching. Sawing is preferred when cap wafer is a thick glass, which is more difficult to etch. Sawing can be done with a dicing saw 300 along the outer edge of the adhesive or polymer rings 102, as shown in cross-sectional view
Then a diffusion barrier 110 that is impermeable to moisture and other gases, is deposited to cover the sidewall of the trench 104, part of the cap wafer 100, the shoulder 103, and part of the substrate 10, as shown in cross-sectional view of
Sometime it may be desirable to remove all or a portion of the adhesive ring in the cavity enclosure 200. The purpose of total removal of the adhesive ring is to prevent outgas of the polymer. This is important if the packaging enclosure is vacuum. The partial removal of adhesive ring can be used to avoid thermal stress from thermal expansion coefficient difference between the polymer ring 102 and the diffusion barrier 110. Additionally, the remnant polymer ring can behave like pillars to support the cap wafer 100. This can be done by the following procedure; referring to
An alternative to patterning and etching etch-access holes 114 is described herein. Referring to perspective views of a small section of the wafer in
Bond pads needed for wire bonding are normally located in the gaps 118 as shown in
The method and system of packaging described hereinabove are applicable to packaging most MEMS devices such as deformable mirror devices (DMD) or TI's DLP™, inertial sensors, and radio frequency switches. Since these small packaging is enclosures or cavities very similar to many MEMS pressure sensors (see, for example, U.S. Pat. No. 6,346,742 Bryzek, et al.), they are suitable for making pressure sensors, wherein the cap wafer is thinned to a flexible membrane and the enclosure is empty.
2. A method of manufacturing hermetic packaging for MEMS devices on a substrate wafer before being diced into individual chips, comprising:
- forming separate adhesive rings on a top wafer with a gap between each other;
- bonding said top wafer to said substrate wafer with said adhesive rings to form a bonded wafer;
- Etching, sawing, or cutting through said top wafer along the edges of said gaps, but not through said adhesive rings, on both sides of said gap with a pattern, thereby exposing said gaps and outer rims of said adhesive rings to the open air, and forming a matrix of trenches on said bonded wafer, wherein the said trenches are centered at the middle of said gaps and have a width substantially larger than said gaps, to form a plurality of islands of cavity enclosures having said adhesive rings as sidewalls, said top wafer as cap; and said substrate as bottom;
- depositing and patterning a diffusion barrier on the outer surface of said sidewalls.
3. The method of claim 2, further comprises a stop of etching and patterning said diffusion barrier.
4. The method of claim 2, wherein said diffusion barrier comprises a metal or a ceramic layer.
5. The method of claim 2, wherein said trenches are formed by cutting with a dicing saw.
6. The method of claim 2, further comprising a step of forming metal or dielectric pillars on said top wafer or on said substrate wafer prior to said bonding said top wafer to said substrate wafer.
7. The method of claim 2, further comprising forming via holes through said cap wafer and said adhesive rings underneath, and forming interconnect through said via hole.
8. The method of claim 2, wherein said diffusion barrier further comprises a getter.
9. The method of claim 2, further comprising:
- (a) Depositing a structural layer on said sidewall;
- (b) forming etch-access holes on said structural layer;
- (c) removing part or all of said adhesive rings through said etch-access holes;
21. The method of claim 9, further comprising a step of sealing said etch-access holes with said diffusion barrier.
Filed: Jun 8, 2008
Publication Date: Jan 29, 2009
Inventor: Chang-Feng Wan (Dallas, TX)
Application Number: 12/101,957
International Classification: H01L 21/50 (20060101); B81C 1/00 (20060101);