Assembling Semiconductor Devices, E.g., Packaging , Including Mounting, Encapsulating, Or Treatment Of Packaged Semiconductor (epo) Patents (Class 257/E21.499)

  • Patent number: 10796999
    Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Boon Ping Koh, Eng Huat Goh, Jiun Hann Sir, Khang Choong Yong, Min Suet Lim, Wil Choon Song
  • Patent number: 10763199
    Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate having a front surface and a back surface opposite to the front surface, an interconnection structure disposed over the front surface of the substrate, a first passivation layer disposed over the back surface of the substrate, a second passivation layer disposed over the first passivation layer, and a TSV disposed in the substrate. In some embodiments, the TSV structure penetrates the substrate from the back surface of the substrate to the front surface of the substrate. In some embodiments, the TSV has an end portion protruding from the first passivation layer and separated from the second passivation layer.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: September 1, 2020
    Assignee: Nanya Technology Corporation
    Inventor: Shing-Yih Shih
  • Patent number: 10720403
    Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Hao Tsai, Li-Hui Cheng, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 10700021
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Patent number: 10693207
    Abstract: A Printed Circuit Board (PCB) and methods for manufacturing the PCB board are provided. The PCB includes a Radio Frequency (RF) signal transition at a RF signal pad. Multiple conductive layers other than a conductive signal layer of the PCB and conductive portions of the conductive signal layer not in electrical contact with a RF signal transmission trace have common ground connections forming a ground cage structure within the PCB around the RF signal pad and RF the signal transmission trace.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Ciena Corporation
    Inventors: Kaisheng Hu, Georges-Andre Chaudron, John David Wice
  • Patent number: 10686108
    Abstract: Disclosed is a semiconductor device package according to an embodiment, the semiconductor comprising: a substrate; first and second lead frames arranged on the substrate; a semiconductor device electrically connected to the first and second lead frames; a reflective layer arranged on the substrate so as to reflect the light emitted from the semiconductor device; and a lens arranged on the substrate so as to cover the semiconductor device, the reflective layer, and the first and second lead frames.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 16, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Sung Min Kong
  • Patent number: 10672754
    Abstract: A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Sung-Feng Yeh, Chi-Hwang Tai
  • Patent number: 10665570
    Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first semiconductor chip, a first through mold via (TMV) for connection that is spaced apart from the first semiconductor chip in an X-axis direction, a first TMV for bypass that is spaced apart from the first semiconductor chip in a Y-axis direction, and a redistribution line (RDL) pattern for connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second semiconductor chip, a second TMV for connection that is spaced apart from the second semiconductor chip in the Y-axis direction, and another RDL pattern for connecting the second semiconductor chip to the second TMV for connection. The second sub-package stacked is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: May 26, 2020
    Assignee: SK hynix Inc.
    Inventors: Juil Eom, Jae Hoon Lee, Bok Kyu Choi
  • Patent number: 10611632
    Abstract: A method includes, before attaching a window assembly to a semiconductor wafer, the semiconductor wafer including a plurality of integrated circuits and each integrated circuit including an electrical connection pad, adhering the window assembly to a carrier fixture. The method further includes, before attaching the window assembly to the semiconductor wafer, removing portions of the window assembly to create removal areas. The method then includes attaching the window assembly to the semiconductor wafer such that the electrical connection pad of each of the plurality of integrated circuits is within a removal area and removing the carrier fixture leaving the window assembly adhered to the semiconductor wafer with the electrical connection pad exposed of each of the plurality of integrated circuits.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: April 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Clayton Lee Stevenson, Frank Odell Armstrong
  • Patent number: 10483618
    Abstract: A semiconductor package includes a lower package including at least one electronic device, and an antenna unit disposed on an upper surface of the lower package, wherein the antenna unit includes: a ground portion disposed on an upper surface of the lower package, a radiating portion disposed to be spaced apart from the ground portion, and a support portion separating the radiating portion and the ground portion, and at least a portion between the radiating portion and the grounding portion is empty space.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Wook Park, Tah Joon Park, Jae Hyun Jung, Hwa Sun Lee, Seong Hun Na
  • Patent number: 10418359
    Abstract: A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Kanai, Motohito Hori, Satoshi Kaneko
  • Patent number: 10366907
    Abstract: There is provided a manufacturing method of a semiconductor package in which plural semiconductor chips different in the thickness are mounted. In the manufacturing method, the back surface of a package board in which the plural semiconductor chips on a wiring base are collectively sealed by a sealant is held by a holding tape and a resin layer is thinned by a shaping abrasive stone. Then, a dividing unit is caused to cut to the middle of the holding tape along planned dividing lines to divide the package board into individual semiconductor packages.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: Disco Corporation
    Inventors: Byeongdeck Jang, Youngsuk Kim
  • Patent number: 10281812
    Abstract: Disclosed is a projection device using a micro light emitting diode (LED) panel, the projection device including: a first micro LED panel configured to output light of a first wavelength using first micro LED pixels with the first wavelength; a second micro LED panel configured to output light of a second wavelength using second micro LED pixels with the second wavelength; a third micro LED panel configured to output light of a third wavelength using the first or second micro LED pixels; and a dichroic prism configured to synthesize lights output from the first to third micro LED panels, wherein the third micro LED panel includes a color conversion film for changing the light of the first or second wavelength to the light of the third wavelength.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: May 7, 2019
    Assignee: LUMENS CO., LTD.
    Inventors: Eun Sung Shin, Dong Hee Cho, Yong Pil Kim, Myung Ji Moon, Han Beet Chang, Jae Soon Park
  • Patent number: 10276621
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 10256148
    Abstract: The invention relates to a method of processing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area having no devices and being formed around the device area, wherein the device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The method comprises attaching a protective film, for covering the devices on the wafer, to the one side of the wafer, wherein the protective film is adhered to at least a part of the one side of the wafer with an adhesive, and providing a carrier having a curable resin applied to a front surface thereof.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: April 9, 2019
    Assignee: DISCO Corporation
    Inventor: Karl Heinz Priewasser
  • Patent number: 10232471
    Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 19, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Mathias Kaempf
  • Patent number: 10222671
    Abstract: The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Changseung Woo, Byunghyun Lee, Soonhwan Hong, Gyusik Won
  • Patent number: 10204841
    Abstract: A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: February 12, 2019
    Assignee: XILINX, INC.
    Inventors: Matthew H. Klein, Raghunandan Chaware
  • Patent number: 10193011
    Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Srinivasa Banna, Deepak Nayak, Luke England, Rahul Agarwal
  • Patent number: 10141251
    Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: November 27, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Risto Ilkka Tuominen
  • Patent number: 10110791
    Abstract: A camera module and an array camera module based on an integral packing process are disclosed. The camera module or each of the camera module units of the array camera module includes a circuit board, an integral base, a photosensitive element operatively connected to the circuit board, a lens, a light filter holder installed at the integral base and a light filter installed at the light filter holder. The light filter is not required to be directly installed to the integral base, so that the light filter is protected and the requiring area of the light filter is reduced.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 23, 2018
    Assignee: Ningbo Sunny Opotech Co., Ltd.
    Inventors: Mingzhu Wang, Bojie Zhao, Zhenyu Chen, Nan Guo, Takehiko Tanaka
  • Patent number: 10032740
    Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: July 24, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jong Sik Paek, Doo Hyun Park
  • Patent number: 10022937
    Abstract: This disclosure describes methods and devices useful for adhering a first substrate of a display to a second substrate of the display. In example embodiments, a first plate may be sealed to the first substrate, and a second plate may be sealed to the second substrate. In addition, a layer of adhesive may be disposed between the first and second substrates to assist in adhering the first substrate to the second substrate. A pressure may then be applied to the first and second plates as well as the first and second substrates to assist in the adhesion process. In example embodiments, the first plate may assist in applying pressure proximate a perimeter of the first substrate such that the perimeter of the first substrate adheres to a perimeter of the second substrate.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: July 17, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Weihsin Hou, Anoop Menon, Chin Siong Khor, Yean Chan Woon
  • Patent number: 10023461
    Abstract: The microintegrated sensor comprises a stack formed by a sensor layer, of semiconductor material, by a cap layer, of semiconductor material, and by an insulating layer. The sensor layer and the cap layer have a respective peripheral portion surrounding a central portion, and the insulating layer extends between the peripheral portions of the sensor layer and of the cap layer. An air gap extends between the central portions of the sensor layer and of the protection layer. A through trench extends into the central portion of the sensor layer as far as the air gap and surrounds a platform housing a sensitive element. The cap layer has through holes in the insulating layer that extend from the air gap and form a fluidic path with the air gap and the through trench.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: July 17, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventor: Andrea Picco
  • Patent number: 10014446
    Abstract: A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 3, 2018
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Tae Hwan Song
  • Patent number: 10008534
    Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/?10 degrees.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: June 26, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Rajesh Katkar
  • Patent number: 10008437
    Abstract: An electronic component device, includes: a lead frame including a terminal portion, the terminal portion including a columnar electrode and a metal plating layer, wherein the metal plating layer is formed on a lower surface of the electrode and a portion of a side surface of the electrode; an electronic component mounted on the lead frame to be electrically connected to the terminal portion; and a sealing resin that seals the lead frame and the electronic component, wherein another portion of the side surface of the electrode is embedded in the sealing resin and the metal plating layer is exposed from the sealing resin.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 26, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Shintaro Hayashi
  • Patent number: 9966371
    Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: May 8, 2018
    Assignee: General Electric Company
    Inventors: Risto Ilkka Tuominen, Arun Virupaksha Gowda
  • Patent number: 9950924
    Abstract: A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: April 24, 2018
    Assignee: mCube, Inc.
    Inventors: Sudheer S. Sridharamurthy, Te-Hse Terrence Lee, Ali J. Rastegar, Mugurel Stancu, Xiao Charles Yang
  • Patent number: 9921379
    Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: March 20, 2018
    Assignee: INPHI CORPORATION
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan, Roberto Coccioli
  • Patent number: 9923129
    Abstract: Various embodiments may relate to a method for producing an LED module, including providing a housing implemented as a hollow body, having an opening on a light exit side of the LED module, wherein the housing has a base side, arranged opposite to the light exit side, arranging a circuit board having one LED on the base side of the housing, pouring in one first base layer made of a curable material in a non-cured state through the opening into the housing, and pouring in a scattering layer made of a curable material in a non-cured state through the opening into the housing. The scattering layer is poured in onto the first base layer. The first base layer is not cured during the pouring in of the scattering layer, and after the pouring in of the scattering layer, the one first base layer and the scattering layer are cured.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 20, 2018
    Assignee: Osram GmbH
    Inventors: Martin Reiss, Simon Schwalenberg
  • Patent number: 9892916
    Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 13, 2018
    Assignee: ADVANPACK SOLUTIONS PTE LTD.
    Inventors: Shoa-Siong Raymond Lim, Hwee-Seng Jimmy Chew
  • Patent number: 9873166
    Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: January 23, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Mathias Kaempf
  • Patent number: 9875955
    Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 23, 2018
    Assignee: Tessera, Inc.
    Inventors: Kishor Desai, Qwai H. Low, Chok J. Chia, Charles G. Woychik, Huailiang Wei
  • Patent number: 9870968
    Abstract: A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which includes a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit. The packaged integrated circuit also includes a hermetic package comprising a base and a lid and a plurality of bond wires. The reconditioned die is placed into a cavity in the base. After the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds. After bonding the plurality of bond wires, the lid is sealed to the base.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 16, 2018
    Assignee: Global Circuit Innovations Incorporated
    Inventors: Erick Merle Spory, Timothy Mark Barry
  • Patent number: 9871026
    Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: January 16, 2018
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Debendra Mallik, Sasha N. Oster, Timothy E. McIntosh
  • Patent number: 9837453
    Abstract: After forming a doped semiconductor layer on a backside of a semiconductor substrate that has a conductivity type opposite a conductivity type of the doped semiconductor layer so as to provide a p-n junction for a photovoltaic cell, transistors are formed in a front side of the semiconductor substrate. The photovoltaic cell is then electrically connected to the transistors from the front side of the semiconductor substrate using through-dielectric (TDV) via structures embedded in the semiconductor substrate.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: December 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Effendi Leobandung
  • Patent number: 9812381
    Abstract: An integrated fan-out package is described. The integrated fan-out package comprises a first die and a second die arranged adjacent to each other. A molding compound encapsulates the first and second dies. A redistribution structure is disposed over the molding compound and on the first and second dies. The redistribution structure comprises a first connection structure electrically connected to the first die, a second connection structure electrically connected to the second die and an inter-dielectric layer located between the first and second connection structures and separating the first connection structure from the second connection structure. The ball pad is disposed on the redistribution structure and electrically connected with the first die or the second die. The bridge structure is disposed on the first connection structure and on the second connection structure and electrically connects the first die with the second die.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Hsi Wu, Chun-Yi Liu, Der-Chyang Yeh, Hsien-Wei Chen, Shih-Peng Tai, Chuen-De Wang
  • Patent number: 9761547
    Abstract: A system and method for vertically integrating heterogeneous devices into a 3D tile architecture are disclosed. The system uses high precision microelectronics fabrication techniques and known-good-die to achieve high yield to integrate devices to process radio frequency signals at microwave frequencies of approximately 300 MHz to 300 GHz and above. The inventive architecture is based on a high density of small diameter vias to manage the integrity of electrical interconnects and simplify electrical routing.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 12, 2017
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Elizabeth T. Kunkee, Charles M. Jackson, Dah-Weih Duan
  • Patent number: 9754805
    Abstract: A system and method for manufacturing a semiconductor device are provided. In an embodiment a first semiconductor device and a second semiconductor device are encapsulated with an encapsulant. A dielectric layer is formed over the encapsulant, the first semiconductor device, and the second semiconductor device. The dielectric layer is planarized in order to reset the planarity of the dielectric layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ching-Hua Hsieh, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 9735320
    Abstract: A method of manufacturing LED packages includes the steps of: forming a conductive circuit layer on a substrate; screen printing a wall layer on the conductive circuit layer to form a trellis with a plurality of wall units, so that regions of the conductive circuit layer surrounded by the wall units are exposed; mounting and electrically connecting at least one LED die on the conductive circuit layer within each of the wall units; molding a transparent layer to cover the LED dies; and cutting along the wall units to form a plurality of LED packages.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: August 15, 2017
    Assignees: Lite-On Electronics (Guangzhou) Limited, Lite-On Technology Corp.
    Inventor: Chen-Hsiu Lin
  • Patent number: 9651751
    Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 16, 2017
    Assignee: INPHI CORPORATION
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan, Roberto Coccioli
  • Patent number: 9640733
    Abstract: A carrier leadframe, including a frame body and a carrier, is provided. The frame body includes at least one supporting portion, and the carrier includes a shell and at least one electrode portion and is mechanically engaged with the frame body via the supporting portion. A method for manufacturing the carrier leadframe as described above, as well as a light emitting device made from the carrier leadframe and a method for manufacturing the device, are also provided. The carrier leadframe has carriers that are separate in advance and mechanically engaged with the frame body, thereby facilitating the quick release of material after encapsulation. Besides, in the carrier leadframe as provided, each carrier is electrically isolated from another carrier, so the electric measurement can be performed before the release of material. Therefore, the speed and yield of production of the light emitting device made from the carrier leadframe is improved.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: May 2, 2017
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Chung-Chuan Hsieh, Yung Chieh Chen
  • Patent number: 9640748
    Abstract: A thermal oscillator (10) for creating an oscillating heat flux from a stationary spatial thermal gradient between a warm reservoir (20) and a cold reservoir (30) is provided. The thermal oscillator (10) includes a thermal conductor (11) which is connectable to the warm reservoir (20) or to the cold reservoir (30) and configured to conduct a heat flux from the warm reservoir (20) towards the cold reservoir (30), and a thermal switch (12) coupled to the thermal conductor (11) for receiving the heat flux and having a certain difference between two states (S1, S2) of thermal conductance for providing thermal relaxation oscillations such that the oscillating heat flux is created from the received heat flux.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: May 2, 2017
    Assignee: International Business Machines Corporation
    Inventors: Bernd Gotsmann, Fabian Menges
  • Patent number: 9603283
    Abstract: An electronic module, and method for making same, includes free-formed, self-supported interconnect pillars that electrically connect cover electronic components disposed on a cover substrate with base electronic components disposed on a base substrate. The free-formed, self-supported interconnect pillars may extend vertically in a straight path between the cover electronic components and the base electronic components. The free-formed, self-supported interconnect pillars may be formed from an electrically conductive filament provided by an additive manufacturing process. By free-forming the self-supported interconnect pillars directly on the electronic components, the flexibility of electronic module design may be enhanced, while reducing the complexity and cost to manufacture such electronic modules.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: March 21, 2017
    Assignee: Raytheon Company
    Inventors: Brandon W. Pillans, James Mcspadden
  • Patent number: 9576595
    Abstract: A mounting surface of a read/write head is prepared to receive an epitaxial layer. The mounting surface is proximate a waveguide of the read/write head, and the waveguide is configured to receive an optical output from the epitaxial layer. The epitaxial layer is transfer printed on to the mounting surface. The mounting surface maintains a vertical alignment between the optical output and the waveguide. The epitaxial layer is processed to form a laser integrated with the read/write head.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: February 21, 2017
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Roger L. Hipwell, Jr., Mark Ostrowski, Marcus B. Mooney, Michael J. Hardy, Scott Eugene Olson, Mark Gubbins
  • Patent number: 9570422
    Abstract: An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: February 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: David J. West, Richard S. Graf
  • Patent number: 9570370
    Abstract: A multi chip package includes a protective layer having an upper surface that surrounds a first chip and a second chip, which are mounted over a first substrate, to expose an upper surface of the first chip and an upper surface of the second chip, a heat spreader disposed over the upper surfaces, and a thermal interface material disposed at an interface between the heat spreader and the upper surfaces.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: February 14, 2017
    Assignee: SK HYNIX INC.
    Inventors: Tac Keun Oh, Jong Hoon Kim, Ho Young Son, Jeong Hwan Lee
  • Patent number: 9530746
    Abstract: Chip mounting is provided in which the pitch between bumps can be further narrowed without establishing contact between bumps. In a chip mounting structure in which a flip-chip bond has been established between a chip and a board via bumps, the bumps are provided so that the height position of the bumps from the connection surface of the chip or the connection surface of the board has a difference in height exceeding the thickness of adjacent bumps. This further narrows the pitch between bumps without establishing contact between the bumps.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: December 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Satsuo Kiyono, Eiji Ohno, Masahiro Uemura
  • Patent number: 9520385
    Abstract: A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Kuo-Chuan Liu