Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a first dielectric structure disposed over a first semiconductor substrate, where the first dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the first dielectric structure and includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. A first piezoelectric anti-stiction structure is disposed between the movable mass and the first dielectric structure, wherein the first piezoelectric anti-stiction structure includes a first piezoelectric structure and a first electrode disposed between the first piezoelectric structure and the first dielectric structure.

Abstract: A semiconductor device includes a peripheral circuit region on a lower substrate, and including circuit elements, memory cell regions including memory cells on each of a first upper substrate and a second upper substrate, which are on the lower substrate, at least one cutting region between the first upper substrate and the second upper substrate, and at least one semiconductor pattern between the first upper substrate and the second upper substrate, and adjacent to the at least one cutting region.

Abstract: An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly.

Abstract: A wafer having on one side a device area with a plurality of devices is processed by providing a protective film and applying the protective film, for covering the devices on the wafer, to the one side of the wafer, so that a front surface of the protective film is in direct contact with the one side of the wafer. The protective film is heated during and/or after applying the protective film to the one side of the wafer, so that the protective film is attached to the one side of the wafer, and the side of the wafer opposite to the one side is processed. Further, the invention relates to a method of processing such a wafer in which a liquid adhesive is dispensed only onto a peripheral portion of a protective film and/or only onto a peripheral portion of the wafer.

Abstract: In accordance with an embodiment, a system includes a digital calibration filter device configured to receive a digital input signal based on a sensor output signal from a sensor, receive a sensor-specific control signal, and perform digital filter processing of the digital input signal to produce a calibrated output signal, wherein the digital filter processing is based on the sensor-specific control signal; and a control device configured to select the sensor-specific control signal from a plurality of sensor-specific control signals based on an ascertained influencing parameter, and provide the sensor-specific control signal to the digital calibration filter device.

Abstract: A feedstock for an additive manufacturing process includes a pre-ceramic polymer intermixed with a base material. A method of additive manufacturing includes melting and pyrolizing a feedstock containing metal and a pre-ceramic polymer. An article of manufacture includes an additive manufacturing component including a pyrolized feedstock.

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

Abstract: A method includes positioning an integrated circuit package in a coining apparatus having a fixture and a pressing plate. The integrated circuit package includes a substrate, an integrated circuit device disposed on a top surface of the substrate, and a plurality of solder balls disposed on a bottom surface of the integrated circuit package. The fixture includes a support structure and a cavity. The cavity receives the integrated circuit device while the support structure supports portions of a top surface of the integrated circuit package. The pressing plate is pressed against two or more of the solder balls, coining the two or more solder balls until each solder ball has a desired coined surface profile.

Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Abstract: A method for producing a plurality of piezoelectric multilayer components is disclosed. In an embodiment, a method for producing a plurality of piezoelectric multilayer components includes grinding the piezoelectric multilayer components without an addition of an abrasive by rubbing the piezoelectric multilayer components against one another so that a material abrasion of the piezoelectric multilayer components is carried out.

Abstract: The chip transfer method includes: firstly, (A) providing a carrier film carrying a plurality of chips and a substrate having an adhesive layer; next, (B) disposing the carrier film opposite the substrate so that the chips face the adhesive layer; then, (C) using an abutting element to pass through the carrier film to abut at least one of the chips, so that the chip is detached from the carrier film and attached to the adhesive layer; finally, (D) repeating step (C) to detach the remaining chips from the carrier film and attach the remaining chips to the adhesive layer.

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

Abstract: A package substrate and a method of fabricating the package substrate are provided. The package substrate includes a substrate having a first surface including a plurality of conductive pads and a second surface; an insulating protective layer formed on the first surface of the substrate; an interposer embedded in and exposed from the insulating protective layer; and at least a passive component provided on the first surface of the substrate. The insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening.

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

Abstract: The present disclosure provides a semiconductor package structure. The semiconductor package structure includes a substrate having a front surface and a back surface opposite to the front surface, an interconnection structure disposed over the front surface of the substrate, a first passivation layer disposed over the back surface of the substrate, a second passivation layer disposed over the first passivation layer, and a TSV disposed in the substrate. In some embodiments, the TSV structure penetrates the substrate from the back surface of the substrate to the front surface of the substrate. In some embodiments, the TSV has an end portion protruding from the first passivation layer and separated from the second passivation layer.

Abstract: A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die includes a second substrate and a second metal pad overlying the second substrate. A molding compound molds the first die and the second die therein. The molding compound has a first portion between the first die and the second die, and a second portion, which may form a ring encircles the first portion. The first portion and the second portion are on opposite sides of the first die. The first portion has a first top surface. The second portion has a second top surface higher than the first top surface.

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: A Printed Circuit Board (PCB) and methods for manufacturing the PCB board are provided. The PCB includes a Radio Frequency (RF) signal transition at a RF signal pad. Multiple conductive layers other than a conductive signal layer of the PCB and conductive portions of the conductive signal layer not in electrical contact with a RF signal transmission trace have common ground connections forming a ground cage structure within the PCB around the RF signal pad and RF the signal transmission trace.

Abstract: Disclosed is a semiconductor device package according to an embodiment, the semiconductor comprising: a substrate; first and second lead frames arranged on the substrate; a semiconductor device electrically connected to the first and second lead frames; a reflective layer arranged on the substrate so as to reflect the light emitted from the semiconductor device; and a lens arranged on the substrate so as to cover the semiconductor device, the reflective layer, and the first and second lead frames.

Abstract: A package manufacturing having a semiconductor substrate, a bonding layer, at least one semiconductor device, a redistribution circuit structure and an insulating encapsulation. The bonding layer is disposed on the semiconductor substrate. The semiconductor device is disposed on and in contact with a portion of the bonding layer, wherein the bonding layer is located between the semiconductor substrate and the semiconductor device and adheres the semiconductor device onto the semiconductor substrate. The redistribution circuit structure is disposed on and electrically connected to the semiconductor device, wherein the semiconductor device is located between the redistribution circuit structure and the bonding layer. The insulating encapsulation wraps a sidewall of the semiconductor device, wherein a sidewall of the bonding layer is aligned with a sidewall of the insulating encapsulation and a sidewall of the redistribution circuit structure.

Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first semiconductor chip, a first through mold via (TMV) for connection that is spaced apart from the first semiconductor chip in an X-axis direction, a first TMV for bypass that is spaced apart from the first semiconductor chip in a Y-axis direction, and a redistribution line (RDL) pattern for connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second semiconductor chip, a second TMV for connection that is spaced apart from the second semiconductor chip in the Y-axis direction, and another RDL pattern for connecting the second semiconductor chip to the second TMV for connection. The second sub-package stacked is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

Abstract: A method includes, before attaching a window assembly to a semiconductor wafer, the semiconductor wafer including a plurality of integrated circuits and each integrated circuit including an electrical connection pad, adhering the window assembly to a carrier fixture. The method further includes, before attaching the window assembly to the semiconductor wafer, removing portions of the window assembly to create removal areas. The method then includes attaching the window assembly to the semiconductor wafer such that the electrical connection pad of each of the plurality of integrated circuits is within a removal area and removing the carrier fixture leaving the window assembly adhered to the semiconductor wafer with the electrical connection pad exposed of each of the plurality of integrated circuits.

Abstract: A semiconductor package includes a lower package including at least one electronic device, and an antenna unit disposed on an upper surface of the lower package, wherein the antenna unit includes: a ground portion disposed on an upper surface of the lower package, a radiating portion disposed to be spaced apart from the ground portion, and a support portion separating the radiating portion and the ground portion, and at least a portion between the radiating portion and the grounding portion is empty space.

Abstract: A semiconductor device 100 includes a semiconductor element 12 having an electrode on a front surface, a wire 15 bonded to the electrode of the semiconductor element 12, a resin layer 22b covering a bonding portion of the wire 15 on the front surface of the semiconductor element 12, and a gel filler material 23 that seals the semiconductor element 12, the wire 15, and the resin layer 22b. By protecting the bonding portion of the wire 15 with the resin layer 22b, degradation of the wire 15 is ameliorated and the reliability of the semiconductor device 100 is improved.

Abstract: There is provided a manufacturing method of a semiconductor package in which plural semiconductor chips different in the thickness are mounted. In the manufacturing method, the back surface of a package board in which the plural semiconductor chips on a wiring base are collectively sealed by a sealant is held by a holding tape and a resin layer is thinned by a shaping abrasive stone. Then, a dividing unit is caused to cut to the middle of the holding tape along planned dividing lines to divide the package board into individual semiconductor packages.

Abstract: Disclosed is a projection device using a micro light emitting diode (LED) panel, the projection device including: a first micro LED panel configured to output light of a first wavelength using first micro LED pixels with the first wavelength; a second micro LED panel configured to output light of a second wavelength using second micro LED pixels with the second wavelength; a third micro LED panel configured to output light of a third wavelength using the first or second micro LED pixels; and a dichroic prism configured to synthesize lights output from the first to third micro LED panels, wherein the third micro LED panel includes a color conversion film for changing the light of the first or second wavelength to the light of the third wavelength.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract: The invention relates to a method of processing a wafer, having on one side a device area with a plurality of devices partitioned by a plurality of division lines and a peripheral marginal area having no devices and being formed around the device area, wherein the device area is formed with a plurality of protrusions protruding from a plane surface of the wafer. The method comprises attaching a protective film, for covering the devices on the wafer, to the one side of the wafer, wherein the protective film is adhered to at least a part of the one side of the wafer with an adhesive, and providing a carrier having a curable resin applied to a front surface thereof.

Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.

Abstract: The present disclosure relates to a thin film transistor substrate having a color filter layer. The present disclosure provides a thin film transistor substrate comprising: a plurality of pixel areas disposed in a matrix manner on a substrate, each pixel area including an aperture area and a non-aperture area; a first color filter and a second color filter stacked at the non-aperture area on the substrate; an overcoat layer disposed on the first color filter and the second color filter; a semiconductor layer disposed at the non-aperture area on the overcoat layer; a gate insulating layer and a gate electrode stacked on a middle portion of the semiconductor layer; a third color filter at the non-aperture area on the semiconductor layer and the gate electrode; and a source electrode and a drain electrode disposed on the third color filter.

Abstract: A method for fabricating integrated circuit (IC) dies and wafers having such dies, are disclosed herein that leverage temporary connection traces during wafer level testing of the functionality of the IC die. In one example, a wafer includes a plurality of IC dies. At least a first IC die of the plurality of IC dies includes a plurality of micro-bumps and a first temporary connection trace formed on an exterior surface of the die body. The plurality of micro-bumps includes at least a first micro-bump and a second micro-bump. The first temporary connection trace electrically couples the first micro-bump and the second micro-bump.

Abstract: Methods of forming an integrated RGB LED and Si CMOS driver wafer and the resulting devices are provided. Embodiments include providing a plurality of first color die over a CMOS wafer, each first color die being laterally separated with a first oxide and electrically connected to the CMOS wafer; providing a second color die above each first color die, each second color die being separated from each other with a second oxide, bonded to a first color die, and electrically connected to the CMOS wafer through the bonded first color die; removing a portion of each second color die to expose a portion of each bonded first color die; forming a conformal TCO layer over each first and second color die and on a side surface of each second color die and oxide; forming a PECVD oxide layer over the CMOS wafer; and planarizing the PECVD oxide layer.

Abstract: An electronic package is provided. The electronic package includes a substrate and a plurality of vias defined by a corresponding plurality of pre-defined via patterns. The electronic package further a metal built-up layer disposed on portions of the substrate to provide a plurality of pre-defined via locations and the plurality of pre-defined via patterns of the plurality of vias. Also, the electronic package includes a first conductive layer disposed on at least a portion of the metal built-up layer. Moreover, the electronic package includes a second conductive layer disposed on the first conductive layer, where the plurality of vias is disposed at least in part in the metal built-up layer, the first conductive layer, and the second conductive layer.

Abstract: A camera module and an array camera module based on an integral packing process are disclosed. The camera module or each of the camera module units of the array camera module includes a circuit board, an integral base, a photosensitive element operatively connected to the circuit board, a lens, a light filter holder installed at the integral base and a light filter installed at the light filter holder. The light filter is not required to be directly installed to the integral base, so that the light filter is protected and the requiring area of the light filter is reduced.

Abstract: A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

Abstract: This disclosure describes methods and devices useful for adhering a first substrate of a display to a second substrate of the display. In example embodiments, a first plate may be sealed to the first substrate, and a second plate may be sealed to the second substrate. In addition, a layer of adhesive may be disposed between the first and second substrates to assist in adhering the first substrate to the second substrate. A pressure may then be applied to the first and second plates as well as the first and second substrates to assist in the adhesion process. In example embodiments, the first plate may assist in applying pressure proximate a perimeter of the first substrate such that the perimeter of the first substrate adheres to a perimeter of the second substrate.

Abstract: The microintegrated sensor comprises a stack formed by a sensor layer, of semiconductor material, by a cap layer, of semiconductor material, and by an insulating layer. The sensor layer and the cap layer have a respective peripheral portion surrounding a central portion, and the insulating layer extends between the peripheral portions of the sensor layer and of the cap layer. An air gap extends between the central portions of the sensor layer and of the protection layer. A through trench extends into the central portion of the sensor layer as far as the air gap and surrounds a platform housing a sensitive element. The cap layer has through holes in the insulating layer that extend from the air gap and form a fluidic path with the air gap and the through trench.

Abstract: A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased.

Abstract: An electronic component device, includes: a lead frame including a terminal portion, the terminal portion including a columnar electrode and a metal plating layer, wherein the metal plating layer is formed on a lower surface of the electrode and a portion of a side surface of the electrode; an electronic component mounted on the lead frame to be electrically connected to the terminal portion; and a sealing resin that seals the lead frame and the electronic component, wherein another portion of the side surface of the electrode is embedded in the sealing resin and the metal plating layer is exposed from the sealing resin.

Abstract: In a microelectronic package, a first wire bond wire is coupled to an upper surface of a substrate. A first bond mass is coupled to another end of the first wire bond wire. A second wire bond wire is coupled to the upper surface. A second bond mass is coupled to another end of the second wire bond wire. The first and second wire bond wires laterally jut out horizontally away from the upper surface of the substrate for at least a distance of approximately 2 to 3 times a diameter of both the first wire bond wire and the second wire bond wire. The first wire bond wire and the second wire bond wire are horizontal for the distance with respect to being co-planar with the upper surface within +/?10 degrees.

Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

Abstract: A method for fabricating an integrated MEMS-CMOS device uses a micro-fabrication process that realizes moving mechanical structures (MEMS) on top of a conventional CMOS structure by bonding a mechanical structural wafer on top of the CMOS and etching the mechanical layer using plasma etching processes, such as Deep Reactive Ion Etching (DRIE). During etching of the mechanical layer, CMOS devices that are directly connected to the mechanical layer are exposed to plasma. This sometimes causes permanent damage to CMOS circuits and is termed Plasma Induced Damage (PID). Embodiments of the present invention presents methods and structures to prevent or reduce this PID and protect the underlying CMOS circuits by grounding and providing an alternate path for the CMOS circuits until the MEMS layer is completely etched.

Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

Abstract: Various embodiments may relate to a method for producing an LED module, including providing a housing implemented as a hollow body, having an opening on a light exit side of the LED module, wherein the housing has a base side, arranged opposite to the light exit side, arranging a circuit board having one LED on the base side of the housing, pouring in one first base layer made of a curable material in a non-cured state through the opening into the housing, and pouring in a scattering layer made of a curable material in a non-cured state through the opening into the housing. The scattering layer is poured in onto the first base layer. The first base layer is not cured during the pouring in of the scattering layer, and after the pouring in of the scattering layer, the one first base layer and the scattering layer are cured.

Abstract: A manufacturing method of a package substrate is provided. A conductive substrate is provided. A first photoresist layer is patterned to form first openings. A first conductive layer is formed in the first openings. A second photoresist layer is patterned to form second openings. A second conductive layer contacting the first conductive layer is formed in the second openings. The first and second photoresist layers are removed. A dielectric layer covers the first, second conductive layers and a portion of the conductive substrate. A portion of the dielectric layer is removed. A third photoresist layer is patterned to form a third opening. A portion of the conductive substrate is removed to form a fourth opening. The third photoresist layer is removed. A fourth photoresist layer is patterned to form a fifth opening. A bonding pad is formed in the fifth opening. The fourth photoresist layer is removed.

Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.

Abstract: A microelectronic assembly includes a substrate, a first and second microelectronic elements, a lead finger, electrical connections extending between contacts of the second microelectronic element and the lead fingers, and an encapsulant overlying at least portions of the first and second microelectronic elements, lead finger and electrical connections. The substrate has contacts at a first surface and terminals at an opposed second surface that are electrically connected with the substrate contacts. The first microelectronic element has contacts exposed at its front face. The front face of the first microelectronic element is joined to the substrate contacts. The second microelectronic element overlies the first microelectronic element and has contacts at a front face facing away from the substrate. The lead frame has lead fingers, wherein the second surface of the substrate and the lead fingers define a common interface for electrical interconnection to a component external to the microelectronic assembly.

Abstract: A packaged integrated circuit for operating reliably at elevated temperatures is provided. The packaged integrated circuit includes a reconditioned die, which includes a fully functional semiconductor die that has been previously extracted from a different packaged integrated circuit. The packaged integrated circuit also includes a hermetic package comprising a base and a lid and a plurality of bond wires. The reconditioned die is placed into a cavity in the base. After the reconditioned die is placed into the cavity, the plurality of bond wires are bonded between pads of the reconditioned die and package leads of the hermetic package base or downbonds. After bonding the plurality of bond wires, the lid is sealed to the base.

Abstract: Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a processor and memory. In one embodiment, a package assembly includes a die embedded in a subpackage directly coupled to another die attached to the subpackage. In some embodiments the subpackage may also contain power management devices. In some embodiments the die embedded in the subpackage and/or the power management device may overlap, or be located in, a region defined by the die coupled to the subpackage such that they are located between the die coupled to the subpackage and a substrate underlying the subpackage. Other embodiments may be described and/or claimed.