METHOD TO REDUCE RESIDUAL STI CORNER DEFECTS GENERATED DURING SPE IN THE FABRICATION OF NANO-SCALE CMOS TRANSISTORS USING DSB SUBSTRATE AND HOT TECHNOLOGY
A device and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.
The present invention relates generally to semiconductor devices and more particularly to methods for reducing corner defects generated during SPE in shallow trench isolation in the manufacture of semiconductor devices.
BACKGROUND OF THE INVENTIONComplementary metal oxide semiconductor (CMOS) devices (e.g., NMOS or PMOS transistors) have conventionally been fabricated on semiconductor workpieces with a single crystal orientation (e.g., silicon having a Miller index (100)). Transistors within the CMOS devices, for example, are used in cell phones, laptop computers, etc., requiring greater speed, lower power consumption, higher reliability, and the like. The speed of the devices can be improved by increasing electron mobility, hole mobility, or both, using hybrid orientation technology (HOT). Electron mobility/movement for NMOS devices, for example, is high (e.g., 2-4 times higher) when the NMOS devices are built on a Miller index (100) substrate, however the hole mobility for PMOS devices is enhanced when the PMOS devices are fabricated on a Miller index (110) substrate. As a result, PMOS devices formed on a Miller index (110) surface will exhibit significantly higher drive currents than PMOS devices formed on a Miller index (100) surface. In other words, there is a desire to exploit the substrate orientation with Miller index (110) for pFETs and Miller index (100) for nFETs, for example. Previous endeavors to take advantage of this difference between NMOS and PMOS devices has resulted in hybrid substrates with different surface orientations using workpiece composites to optimize the crystalline orientation of the NMOS and PMOS devices, for example.
Direct silicon bonded (DSB) substrates are fabricated by chemo-mechanically bonding a film of single-crystal silicon of a first crystal orientation onto a base substrate having a different or second crystal orientation. Unlike, silicon-on-insulator (SOI) substrates, DSB substrates demonstrate “bulk-like” properties.
The industry continues to seek new approaches to “force” electric charges to move at faster rates through the semiconductor device channels in an endless pursuit of increased circuit speeds and power consumption reductions. The ever decreasing size and scale of semiconductor device technology has presented numerous challenges. For example, gate leakage current due to sharp corner effects in thin silicon gate oxide is a more pronounced problem with smaller devices. These sharp features can also increase stresses, produce large electric fields, create dislocations in the silicon, and ultimately fail the device, for example.
Crystallographic planes are significant in both the semiconductor characteristics and applications since different crystallographic planes can exhibit significantly diverse physical properties. For example, surface density of atoms (i.e., atoms/cm2) on various crystallographic planes can differ substantially from each other. One of the standard notations for the various planes is the Miller indices that are used to denote the crystallographic planes and the directions normal to those planes. The general crystal lattice is represented by a set of unit vectors (e.g., a, b, and c) such that an entire crystal can be replicated by copying the unit cell of the crystal and duplicating it at a given integer offset along the unit vectors. For example, reproducing the basic cell at positions (na)a+(nb)b+(nc)c, wherein na, nb, and nc are integers. It is not a requirement that the unit vectors be orthogonal.
Amorphization templated recrystallization (ATR) is an approach for providing planar hybrid orientation substrates. Silicon is easily amorphized by ion implantation and easily recrystallized by a subsequent annealing.
Subsequently,
However, it should be noted that end-of-range defects 408 remain in the structure at an approximate depth based upon the implantation energy. These defects 408 are well known by those of ordinary skill in the art.
Subsequently,
As illustrated in
Subsequently,
Accordingly, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
SUMMARY OF THE INVENTIONThe following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
It is aspect of the present invention to provide a device with reduced residual STI corner defects formed by the process of forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, completing front end processing, and performing back end processing.
It is another aspect of the present invention to provide a method of fabricating a semiconductor device with reduced residual STI corner defects comprising forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation forming a pad oxide layer on the second silicon layer, forming a nitride layer on the pad oxide layer, forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench, implanting and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing and performing back end processing.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
The present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The drawings are not drawn to scale, nor are individual components within the drawings necessarily drawn in scale relative to one another.
In order to fully appreciate the various aspects of the present invention, a brief description of one embodiment of a semiconductor device including an STI region will be discussed. In the fabrication of semiconductor devices, isolation structures are formed between active areas in which electrical devices such as transistors, memory cells, or the like, are to be formed. The isolation structures, in this case STI structures, are typically formed during initial processing of a semiconductor substrate, prior to the formation of such electrical devices.
A modified amorphization templated recrystallization (ATR) approach for providing planar hybrid orientation substrates can be utilized in the present invention. As discussed supra, silicon is easily amorphized by ion implantation and easily recrystallized by subsequent SPE processing and annealing. The inventive solution enables the elimination of STI corner defects without the use of a subsequent anneal at extremely high temperature (e.g., greater than 1250 degrees Celsius) that can generate undesired mechanical stresses resulting in workpiece warping, and the like.
Turning now to the figures,
Device 2100 in
The nitride layer 2104 can provide protection for an electrical device active area formation during shallow trench creation. The nitride layer 2104 can be, for example, SiN, silicon nitride (Si3N4), reaction bonded silicon nitride (RBSN), hot pressed silicon nitride (HPSN), sintered silicon nitrides (SSN), and the like. The dielectric layer 2102 and the nitride layer 2104 together form what is referred to as a “hard mask”. During pattern transfer to an integrated circuit device, the hard mask layer is consumed during an etching process, for example. However, it is to be appreciated that any hard mask techniques may be practiced in this invention, and that other hard mask materials and masking processes are contemplated as falling within the scope of the invention.
A conventional photoresist (not shown) can be applied, for example and can be utilized to pattern and etch the nitride layer 2104 and the pad oxide layer 2102 in order to result in a patterned and etched device 2200 with a resultant STI trench 2206. The photoresist can be, for example, a solvent-based, light-sensitive resin solution that is uniformly applied, for example, on the nitride layer 2104 of the device 2200, utilizing a spin type process, and the like. The photoresist can, for example, be a chemical, negative photoresist that hardens when exposed to ultraviolet light or other light wavelengths and the unexposed photoresist can be dissolved by employing a developer solvent, leaving openings in the exposed photoresist. Another approach involves utilizing a positive photoresist that is initially insoluble, and when exposed to e.g., UV, mercury light, laser, x-rays, electron beam, etc., becomes soluble. After exposure, the photoresist can create the etch pattern needed to form the active STI trenches 2206 during, for example, reactive ion etching (RIE).
Referring to
In
The ion implantation 2304 ((
The device 2400 in
In
Referring to
Beginning at 2602 of
At 2608 a pad oxide layer (e.g., 10-20 nm) can be formed over the second substrate (110) utilizing a thermal oxide process, for example. Any appropriate process steps and materials can be employed in the formation of the oxide layer at 2608, including oxidation processes as are well known to those of ordinary skill in the art. At 2610 a nitride layer (e.g., 150-200 nm) can be formed over the oxide layer at 2608. Known deposition processes by those of ordinary skill in the art can be employed in the formation of the nitride layer at 2610. The nitride layer, as discussed in
The methodology continues at 2614, where a soluble photoresist (exposed or un-exposed), for example is developed or etched away exposing the outer surface of the nitride layer formed at 2610. The process at 2614 results in a pattern being formed on the substrate allowing for STI trench formation. At 2616 a nitride layer and oxide layer etching process can be performed. As disclosed in
At 2616 a recessed active trench can be created in the substrate. The etching procedure may be, for example, a single step or multi-step process, a wet or dry etch process, by which material is removed in the exposed isolation regions in the semiconductor substrate to form the isolation trenches. At 2618 the photoresist is removed. The process of removing photoresist is well known by those of ordinary skill in the art. The oxide and nitride layers can protect the surface of “active areas” from subsequent chemical mechanical polishing (CMP), for example. The nitride layer can provide protection for an electrical device active area formation during shallow trench creation. The nitride layer can be, for example, SiN, silicon nitride (Si3N4), reaction bonded silicon nitride (RBSN), hot pressed silicon nitride (HPSN), sintered silicon nitrides (SSN), and the like. The exemplary method 2600 continues at 2620, for example, a photoresist can be formed over the PMOS active area as illustrated. The photoresist can be applied to the device followed by patterning involving photoresist removal and a standard clean in that is well known by those of ordinary skill in the art. The device can be implanted utilizing Si+ and/or Ge+ at 2622 through the nitride-oxide hard mask, for example as discussed supra. The implant dose and energy can be in the range of 2.5-5.0E15/cm2 and 200-300 keV, respectively, for example. The device after the first silicon layer has been amorphized (α-Si) by ion implantation to create an amorphous layer. The amorphized layer can be approximately 250-350 nm deep, for example.
The change of the crystal orientation of the top silicon layer can be realized as an amorphized top layer which will re-grow aligned to the handle workpiece crystalline structure, for example. SPE can be employed at 2624 by a low temperature anneal in an Ar, N2 or H2 environment, for example. Typical ranges for temperatures can be respectively 400-700 degrees Celsius. After SPE, an anneal (e.g., greater than 1050 but less than 1250 degrees Celsius, 10 sec, N2, Ar or H2 environment) can be applied to reduce residual crystal damage. The damage can be in the form of stable end-of-range damage induced dislocation loops located at the amorphous/silicon interface, STI corner defects, and the like, for example. The inventors recognized that by keeping the anneal temperature below 1250 degrees Celsius that wafer warpage defects, and the like would be reduced. In order to be able to remove the corner defects without applying extremely high conventional temperature anneals (e.g., greater than 1250 degrees Celsius) the SPE can be conducted before the oxide lining and oxide filling of the trench. The “free” sidewall surface of the trench provides the silicon atoms more freedom in realigning to the handle workpiece crystalline structure during SPE. The atoms are not constrained and there for can move at the sidewall surface.
This can be followed at 2626 with the deposition or forming of a dielectric trench liner that can be formed over the exposed portions of the STI trench. The trench dielectric liner can be deposited or formed in any suitable process step, such as, a thermal growth process at the exposed trench surfaces, including sidewall recesses and center section of the etched STI trench. As discussed supra, the trench dielectric liner can be deposited to act as a protective layer of the trench, to act as a high purity spacer between the silicon and the fill dielectric, and the like. The trench lining process can be, for example, a thermal process, a LVCVD process, a thermal process bi-layered liner, a chemical oxide process in combination with LPCVD films, and the like. It should be apparent to those of ordinary skill in the art that other trench liner materials (e.g., nitride), multiple isolation liners, no liners at all, and the like are contemplated with this invention. At 2626 the front end processing can be completed, for example. Front end processing can include filling the STI trench with oxide and chemical mechanical polishing, and the like.
The exemplary method 2600 continues at 2628, for example, where back end processing can be completed. The back end processing of CMOS devices is well known by those of ordinary skill in the art and can include forming metal interconnect layers, and the like. The process ends at 2630.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
Claims
1. A semiconductor device with reduced residual STI corner defects formed by the process of:
- forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation;
- forming a pad oxide layer on the second silicon layer;
- forming a nitride layer on the pad oxide layer;
- forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate;
- patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench;
- implanting and amorphizing an NMOS region of the direct silicon bonded substrate;
- removing the photoresist;
- performing solid phase epitaxy;
- performing a recrystallization anneal;
- completing front end processing; and
- performing back end processing.
2. The device of claim 1, wherein the first silicon layer comprises a Miller index (110) silicon and the handle substrate with a Miller index of (100).
3. The device of claim 1, wherein the first silicon layer comprises a Miller index (100) silicon and the handle substrate with a Miller index of (110);
- patterning an NMOS region of the direct silicon bonded substrate instead of the PMOS region utilizing photoresist including a portion of the isolation trench; and
- implanting and amorphizing the PMOS region of the direct silicon bonded substrate.
4. The device of claim 1, wherein the recrystallization anneal is performed at a temperature of less than 1250 degrees Celsius.
5. The device of claim 1, wherein the nitride layer is deposited using a technique comprising deposition by evaporation, sputtering, chemical-vapor deposition.
6. The device of claim 1, wherein front end processing comprises at least one of the following: forming an STI liner, filling the STI trench with oxide, and chemical mechanical polishing.
7. The device of claim 1, wherein the recrystallization anneal is performed in an environment comprising: N2, Ar, and H2.
8. A method of fabricating a semiconductor device with reduced residual STI corner defects comprising:
- forming a direct silicon bonded substrate wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation;
- forming a pad oxide layer on the second silicon layer;
- forming a nitride layer on the pad oxide layer;
- forming an isolation trench within the direct silicon bonded substrate through the second silicon layer and into the handle substrate;
- patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist including a portion of the isolation trench;
- implanting and amorphizing an NMOS region of the direct silicon bonded substrate;
- removing the photoresist;
- performing solid phase epitaxy;
- performing a recrystallization anneal;
- forming an STI liner;
- completing front end processing; and
- performing back end processing.
9. The method of claim 8, wherein the first silicon layer comprises a Miller index (110) silicon and the handle substrate with a Miller index of (100).
10. The method of claim 8, wherein the first silicon layer comprises a Miller index (100) silicon and the handle substrate with a Miller index of (110).
11. The method of claim 8, wherein the recrystallization anneal is performed at a temperature of less than 1250 degrees Celsius.
12. The device of claim 8, wherein the recrystallization anneal is performed in an environment comprising: N2, Ar, and H2.
13. The method of claim 8, wherein the nitride layer is deposited using a technique comprising deposition by evaporation, sputtering, chemical-vapor deposition.
14. The device of claim 8, wherein front end processing comprises at least one of the following: filling the STI trench with oxide, and chemical mechanical polishing.
Type: Application
Filed: Aug 29, 2007
Publication Date: Mar 5, 2009
Inventors: Angelo Pinto (San Diego, CA), Periannan R. Chidambaram (Richardson, TX), Rick L. Wise (Fairview, TX)
Application Number: 11/847,053
International Classification: H01L 21/76 (20060101); H01L 29/00 (20060101);