PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING DEPOSITING A CONDUCTIVE LAYER OVER A SEED LAYER

Abstract

A process of forming an electronic device can include placing a seed layer into an electroplating solution within an electroplating tool. The electroplating tool can include a first electrode and a second electrode, wherein the first electrode is electrically connected to the seed layer. The process can also include depositing a first portion of a conductive layer using a first signal of a first type (e.g., direct current) between the first electrode and a second electrode, and depositing a second portion of the conductive layer over the first portion of the conductive layer, using a second signal of a second type (e.g., alternating current) between the first electrode and the second electrode of the electroplating tool.

Description

BACKGROUND

1. Field of the Disclosure

The present disclosure relates to processes of electroplating conductive layers and more particularly to processes of electroplating conductive layers using an electroplating tool.

2. Description of the Related Art

Electronic devices can include conductive layers that are deposited by electroplating. One or more compounds can be added to an electroplating solution to affect the electroplating of a conductive layer over a patterned layer and within openings in the patterned layer. For example, a suppressor can be used to the reduce local electroplating rate along the upper corners of the openings, an accelerator can be added to increase the local electroplating rate within the openings, and a leveler can be added to reduce the local electroplating rate along a relatively flat, exposed surface. When all three compounds are used, electroplating can be performed using direct current during all of the electroplating.

A leveler is optional and may not be used. When a leveler is not used in the electroplating solution, an alternating current is typically used. The process without the leveler has problems that are better understood with respect to the illustrations in FIGS. 1 and 2. FIG. 1 includes an illustration of a substrate 12 that includes openings 15 and 16, and a seed layer 14 that lies along the surface of the substrate 12 and within the openings 15 and 16. A barrier layer can be used and would lie between the substrate 12 and the seed layer 14, but the barrier layer is not illustrated to simplify understanding. The seed layer 14 lies along the upper exposed regions 112 of the substrate, the corners of the openings 18, the sides of the openings 114, and the bottoms 110 of the openings.

FIG. 2 includes an illustration after electroplating a conductive layer 22 over the seed layer 12. One or more problems may occur during electroplating. For example, the accelerator can increase the deposition rate along the bottoms of the openings 110 relative to another location, such as the corners 18 of openings 15 and 16. As the opening 15 fills, the accelerator can remain active and continue to enhance the deposition rate through substantially the entire electroplating process. After the opening 15 has been filled, the accelerator can continue to affect the deposition rate above the opening, and a mound 24 can be formed as illustrated near the left-hand side in FIG. 2.

A pulse reverse waveform can be used to help control the mounding without the complexity of adding and controlling the leveler to the electroplating solution. However, when the current flow is reversed, a portion of the electroplated layer is removed. Again referring to FIG. 1, the seed layer 14 has a relatively thinner portion along the sidewalls 114, where the resistance of the conductive layer 14 may be higher than another location where the seed layer 114 is relatively thicker. Such differences in resistance can shift the electroplating and deplating rates differently at different locations along the seed layer 14, and thus contribute to void formation when a pulse reverse waveform is used. Referring to the opening 16 to the right-hand side of FIG. 2, a void 26 has been formed within the opening 16 during electroplating. After the electroplating, a workpiece may have mounds, voids, or a combination of mounds and voids.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

FIG. 1 includes an illustration of a cross-sectional view of a workpiece including a substrate, openings in the substrate, and a seed layer over the substrate. (Prior art)

FIG. 2 includes an illustration of a cross section of the workpiece of FIG. 1 after electroplating a conductive layer within the openings. (Prior art)

FIG. 3 includes an illustration of a cross-sectional view of a workpiece after forming an opening in an insulating layer overlying a substrate to expose a conductive portion of the substrate.

FIG. 4 includes an illustration of a cross-sectional view of the workpiece of FIG. 3 after forming a barrier layer and a seed layer.

FIG. 5 includes an illustration of a schematic diagram of the workpiece of FIG. 4 within an electroplating tool.

FIG. 6 includes an illustration of a circuit within a controller of the electroplating tool of FIG. 5.

FIG. 7 includes an illustration of a cross sectional view of the workpiece of FIG. 5 when forming a first portion of a conductive layer over the seed layer.

FIG. 8 includes an illustration of a cross sectional view of the workpiece of FIG. 7 when forming a second portion of the conductive layer.

FIG. 9 includes an illustration of a cross sectional view of the workpiece of FIG. 8 after removing the workpiece, including the conductive layer, from the electroplating tool.

FIG. 10 includes an illustration of a cross sectional view of the workpiece of FIG. 9 after removing portions of the barrier, seed, and conductive layers.

FIG. 11 includes an illustration of a cross sectional view of a system including an electronic device formed by a process described herein.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.

DETAILED DESCRIPTION

A process of forming an electronic device can include placing a seed layer overlying a substrate into an electroplating solution within an electroplating tool. A first electrode of the electroplating tool can be electrically connected to the seed layer, and a second electrode of the electroplating tool is disposed within the electroplating solution. The process can include depositing a first portion of a conductive layer over the seed layer, wherein depositing the first portion is performed using a first signal of a first type (e.g., direct current or DC) between the first electrode and a second electrode. The process can further include depositing a second portion of the conductive layer over the first portion of the conductive layer, wherein depositing the second portion is performed using a second signal of a second type (e.g., alternating current or AC) between the first electrode and the second electrode of the electroplating tool.

In an exemplary, non-limiting embodiment, initial electroplating of the conductive layer can be performed using a DC signal, and subsequent electroplating of the conductive layer can be performed using an AC signal. The electroplating solution does not require a leveler as used in conventional method where a DC signal is used during the entire electroplating process. Therefore, costs and the technical complexity of having an extra additive (e.g., the leveler) can be omitted. Also, by using a DC signal during the initial electroplating, erosion of the seed layer within the openings during the initial electroplating, which may occur with a reverse bias pulse of an AC signal, can be reduced or eliminated. Thus, in this particular embodiment, the mounding, void formation, or both issues can be significantly reduced or potentially eliminated.

Attention is now directed to particular embodiments of forming an electronic device, as illustrated in FIGS. 3 to 10. FIG. 3 includes an illustration of a cross-sectional view of a workpiece that includes a partially formed electronic device. The workpiece includes a substrate 30 that can include a monocrystalline semiconductor wafer, a semiconductor-on-insulator wafer, a flat panel display (e.g., a silicon layer over a glass electroplate), or other substrate conventionally used to form electronic devices. An electronic component 314 lies within the substrate 30, over the substrate 30, or both. In a particular embodiment, the electronic component 314 can be a transistor, a diode, a capacitor, a resistor, or an inductor. As illustrated in FIG. 3, the electronic component 314 includes a transistor structure. The workpiece can include many other electronic components that may be substantially the same or different from the electronic component 314.

An insulating layer 32 overlies the substrate 30 and the electronic component 314. The insulating layer 32 can include an insulating material, such as an oxide, a nitride, an oxynitride, or a combination thereof. The insulating layer 32 can include a single insulating film or a plurality of insulating films. The thickness of the insulating layer 32 needs to be sufficient to provide electrical insulation between conductors at different elevations. Although the insulating layer 32 does not have a theoretical upper limit on its thickness, other considerations may limit the thickness of the insulating layer 34 from a practical standpoint (e.g., ability to form reproducibly openings to an underlying conductor, equipment throughput, etc.). In one embodiment, the insulating layer 32 has thickness no greater then 5000 nm, no greater than 2000 nm, or no greater than 900 nm, and in another embodiment, the insulating layer 32 has a thickness at least 110 nm, at least 300 nm, or at least 700 μm. In still another embodiment, the insulating layer 32 can be thicker or thinner than those thicknesses.

A conductive plug 34 lies within an opening within the insulating layer 32. The conductive plug 34 is electrically connected to the electronic component 314. The conductive plug 34 can include doped silicon, tungsten, another suitable conductive material, or any combination thereof. The conductive plug 34 can include a glue layer, a barrier layer, or any combination thereof before forming a fill material, such as tungsten or the like.

An insulating layer 36 overlies the insulating layer 32. The insulating layer 32 can include an insulating material, such as an oxide, a nitride, an oxynitride, or a combination thereof. The insulating layer 36 can include a single insulating film or a plurality of insulating films. As compared to the insulating layer 32, insulating layer 36 can have the same or different composition, the same or different number of films, and the same or different thickness.

An opening 38 is formed through the insulating layer 36 to expose the conductive plug 34. The width of the opening 38 is sufficiently wide to allow for the proper formation of a subsequently-formed conductor within the opening 38, but not so wide as to form a contact to a different underlying conductor to which a subsequently-formed conductor is not to make electrical contact. The opening 38 has a width 310, which in one embodiment is less than 900 nm, less than 300 nm, or less than 130 nm. The depth of the opening 38 is substantially the same as the thickness of the insulating layer 32 near the opening 32. An aspect ratio is the ratio of the depth of the opening 38 to the width of the opening 38 can be 1:2, 1:1, 2:1, 5:1, 9:1, a higher ratio, or any value between those listed.

As used within this specification, length, width, and depth refer to different dimensions of feature. The length and width are seen from a top view of the feature, wherein the width is the same size or smaller than the length, and depth is seen from a cross-sectional view of the feature.

The workpiece with the component 314, insulating layers 32 and 36, conductive plug 34, and opening 38 are formed using conventional or proprietary techniques. Such techniques can include film growth, film deposition, etching, polishing, ion implantation, silicide reaction, or any combination thereof.

FIG. 4 includes an illustration of a cross-sectional view of the workpiece 40 after forming a barrier layer 42 and a seed layer 44 over the insulating layer 36 and within the opening 38. The barrier layer 42 is formed over the insulating layer 36 and within the opening 38. The barrier layer 42 has a composition and thickness sufficient to keep a material from a subsequently-formed conductor from migrating into the insulating layer 32, 36, or both. The barrier layer 42 can include a nitrogen-containing material, such as a metal nitride, a metal semiconductor nitride, or a combination thereof. For example, the barrier layer can include TiN, Ti/TiN, TaN, Ta/TaN, WN, TaSiN, another suitable conductive nitrogen-containing material, or any combination thereof. The barrier layer 42 can include a single film or more than one film. In one embodiment, the barrier layer 42 can include an adhesion film in addition to the nitrogen-containing film. The adhesion film lies between the insulating layer 36 and a nitrogen-containing film to reduce the likelihood that the nitrogen-containing film will delaminate from the insulating layer 36. In one embodiment, the barrier layer 42 has a thickness no greater than 90 nm, no greater than 50 nm, or no greater than 30 nm, and in another embodiment, the barrier layer 42 has a thickness at least 2 nm, at least 11 nm, or at least 20 nm. In still another embodiment, the barrier layer 42 can be thicker or thinner than those thicknesses. The barrier layer 42 can be formed by a conventional or proprietary technique. In one embodiment, the barrier layer 42 can be formed by using a physical vapor deposition, such as sputtering.

A seed layer 44 is deposited over the barrier layer 42. The seed layer 44 includes a conductive layer that promotes electroplating onto the workpiece 40. The seed layer 44 typically includes the same material that will be subsequently electroplated. For example, if copper is to be electroplated, the seed layer 44 can include copper. In another embodiment, the seed layer 44 can have a composition dissimilar to the material that will subsequently be electroplated. The thickness of the seed layer 44 is sufficient to cover all surfaces of the barrier layer 42. In one embodiment, the seed layer 44 has a thickness no greater than 90 nm, no greater than 50 nm, or no greater than 30 nm, and in another embodiment, the seed layer 44 has a thickness at least 2 nm, at least 11 nm, or at least 20 nm. In still another embodiment, the seed layer 44 can be thicker or thinner than those thicknesses. The seed layer 44 can be formed by a conventional or proprietary technique. In one embodiment, the seed layer 44 can be formed by using a physical vapor deposition, such as sputtering.

In one embodiment, the barrier layer 42, the seed layer 44, or both may be locally thinner along the side of the opening 38 than along surface of the insulating layer 32. Further, the thickness along the side of the opening 38 can decrease as a function of the distance from the top of the opening 38.

The barrier layer 42 and the seed layer 44 have a combined thickness 46 that only partly, and not completely, fills the opening 38. In one embodiment, the combined thickness 46 has a thickness no greater than 90 nm, no greater than 50 nm, or no greater than 30 nm, and in another embodiment, the combined thickness 46 has a thickness at least 4 nm, at least 11 nm, or at least 20 nm. In still another embodiment, the combined thickness 46 can be thicker or thinner than those thicknesses.

In a further embodiment, the width 310 is no greater than 20 times the combined thickness 46, no greater than 15 times the combined thickness 46, or no greater than 9 times the combined thickness 46, and in still a further embodiment, the width 310 is at least 3 times the combined thickness 46, at least 5 times the combined thickness 46, or at least 7 times the combined thickness 46. In still another embodiment, the width 310 can be more times or less times the combined thickness 46. The resulting workpiece 40 is ready for electroplating.

FIG. 5 includes an illustration of a schematic diagram of the workpiece 40 within an electroplating tool 50. The electroplating tool 50 and its relationship with the workpiece 40 during electroplating are described before addressing the details during the entry portion of the electroplating process (i.e., when the workpiece 40 initially comes in contact with the electroplating solution 59).

The electroplating tool 50 includes a chamber 51 with an outlet port 502. The electroplating tool 50 further includes a cup 52 that has an inlet port 512 for receiving an electroplating fluid. An anode (one of the electrodes of the electroplating tool 50) lies between the cup 52 and workpiece 40. The anode includes a material that is to be electroplated onto the workpiece. The anode can include an elemental metal, such as copper, nickel, a noble metal (gold, silver, platinum, palladium, osmium, or iridium), or another suitable metal. In the embodiment as illustrated, the electroplating tool 50 includes three anodes 541, 542, and 543. The anode 543 can be generally circular, and anodes 541 and 542 can be annular rings surrounding the anode 543. Each of the anodes 541, 542, and 543 are coupled to a controller 58 that can control the anodes 541, 542, and 543 independently of one another to allow for more uniform electroplating across the surface of the workpiece 40. In another embodiment, more or fewer anodes can be used.

The electroplating tool further includes a head 55 that has a turntable 551 and clamp ring 552. The clamp ring 552 is the cathode for the electroplating tool 50 and is electrically coupled to the controller 58. The clamp ring 552 can include a conductive material that is dissimilar to the material that is to be electroplated onto the workpiece 40, such that material that electroplates onto the clamp ring 552 may be subsequently removed selective to the material that makes up the clamp ring 552. The workpiece 40 is mounted to the head 52 so that the seed layer 44 (not illustrated in FIG. 5) is in contact with the clamp ring 551. In other words, the workpiece 40 will be oriented such that the seed layer 44 is exposed to the electroplating solution 59 (faces the anodes 541, 542, and 543). In the operation of the electroplating tool 50, the electroplating solution 59 enters the cup 52 through the inlet port 512, flows by the anodes 541, 542, and 543, at which point ions from the anodes 541, 542, and 543 are dissolved into the electroplating solution 59. The electroplating solution 59 eventually flows over the sides of the cup 52, down between the walls of the cup 52 and the chamber 51, and through the outlet port 502.

The composition of the electroplating solution 59 can depend on the material that is to be electroplated onto the workpiece 40. When copper is to be electroplated, the electroplating solution 59 can include copper, copper sulfate (Cu₂SO₄), sulfuric acid (H₂SO₄), chloride ions, such as those from HCl, and water. Other chemicals are used if a material other than copper is to be electroplated. Skilled artisans will be able to determine the basic chemistry for the material to be electroplated.

The electroplating solution 59 can also include organic additives. In one embodiment, the electroplating solution 59 includes an accelerator and a suppressor. The accelerator helps to accelerate electroplating near the bottom of the opening 38 (see FIG. 4). The suppressor helps to suppress electroplating near the upper corner of the opening 38. The accelerator can include a disulfide, and the suppressor can include a polymeric diol (e.g., polyethylene glycol or the like). After reading this specification, another conventional or proprietary accelerator or suppressor can be used in place of or in addition to the accelerator or suppressor listed. In one embodiment, no leveler (e.g., an amine) is used in the electroplating solution 59. In another embodiment, more, fewer, or different additives can be used.

FIG. 6 includes a control circuit 60 within the controller 58. The control circuit can control the anode 541, 542, 543, or any combination thereof. The control circuit includes switches 62 that can be configured to allow current to flow through the upper conduction path or the lower conduction path. The switches 62 can include a transistor, a multiplexer, a demultiplexer, a relay, a mechanical switch, another suitable switch, or the like. The switches 62 can be controlled manually or by suitable hardware, firmware, or software within the controller 58.

The upper conduction path includes a DC signal source 64 and a timing circuit 66. The upper conduction path is used during entry and other initial electroplating. The timing circuit 66 can be used to reduce a sudden surge in current when the workpiece 40 initially contacts the electroplating solution 59, as will be described in more detail below. The timing circuit 66 can include a resistive component, a capacitive component, an inductive component, or the like. If the timing circuit 66 includes the capacitive component, the timing circuit 66 may include a discharge circuit to discharge the capacitive element before a different workpiece is electroplated. In another embodiment, the timing circuit 66 may not be used.

The lower conduction path includes an AC signal source 68. The lower conduction path is used during most of the electroplating.

Attention is now directed to details regarding the electroplating process. Before the workpiece 40 contacts the electroplating solution 59, the workpiece 40 is oriented to an angle different from a plane defined by the lip of the cup 52 and is rotated to reduce the likelihood that a bubble with form within the opening 38 of the workpiece 40). In one embodiment, the angle (as measured from a horizontal plane as seen in FIG. 5) is no greater than 4 degrees or at no greater than 2.9 degrees, and in another embodiment the angle is at least 1.1 degrees or at least 2.2 degrees.

The rotational speed can be high enough to reduce the likelihood of bubble formation, but not so high as to cause splashing or other turbulent or eddy effects. In one embodiment, the rotational speed is no greater than 150 revolutions per minute (“rpm”), or no greater than 90 rpm, and in another embodiment, the rotational speed is at least 50 rpm or at least 60 rpm.

The vertical entry speed can be as high as reasonable possible without causing splashing, eddy or other turbulent effects. In one embodiment, the vertical entry speed is at no greater than 50 mm/s or no greater than 25 mm/s, and in another embodiment, the vertical entry speed is at least 1 mm/s or at least 5 mm/s.

The workpiece 40 contacts the electroplating solution 49 when the electroplating occurs. In one embodiment, the workpiece 40 is adjusted so that angle is approximately 0 degrees during most of the electroplating. The workpiece 40 is typically submerged within the electroplating solution 49. The workpiece 40 does not contact the anodes 541, 542, and 543 during electroplating, and thus the workpiece 40 is spaced apart from the anodes 541, 542, and 543. If the workpiece 40 is submerged too far, material may start to plate the backside of the workpiece 40, which is undesired. In a particular embodiment, the workpiece 40 can be submerged such that it is approximately 7 mm to approximately 9 mm below a meniscus of the electroplating solution 49 (near the top of the cup 52).

In a particular, non-limiting embodiment, the angle can be approximately 2.6 degrees, the rotational speed can be approximately 75 rpm, the vertical entry speed can be approximately 15 mm/s, and the workpiece 40 is submerged approximately 8 mm below the meniscus of the plating solution. After reading this specification, skilled artisans will be able to determine particular entry parameters that meet their needs or desires.

Electroplating is performed during two different portions that use different types of signals. In one embodiment, the first portion is performed using a DC signal, and the second portion is performed using an AC signal. The first portion is schematically depicted in FIG. 7 to form a lower portion 72 of a conductive layer, and the second portion is schematically depicted in FIG. 8 to form an upper portion 82 of the conductive layer. The combination of anodes 541, 542, and 543 are depicted an electrode 70, and the upper conduction path (in FIG. 6) is depicted as a battery 74, and the lower conduction path (in FIG. 6) is depicted as an alternator 84 to simplify understanding, even though the actual implementation may be more complicated.

Referring to FIGS. 5 and 6, the controller 58 activates the switches 62 so that the upper conduction path in the control circuit 60 is active. The first portion of the electroplating includes an initial section and a primary section. The primary section is current controlled, and the initial section is to transition as quick as reasonably possible to the primary section. The initial section is to allow a transition to the current control portion and to limit the voltage and current flowing between the anodes 541, 542, and 543 and the clamp ring 552. In one embodiment, the voltage difference between the clamp ring 552 and each of the anodes 541, 542, and 543 is no greater than 4 V or no greater than 3V, and in another embodiment is at least 0.5V or at least 1 V. The initial section lasts for no greater than 2 seconds. The DC signal source 64, the timing circuit 66, or both can be used to control the voltage, time, or both during the initial section. In a particular embodiment, the control circuit 60 can include a resistive element, a capacitive element, an inductive element, or any combination therefore to substantially reduce the likelihood of a significant electrostatic shock when the workpiece 40 contacts the electroplating solution 59. In a particular embodiment, an inductor-capacitor (“LC”) circuit can be used to allow the current flowing between the clamp ring 522 and any anode or all of the anodes 541, 542, and 543 to increase current in a controlled manner during the initial section.

During the primary section, the electroplating is current controlled. The voltage is allowed to vary during the primary section. Lower and upper theoretical limits for the current flux (current per area of the substrate, from a top view) are unknown. Practical limitations, such as the current limit of the electroplating tool, may affect the current used. In one embodiment, the current per unit area is no greater than 20 mA/cm² or no greater than 15 mA/cm², and in another embodiment, the current per unit area is at least 2 mA/cm² or at least 4 mA/cm². As the current decreases, the time period for the primary section may be longer, and as the current increases, the time period for the primary section may be shorter.

In an alternative embodiment, charge per unit area (product of current per unit area times the time period of the primary section, initial section, or both) may be monitored. In one embodiment, the charge per unit area is no greater than 0.09 coulombs/cm² or less than 0.07 coulombs/cm², and in another embodiment, the charge per unit area is at least 0.03 coulombs/cm² or at least 0.04 coulombs/cm².

In a particular, non-limiting embodiment, the initial section can be performed with a voltage difference between the clamp ring 552 and each of the anodes 541, 542, and 542 is approximately 2 volts for a time period of no greater than 2 seconds, and the primary section is performed at a current per unit area of approximately 10 mA/cm² and a charge per unit area of approximately 0.05 coulombs/cm². After reading this specification, skilled artisans will appreciate that these or other parameters may be used to meet the needs or desires for a particular application. At the end of the first portion of the electroplating operation, a lower portion 72 of the conductive layer has been formed, as illustrated in FIG. 7. The lower portion 72 of the conductive layer does not completely fill the opening 38. In one embodiment, the lower portion 72 has a thickness of no greater than 150 nm or no greater than 80 nm, and in another embodiment, the lower portion has a thickness of at least 20 nm or at least 30 nm.

The second portion of the electroplating is performed to form the upper portion 82 of the conductive layer, as illustrated in FIG. 8. The upper portion 82 fills the remainder of the opening 38. The second portion can be performed using an AC signal. Referring briefly to FIG. 6, the switches 62 in the control circuit 60 can be changed to deactivate the upper conduction path and activate the lower conduction path. Thus, the AC signal source 68 can now be active and produce the AC signal. The AC signal can be in the form of pulses, a sinusoidal waveform, another suitable polarity changing function, or any combination thereof The second portion can be current controlled. In one particular embodiment, forward biased pulses and reversed bias pulses can be used. During forward biasing, each of the anodes 541, 542, and 543 is at a higher potential than the clamped ring 552, and thus, copper is electroplated onto the workpiece 40. During reverse biasing, each of the anodes 541, 542, and 543 is at a lower potential than the clamp ring 552, and thus, copper is deplated (removed) from the workpiece 40. More copper is electroplated during forward biasing as compared to the amount of copper removed during reverse biasing. Thus, the absolute value of the cumulative charge during forward biasing is greater than the absolute value of the cumulative charge during reverse biasing. In this manner, the net effect of one cycle is to thicken the conductive layer.

During formation of the upper portion 82 of the conductive layer, the thickness of the upper portion 82 is a function of the charge during forward biasing minus the charge during reverse biasing or

t_UP=f(Q_f−Q_r),

wherein t_UP is the thickness of the upper portion 82, Q_f is the charge during forward biasing (product of current and time), and Q_r is the charge during reverse biasing (product of current and time).

If the current per unit area during forward biasing is too high, the opening 38 may not fill properly (e.g., from the bottom of the opening 38). In one embodiment, the current per unit area during forward biasing is no greater than 50 mA/cm2 or no greater than 40 mA/cm2, and in another embodiment, the current per unit area is at least 1.5 mA/cm2 or at least 11 mA/cm2. The time period for each pulse during forward biasing may be no greater than 900 ms or no greater than 200 ms, and in another embodiment, the time period of at least 30 ms or at least 50 ms. In a particular embodiment, a ratio of the forward bias current to the reverse bias current is in a range of approximately 1.3 to 1.7. In one embodiment, the current per unit area during reverse biasing is no greater than 33 mA/cm2 or no greater than 20 mA/cm2, and in another embodiment, the current per unit area is at least 1.1 mA/cm2 or at least 11 mA/cm2. The time period for each pulse during forward biasing may be no greater than 500 ms or no greater than 200 ms, and in another embodiment, the time period of at least 10 ms or at least 15 ms.

Between each of the forward bias pulses and the reverse bias pulses, no current flows between the clamp ring 522 and each of the anodes 541, 542, and 543, and is referred herein as an off pulse. No theoretical limits on the off pulses are known; however, the material throughput can be adversely affected if the off pulses are too long. In one embodiment, the time period for the off pulse in no greater than 500 ms or no greater than 90 ms, and in another embodiment, the time period is at least 0.5 ms or at least 2 ms.

FIG. 9 illustrates a cross-sectional view of the workpiece 40, including the lower portion 72 and the upper portion 82 after electroplating has been completed. The exposed surface of the upper portion 82 may or may not have a substantially planar surface.

FIG. 10 includes an illustration of a cross-sectional view of the workpiece 40 after parts of the upper portion 82 and the lower portion 72 of the conductive layer, the seed layer 44, and the barrier layer 42 overlying the insulating layer 34 and lying outside the opening 36 have been removed. The removal can be performed by chemical-mechanical polishing, etching, or any combination thereof In one particular embodiment, the upper portion 82 and the lower portion 72 of the conductive layer and the seed layer 44 all principally include copper can be removed by the same chemical-mechanical polishing operation. The barrier layer 42 can be removed using a different chemical-mechanical polishing operation (e.g., different polishing pad, different polishing slurry, different downforce pressure, etc.) or using plasma etching (e.g., reactive ion etching). The removal of the upper portion 82 and the lower portion 72 of the conductive layer, the seed layer 44, and the barrier layer 42 overlying the insulating layer 34 and lying outside the opening 36 can be performed using a conventional or proprietary operation, and such operation may or may not include endpoint detection.

Processing of the workpiece 40 can be continued to form a substantially completed electronic device. In one embodiment (not illustrated), additional insulating and conductive layers can be formed and patterned to form one or more additional levels of interconnects. After the last interconnect level has been formed, an encapsulating layer is formed. The encapsulating layer can include an oxide, a nitride, an oxynitride, or a combination thereof. The encapsulating layer can include a single insulating film or a plurality of insulating films. The thickness and deposition of the encapsulating layer can be conventional or proprietary.

FIG. 11 includes an illustration of a system 1 16. The system 116 includes the electronic device 112 formed by the process described herein. In one embodiment, the electronic device 112 can be an integrated circuit that may include memory cells, such as nonvolatile memory cells, random access memory cells, other suitable memory cells, or any combination thereof. The electronic device 112 can be part of a standalone memory integrated circuit or may be part of a different type of integrated circuit.

The system 116 also includes a processor 114 that is coupled to a display 118 and the electronic device 112. The processor 114 can include a central processing unit, a graphical processing unit, another suitable processing unit, or any combination thereof. The processor 114 may be part of a microcontroller, a microprocessor, a digital signal processor, another suitable data processing integrated circuit or the like. The processor 114 and the electronic device 112 can be separate integrated circuits mounted on the same or different printed wiring boards. In another embodiment, the processor 114 and the electronic device 112 may reside within the same integrated circuit. In one specific embodiment, the processor 114 can read data from the electronic device 112 and render or otherwise provide information to be displayed on the display 118 of the system 116.

Embodiments as described herein can be used to electroplate a material by using a simpler electroplating chemistry without adverse consequences that can occur when using the simpler electroplating chemistry. The second portion of the electroplating can be performed using an AC signal, and therefore, a leveler, which is typically used with electroplating using only a DC signal, is not required. Problems with thinning the seed layer 44, particularly along the sidewall of the opening 38 can be avoided because a first portion of the electroplating is performed using a DC signal, rather than using only an AC signal when electroplating the entire conductive layer. Thus, the first portion using the DC signal can deposit a significant portion of material along the sidewall, such that during the second portion, the AC signal may remove a part of the lower portion of the conductive layer, but will not remove a significant part of the seed layer 44.

The processes herein can be used to form a conductive layer that does not form a mound over or a void within an opening. Thus, polishing may be simplified, and reliability can be improved.

The embodiments can be implement using an existing electroplating tool, and therefore, does not require any capital investment. Additionally, the processes described herein can be implemented without any significant reduction in electroplating capacity. The processes may be implemented by changes in software. Some of the values of parameters can be scaled for different sizes of substrate.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are only illustrative and do not limit the scope of the present invention.

In a first aspect, a process of forming an electronic device can include placing a seed layer overlying a substrate into an electroplating solution within an electroplating tool, wherein a first electrode of the electroplating tool is electrically connected to the seed layer, and a second electrode of the electroplating tool is in disposed within the electroplating solution. The process can also include depositing a first portion of a conductive layer over the seed layer, wherein depositing the first portion is performed using a first signal of a first type between the first electrode and a second electrode. The process can further include depositing a second portion of the conductive layer over the first portion of the conductive layer, wherein depositing the second portion is performed using a second signal of a second type between the first electrode and the second electrode of the electroplating tool, and wherein the second signal type is different from the first signal type.

In one embodiment of the first aspect, the process further includes forming the seed layer over the substrate, wherein the substrate includes an electronic component and an insulating layer over the electronic component, and wherein the insulating layer includes an opening extending therethrough. The process still further includes forming the seed layer includes depositing the seed layer over the insulating layer and within the opening, such that the seed layer is electrically connected to the electronic component, and only a portion of the opening is filled with the seed layer. In a particular embodiment, the process further includes forming a barrier layer before forming the seed layer, wherein after forming the seed layer, a width of the opening in the insulating layer is no greater than approximately 20 times the combined thickness of the barrier layer and the seed layer, as measured over the insulating layer.

In another embodiment of the first aspect, the first signal type is direct current, and the second signal type is alternating current. In a particular embodiment, during depositing the first portion of the conductive layer, the current flow is not greater than approximately 14 milliamps per square centimeter of substrate area from a top view of the substrate. In still another embodiment placing the seed layer overlying the substrate into the electroplating solution includes lowering the seed layer and the substrate into the electroplating solution such that the substrate is a range of approximately 7 mm to approximately 9 mm below a meniscus of the electroplating solution. In yet another embodiment, the process further includes applying a potential difference between the first electrode and the second electrode before placing the seed layer into the electroplating solution, wherein the potential difference is not greater than approximately 4 volts.

In a further embodiment of the first aspect, depositing the first portion of the conductive layer ends after not greater than approximately 0.07 coulombs per square centimeter of substrate area, as seen from a top view of the substrate, flows between the first electrode and the second electrode. In still a further embodiment, the electroplating solution includes a disulfide compound, a polyethylene glycol compound, and substantially no amine compound. In yet a further embodiment, the second electrode includes a plurality of second anodes, and each anode of the plurality of second anodes is independently controlled from each other.

In a second aspect, a process of forming electronic device can include electrically connecting a first electrode of an electroplating tool and a seed layer overlying a semiconductor substrate to each other, and applying a potential difference as a direct current signal between the first electrode and a second electrode of the electroplating tool, wherein the second electrode is spaced apart from the first electrode and the seed layer, is disposed within an electroplating solution of the electroplating tool, and the electroplating solution includes substantially no amine. The process can also include placing the seed layer into an electroplating solution after applying the potential difference between the first electrode and the second electrode. The process can further include depositing a first portion of a conductive layer over the seed layer, wherein depositing the first portion ends after not greater than approximately 0.07 coulombs per square centimeter of substrate area, from a top view of the substrate, flows from the first electrode to the second electrode. The process can still further include depositing a second portion of the conductive layer over the first portion of the conductive layer, wherein depositing the second portion is performed using an alternating current signal between the first electrode and the second electrode.

In one embodiment of the second aspect, the process of claim 11, further includes forming an insulating layer over the substrate, forming an opening in the insulating layer to expose a conductive structure, wherein the opening has an aspect ratio greater than one, and forming the seed layer over the insulating layer and within the opening of the insulating layer before electrically connecting the first electrode of the electroplating tool and the seed layer. In a particular embodiment, the process further includes forming a barrier layer over the conductive structure before forming the seed layer. In another particular embodiment, the opening in the insulating layer has a width no greater than approximately 130 nm.

In still another embodiment of the second aspect, placing the seed layer in contact with the electroplating solution is performed such that the electroplating solution includes a suppressor and an accelerator. In a particular embodiment, the suppressor includes a polyethylene glycol compound, and the accelerator includes a disulfide compound. In yet another embodiment, applying the potential difference is performed such that the voltage difference of no greater than approximately 4 volts.

In a further embodiment of the second aspect, the process further includes increasing a current flowing between the first electrode and the second electrode during placing the seed layer into the electroplating solution, during depositing a first portion of a conductive layer over the seed layer, or both. In still a further embodiment, the semiconductor substrate includes an electronic component and, after depositing the first and the second portions of the conductive layer, the conductive layer is electrically coupled to the electronic component. In yet a further embodiment, placing the seed layer into an electroplating solution includes submerging the semiconductor substrate into the electroplating solution, such that the semiconductor substrate is approximately 7 mm to approximately 9 mm below a meniscus of the electroplating solution.

Note that not all of the activities described above in the general description or the examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed.

In the foregoing specification, the concepts have been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of invention.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims.

After reading the specification, skilled artisans will appreciated that certain features are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, references to values stated in ranges include each and every value within that range.

Claims

1. A process of forming an electronic device comprising:

placing a seed layer overlying a substrate into an electroplating solution within an electroplating tool;

depositing a first portion of a conductive layer over the seed layer, wherein depositing the first portion is performed using a first signal of a first type while the substrate is within the electroplating tool; and

depositing a second portion of the conductive layer over the first portion of the conductive layer, wherein depositing the second portion is performed using a second signal of a second type while the substrate is within the electroplating tool, and wherein the second signal type is different from the first signal type.

2. The process of claim 1, further comprising forming the seed layer over the substrate, wherein:

the substrate includes an electronic component and an insulating layer over the electronic component, wherein the insulating layer includes an opening extending therethrough; and

forming the seed layer comprises depositing the seed layer over the insulating layer and within the opening, such that the seed layer is electrically connected to the electronic component, and only a portion of the opening is filled with the seed layer.

3. The process of claim 2, further comprising forming a barrier layer before forming the seed layer, wherein after forming the seed layer, a width of the opening in the insulating layer is no greater than approximately 20 times the combined thickness of the barrier layer and the seed layer, as measured over the insulating layer.

4. The process of claim 1, wherein the first signal type is direct current, and the second signal type is alternating current.

5. The process of claim 4, wherein during depositing the first portion of the conductive layer, the current flow is not greater than approximately 14 milliamps per square centimeter of substrate area from a top view of the substrate.

6. The process of claim 1, wherein placing the seed layer overlying the substrate into the electroplating solution comprises lowering the seed layer and the substrate into the electroplating solution such that the substrate is a range of approximately 7 mm to approximately 9 mm below a meniscus of the electroplating solution.

7. The process of claim 1, further comprising:

electrically connecting to the seed layer to a first electrode of the electroplating tool that is spaced apart from a second electrode of the electroplating tool; and

applying a potential difference between the first electrode and the second electrode before placing the seed layer into the electroplating solution, wherein the potential difference is not greater than approximately 4 volts.

8. The process of claim 1, wherein:

the process further comprises electrically connecting to the seed layer to a first electrode of the electroplating tool that is spaced apart from a second electrode of the electroplating tool; and

depositing the first portion of the conductive layer ends after not greater than approximately 0.07 coulombs per square centimeter of substrate area, as seen from a top view of the substrate, flows between the first electrode and the second electrode.

9. The process of claim 1, wherein the electroplating solution includes a disulfide compound, a polyethylene glycol compound, and substantially no amine compound.

10. The process of claim 1, further comprising electrically connecting to the seed layer to a first electrode of the electroplating tool that is spaced apart from a second electrode of the electroplating tool, wherein the second electrode includes a plurality of second anodes, and each anode of the plurality of second anodes is independently controlled from each other.

11. A process of forming electronic device comprising:

electrically connecting a first electrode of an electroplating tool and a seed layer overlying a semiconductor substrate to each other;

applying a potential difference as a direct current signal between the first electrode and a second electrode of the electroplating tool, wherein the second electrode is spaced apart from the first electrode and the seed layer, is disposed within an electroplating solution of the electroplating tool, and the electroplating solution includes substantially no amine;

placing the seed layer into an electroplating solution after applying the potential difference between the first electrode and the second electrode;

depositing a first portion of a conductive layer over the seed layer, wherein depositing the first portion ends after not greater than approximately 0.07 coulombs per square centimeter of substrate area, from a top view of the substrate, flows from the first electrode to the second electrode; and

depositing a second portion of the conductive layer over the first portion of the conductive layer, wherein depositing the second portion is performed using an alternating current signal between the first electrode and the second electrode.

12. The process of claim 11, further comprising:

forming an insulating layer over the substrate;

forming an opening in the insulating layer to expose a conductive structure, wherein the opening has an aspect ratio greater than one; and

forming the seed layer over the insulating layer and within the opening of the insulating layer before electrically connecting the first electrode of the electroplating tool and the seed layer.

13. The process of claim 12, further including forming a barrier layer over the conductive structure before forming the seed layer.

14. The process of claim 12, wherein the opening in the insulating layer has a width no greater than approximately 130 nm.

15. The process of claim 11, wherein placing the seed layer in contact with the electroplating solution is performed such that the electroplating solution includes a suppressor and an accelerator.

16. The process of claim 15, wherein the suppressor includes a polyethylene glycol compound, and the accelerator includes a disulfide compound.

17. The process of claim 11, wherein applying the potential difference is performed such that the voltage difference of no greater than approximately 4 volts.

18. The process of claim 11, further comprising increasing a current flowing between the first electrode and the second electrode during placing the seed layer into the electroplating solution, during depositing a first portion of a conductive layer over the seed layer, or both.

19. The process of claim 11, wherein the semiconductor substrate includes an electronic component and, after depositing the first and the second portions of the conductive layer, the conductive layer is electrically coupled to the electronic component.

20. The process of claim 11, wherein placing the seed layer into an electroplating solution comprises submerging the semiconductor substrate into the electroplating solution, such that the semiconductor substrate is approximately 7 mm to approximately 9 mm below a meniscus of the electroplating solution.