Anti-fuse Patents (Class 257/530)
  • Patent number: 10896894
    Abstract: Methods of fabricating semiconductor device packages may involve forming trenches in a first wafer. A dielectric material may be placed over a first active surface. Electrically conductive elements may be operatively connected to bond pads of a second wafer with the dielectric material interposed between the first wafer and the second wafer. Force may be applied to the first wafer and the second wafer while exposing the first wafer and the second wafer to an elevated temperature. Portions of the dielectric material may flow into the trenches. The elevated temperature may be reduced to at least partially solidify the dielectric material. A thickness of the first wafer may be reduced to reveal the portions of the dielectric material in the trenches. The first wager may be singulated and the second wafer may be singulated to form semiconductor dice.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Wei Zhou
  • Patent number: 10886417
    Abstract: Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCl) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCl stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Kuan-Yueh Shen, Rachael Parker, Stephen Ramey
  • Patent number: 10797053
    Abstract: Examples relate generally to the field of semiconductor memory devices. In an example, a memory cell may include an access device coupled to an access line and a gated diode coupled to the access device. The gated diode may include a gate stack structure that includes a direct tunneling material, a trapping material, and a blocking material.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: October 6, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 10763210
    Abstract: An antifuse structure having enhanced programming efficiency is provided in which there is limited contact between the antifuse material and top and bottom electrodes. The antifuse material has a circular ring shape (i.e., donate shape having a hole in the middle (center) thereof) in which a dielectric material structure composed of a dielectric material having a dielectric constant of great than 4.0 is contained in the hole of the circular ring shaped antifuse material. The antifuse material is composed of a dielectric material having a lower dielectric breakdown strength as compared to the dielectric material structure.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 1, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Baozhen Li
  • Patent number: 10720389
    Abstract: An anti-fuse structure includes an active area, a gate electrode over the active area, and a dielectric layer between the active area and the gate electrode. The active area and the gate electrode partially overlap in a vertical projection direction, forming a plurality of channels. One of the gate electrode and the active area includes a plurality of extending portions to form the plurality of channels.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: July 21, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Chang, Jui-Hsiu Jao
  • Patent number: 10720457
    Abstract: An imaging device includes a pixel comprising a photoelectric conversion layer having a first surface and a second surface opposite to the first surface; a pixel electrode on the first surface; an auxiliary electrode on the first surface, the auxiliary electrode being spaced from the pixel electrode; an upper electrode on the second surface, the upper electrode facing the pixel electrode and the auxiliary electrode; and an amplification transistor having a gate coupled to the pixel electrode. The imaging device also includes voltage application circuitry that generates a first voltage and a second voltage different from the first voltage, the voltage application circuitry being coupled to the auxiliary electrode. The voltage application circuitry selectively supplies either the first voltage or the second voltage to the auxiliary electrode.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 21, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masayuki Takase, Takayoshi Yamada, Tokuhiko Tamaki
  • Patent number: 10680006
    Abstract: Various embodiments, disclosed herein, include methods and apparatus having charge trap structures, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, material of the dielectric barrier of each of the charge trap structures may have a dielectric constant greater than that of aluminum oxide. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chris M Carlson
  • Patent number: 10664239
    Abstract: A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: May 26, 2020
    Assignee: eMemory Technology Inc.
    Inventors: Kuan-Hsun Chen, Chun-Hung Lu, Ming-Shan Lo
  • Patent number: 10644021
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 5, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Thomas H. Lee, Igor G. Kouznetsov
  • Patent number: 10629540
    Abstract: In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant 129. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hui-Jung Tsai, Hung-Jui Kuo, Chung-Shi Liu, Han-Ping Pu, Ting-Chu Ko
  • Patent number: 10593875
    Abstract: A plurality of memory cells in a cross-point array in which the memory cell stacks in the cross-points include a switch element, a conductive barrier layer, and a memory cell in series, and having sides aligned within the cross-point area of the corresponding cross-point. The memory cells in the stacks include confinement spacers within the cross-point area having outside surfaces on a pair of opposing sides of the stack, and a body of programmable resistance memory material confined between inside surfaces of the spacers.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Erh-Kun Lai, Hsiang-Lan Lung
  • Patent number: 10566253
    Abstract: An electronic device includes a substrate, an electronic component disposed over the substrate and an electrical testing component disposed over the substrate. The electronic component includes a bottom plate over the substrate, and a top plate over the bottom plate. The electrical testing component includes a first anti-fuse structure and a second anti-fuse structure, wherein the first anti-fuse structure and the second anti-fuse structure are electrically connected to the bottom plate.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: February 18, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Ying Chang, Jui-Hsiu Jao
  • Patent number: 10559530
    Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
  • Patent number: 10529436
    Abstract: A one-time programmable memory device includes a first doped region in a semiconductor substrate, a second doped region implanted within the first doped region, and a gate positioned over the second doped region. The first doped region and second doped regions form a diode. A first contact is coupled to the first doped region for applying a voltage to the first doped region. The gate includes a dielectric portion that is capacitively coupled to the second doped region. The gate also includes a conductive portion that is coupled to a second contact for applying a voltage to the conductive portion. The voltage applied to the conductive portion is independent from the voltage applied to the first doped region. The memory device is programmed by forming a rupture in the dielectric portion of the gate.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: January 7, 2020
    Assignee: Synopsys, Inc.
    Inventors: Hrant Sargsyan, Andrew E. Horch
  • Patent number: 10504907
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 10, 2019
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10490374
    Abstract: One embodiment of the invention includes a phase-change material switch. The switch includes a first terminal that receives an input signal and a second terminal. The switch includes an actuation portion that receives a control signal in one of a first state to emit a first heat profile and a second state to emit a second heat profile. The switch further includes a switch portion comprising a phase-change material arranged as a plurality of longitudinal strips that each interconnect the first terminal and the second terminal and that are each in proximity with the actuation portion. The phase-change material can be selectable between a conducting state in response to the first heat profile to conduct an input signal from the first terminal to the second terminal and a blocking state in response to the second heat profile to block the input signal from the first terminal to the second terminal.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 26, 2019
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Pavel Borodulin, Nabil Abdel-Meguid El-Hinnawy, Robert Miles Young, Matthew Russell King, Michael J. Lee
  • Patent number: 10491787
    Abstract: Various techniques are provided to facilitate electrostatic discharge mitigation for imaging devices. In one example, an imaging device includes an imager assembly. The imaging device further includes a lens holder. The lens holder includes a receiving interface configured to receive a lens assembly therein. The lens holder further includes an alignment pin including electrically conductive material and coupled to the imager assembly to provide an electrostatic discharge path via the imager assembly, where a first portion of the alignment pin has the electrically conductive material exposed and a second portion of the alignment pin has an insulating layer disposed thereon. Related methods and systems are also provided.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: November 26, 2019
    Assignee: FLIR Systems, Inc.
    Inventors: Mark V. Mullenary, Thad Lieb, Bruce A. Covington
  • Patent number: 10347619
    Abstract: Disclosed is a semiconductor device having an electrostatic discharge protection structure. The electrostatic discharge protection structure is a diode connected between a gate electrode and a source electrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate electrode and the source electrode. Lower parts of the two connection portions are respectively provided with a trench. An insulation layer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insulation layer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a metal conductor layer is provided on the dielectric layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: July 9, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Kui Xiao
  • Patent number: 10319908
    Abstract: Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 11, 2019
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Steve Maxwell, Natividad Vasquez, Jr., Harry Yue Gee
  • Patent number: 10304841
    Abstract: Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang
  • Patent number: 10224278
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamamoto, Osamu Takata, Mariko Habu, Shinji Kawahara
  • Patent number: 10212827
    Abstract: Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: John J. Browne, Andrew Maclean, Shawna M. Liff
  • Patent number: 10163520
    Abstract: An integrated circuit OTP memory cell has a programming element with enhanced programmability. The programming element has a doped region at the surface of a semiconductor substrate and a conducting layer partially extending over a surface of the semiconductor surface and along a boundary of the doped region. The conducting layer is displaced from the surface of the doped region and the semiconductor substrate by a thin oxide layer. The partially extending conducting layer provides locations to concentrate electric fields and rupture the gate oxide layer during programming.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 25, 2018
    Assignee: Synopsys, Inc.
    Inventors: Chun Jian, Larry Wang
  • Patent number: 10160639
    Abstract: The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
  • Patent number: 10163526
    Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric D. Hunt-Schroeder, Darren L. Anand
  • Patent number: 10147720
    Abstract: A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 4, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunari Fujii, Toshio Negishi
  • Patent number: 10128184
    Abstract: An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 13, 2018
    Assignee: Zhuhai Chuangfeixin Technology Co., Ltd.
    Inventors: Li Li, Zhigang Wang
  • Patent number: 10109364
    Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jonathan A. Schmitt, Jermyn Tseng
  • Patent number: 10090463
    Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 2, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 10043786
    Abstract: A Zener diode used as an ESD protection element is connected in parallel to a circuit to be protected, for example an LED chip. The Zener diode is connected in parallel to an antifuse element. For example, an LED package (P1-Pn) includes the LED chip and a composite protection element connected in parallel thereto. The composite protection element includes the Zener diode and antifuse element. The Zener diode is formed in a semiconductor substrate, and the antifuse element is formed in a wiring layer on the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 7, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Nobuo Sakai
  • Patent number: 10008507
    Abstract: Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang
  • Patent number: 9997494
    Abstract: Embodiments of a three-dimensional silicon structure for integrated circuits and cooling thereof are described. In one aspect, a device includes a silicon substrate having a first primary side and a second primary side opposite the first primary side. The first primary side includes a circuit structure disposed thereon. The second primary side includes a plurality of fins monolithically formed thereon.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: June 12, 2018
    Inventor: Gerald Ho Kim
  • Patent number: 9953990
    Abstract: Embodiments relate to an anti-fuse device with a transistor. The transistor may be a FinFET. The anti-fuse device includes a first electrode, an insulating layer, and a second electrode. The gate of the transistor may be formed in a same layer as the first electrode. The gate insulating layer on the gate of the transistor may be formed in a same layer as the insulating layer. The second electrode may be formed in a same layer as a local interconnect or a via and overlap the first electrode vertically over the insulating layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Synopsys, Inc.
    Inventors: Andrew E. Horch, Victor Moroz, Jamil Kawa
  • Patent number: 9922723
    Abstract: A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: March 20, 2018
    Assignee: NXP USA, Inc.
    Inventor: Anirban Roy
  • Patent number: 9916903
    Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal, Min-hwa Chi
  • Patent number: 9754877
    Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Takahashi, Hitoshi Matsuura
  • Patent number: 9746730
    Abstract: An array substrate having a data line self-repairing function and a liquid crystal display device is disclosed. The array substrate comprises a plurality of pixel units, the pixel unit at least comprise a gate layer, a gate insulating layer, a data layer and a pixel electrode layer laminated therein. Every of the pixel unit have a translucent area and opening areas. The gate layer relative to the opening area is retained, and the gate insulating layer does not cover the gate layer, and the data layer relative to the opening area contacts with the gate layer so that a broken data line in the data layer has conductive connection through the gate layer. Through the above solution, the data line has automatic repair function for disconnection and the unqualified rate of the data line during the manufacture processes is reduced.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 29, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Meng Wang
  • Patent number: 9691497
    Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Min-hwa Chi, Ajey P. Jacob
  • Patent number: 9633943
    Abstract: A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9628086
    Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 18, 2017
    Assignee: Case Western Reserve University
    Inventors: Ting He, Fengchao Zhang, Swarup Bhunia, Philip X. -L. Feng
  • Patent number: 9613881
    Abstract: A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Heui Gyun Ahn, Sang Wook Ahn, Yong Woon Lee, Huy Chan Jung, Sung Chun Jun
  • Patent number: 9564417
    Abstract: A multi-stacked structure of semiconductor packages includes a plurality of substrates stacked in a vertical direction, semiconductor packages mounted on each substrate of the plurality of the substrates, a heat release column extending commonly through the plurality of the substrates and overlapping at least one semiconductor package serving as a heat generation source among the semiconductor packages in the vertical direction, and a heat dissipation part thermally connected to one end of the heat release column.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Bum Byun, Cheol Kwon, Jong-Yun Yun, Do-Il Kong, Sung-Chul Hur
  • Patent number: 9559110
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Thomas H. Lee
  • Patent number: 9530460
    Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 27, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ren Chen, Wen-Hao Lee
  • Patent number: 9490259
    Abstract: An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yong Sun Jung
  • Patent number: 9384995
    Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Fatma Arzum Simsek-Ege, Krishna K Parat
  • Patent number: 9368567
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 9349686
    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Mojumder, Mustafa Badaroglu
  • Patent number: 9312306
    Abstract: According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Nakakubo, Shigeki Kobayashi, Takeshi Yamaguchi
  • Patent number: 9293357
    Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Takehito Tamura