Anti-fuse Patents (Class 257/530)
  • Patent number: 10347619
    Abstract: Disclosed is a semiconductor device having an electrostatic discharge protection structure. The electrostatic discharge protection structure is a diode connected between a gate electrode and a source electrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate electrode and the source electrode. Lower parts of the two connection portions are respectively provided with a trench. An insulation layer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insulation layer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a metal conductor layer is provided on the dielectric layer.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: July 9, 2019
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventor: Kui Xiao
  • Patent number: 10319908
    Abstract: Providing for a memory device having a resistive switching memory integrated within backend layers of the memory device is described herein. By way of example, the resistive switching memory can be embedded memory such as cache, random access memory, or the like, in various embodiments. The resistive memory can be fabricated between various backend metallization schemes, including backend copper metal layers and in part utilizing one or more damascene processes. In some embodiments, the resistive memory can be fabricated in part with damascene processes and in part with subtractive etch processing, utilizing four or fewer photo-resist masks. Accordingly, the disclosure provides a relatively low cost, high performance embedded memory compatible with a variety of fabrication processes of integrated circuit foundries.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 11, 2019
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Steve Maxwell, Natividad Vasquez, Jr., Harry Yue Gee
  • Patent number: 10304841
    Abstract: Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang
  • Patent number: 10224278
    Abstract: A semiconductor device includes a semiconductor substrate comprising an upper layer portion, a first insulating member located in the upper layer portion of the semiconductor substrate and having one or more corner portions, an electrode located on the semiconductor substrate, wherein the electrode overlies at least one of the corner portions of the first insulating member, and an insulating film located between the semiconductor substrate and the electrode.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Yamamoto, Osamu Takata, Mariko Habu, Shinji Kawahara
  • Patent number: 10212827
    Abstract: Techniques and mechanisms for controlling configurable circuitry including an antifuse. In an embodiment, the antifuse is disposed in or on a substrate, the antifuse configured to form a solder joint to facilitate interconnection of circuit components. Control circuitry to operate with the antifuse is disposed in, or at a side of, the same substrate. The antifuse is activated based on a voltage provided at an input node, where the control circuitry automatically transitions through a pre-determined sequence of states in response to the voltage. The pre-determined sequence of states coordinates activation of one or more fuses and switched coupling one or more circuit components to the antifuse. In another embodiment, multiple antifuses, variously disposed in or on the substrate, are configured each to be activated based on the voltage provided at an input node.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventors: John J. Browne, Andrew Maclean, Shawna M. Liff
  • Patent number: 10163520
    Abstract: An integrated circuit OTP memory cell has a programming element with enhanced programmability. The programming element has a doped region at the surface of a semiconductor substrate and a conducting layer partially extending over a surface of the semiconductor surface and along a boundary of the doped region. The conducting layer is displaced from the surface of the doped region and the semiconductor substrate by a thin oxide layer. The partially extending conducting layer provides locations to concentrate electric fields and rupture the gate oxide layer during programming.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 25, 2018
    Assignee: Synopsys, Inc.
    Inventors: Chun Jian, Larry Wang
  • Patent number: 10160639
    Abstract: The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
  • Patent number: 10163526
    Abstract: The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric D. Hunt-Schroeder, Darren L. Anand
  • Patent number: 10147720
    Abstract: A semiconductor device includes a transistor connected to a terminal having a first potential, an anti-fuse element connected between the transistor and a terminal having a second potential different from the first potential, and a resistor element connected in parallel with the anti-fuse element. An electric path between the transistor and the anti-fuse element has a length smaller than a length of an electric path between the transistor and the resistor element.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: December 4, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunari Fujii, Toshio Negishi
  • Patent number: 10128184
    Abstract: An antifuse structure includes a first electrode layer, an inter-metal dielectric layer over the first electrode layer, and a via in the inter-metal dielectric layer. The via penetrates through the inter-metal dielectric layer exposing a portion of the first electrode layer. An antifuse layer is deposited in the via and over the portion of the first electrode layer. A second electrode is disposed in the via and over the antifuse layer. An interconnect layer may be deposited over the inter-metal dielectric layer and in electrical contact with the second electrode in the via.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: November 13, 2018
    Assignee: Zhuhai Chuangfeixin Technology Co., Ltd.
    Inventors: Li Li, Zhigang Wang
  • Patent number: 10109364
    Abstract: A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 23, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Jonathan A. Schmitt, Jermyn Tseng
  • Patent number: 10090463
    Abstract: Non-crystalline silicon non-volatile resistive switching devices include a metal electrode, a non-crystalline silicon layer and a planar doped silicon electrode. An electrical signal applied to the metal electrode drives metal ions from the metal electrode into the non-crystalline silicon layer to form a conducting filament from the metal electrode to the planar doped silicon electrode to alter a resistance of the non-crystalline silicon layer. Another electrical signal applied to the metal electrode removes at least some of the metal ions forming the conducting filament from the non-crystalline silicon layer to further alter the resistance of the non-crystalline silicon layer.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 2, 2018
    Assignee: The Regents of the University of Michigan
    Inventors: Wei Lu, Sung Hyun Jo
  • Patent number: 10043786
    Abstract: A Zener diode used as an ESD protection element is connected in parallel to a circuit to be protected, for example an LED chip. The Zener diode is connected in parallel to an antifuse element. For example, an LED package (P1-Pn) includes the LED chip and a composite protection element connected in parallel thereto. The composite protection element includes the Zener diode and antifuse element. The Zener diode is formed in a semiconductor substrate, and the antifuse element is formed in a wiring layer on the semiconductor substrate.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 7, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Nobuo Sakai
  • Patent number: 10008507
    Abstract: Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance FinFETs. The anti-fuse includes at least one metal structure having a faceted sidewall. The sharp corner of the faceted sidewall of the at least one metal structure causes an electric field concentration, thus reducing the breakdown voltage of the anti-fuse.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Miaomiao Wang, Chih-Chao Yang
  • Patent number: 9997494
    Abstract: Embodiments of a three-dimensional silicon structure for integrated circuits and cooling thereof are described. In one aspect, a device includes a silicon substrate having a first primary side and a second primary side opposite the first primary side. The first primary side includes a circuit structure disposed thereon. The second primary side includes a plurality of fins monolithically formed thereon.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: June 12, 2018
    Inventor: Gerald Ho Kim
  • Patent number: 9953990
    Abstract: Embodiments relate to an anti-fuse device with a transistor. The transistor may be a FinFET. The anti-fuse device includes a first electrode, an insulating layer, and a second electrode. The gate of the transistor may be formed in a same layer as the first electrode. The gate insulating layer on the gate of the transistor may be formed in a same layer as the insulating layer. The second electrode may be formed in a same layer as a local interconnect or a via and overlap the first electrode vertically over the insulating layer.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Synopsys, Inc.
    Inventors: Andrew E. Horch, Victor Moroz, Jamil Kawa
  • Patent number: 9922723
    Abstract: A one-time programmable (OTP) latch includes a memory cell having a first non-volatile (NV) resistive element and a second NV resistive element, cross-coupled inverter circuitry, a first transistor having a first current electrode coupled to a first node of the cross-coupled inverter circuitry and a second current electrode coupled to a first terminal of the first NV resistive element, and a second transistor having a first current electrode coupled to a second node of the cross-coupled inverter circuitry, different from the first node, and a second current electrode coupled to a first terminal of the second NV resistive element. The OTP latch also includes write circuitry coupled to the memory cell and configured to program only one of the first NV resistive element or the second NV resistive element to an OTP state while the cross-coupled inverter circuitry is isolated from the memory cell by the first and second transistors.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: March 20, 2018
    Assignee: NXP USA, Inc.
    Inventor: Anirban Roy
  • Patent number: 9916903
    Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: March 13, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal, Min-hwa Chi
  • Patent number: 9754877
    Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yukio Takahashi, Hitoshi Matsuura
  • Patent number: 9746730
    Abstract: An array substrate having a data line self-repairing function and a liquid crystal display device is disclosed. The array substrate comprises a plurality of pixel units, the pixel unit at least comprise a gate layer, a gate insulating layer, a data layer and a pixel electrode layer laminated therein. Every of the pixel unit have a translucent area and opening areas. The gate layer relative to the opening area is retained, and the gate insulating layer does not cover the gate layer, and the data layer relative to the opening area contacts with the gate layer so that a broken data line in the data layer has conductive connection through the gate layer. Through the above solution, the data line has automatic repair function for disconnection and the unqualified rate of the data line during the manufacture processes is reduced.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 29, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Meng Wang
  • Patent number: 9691497
    Abstract: Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 27, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. Patil, Min-hwa Chi, Ajey P. Jacob
  • Patent number: 9633943
    Abstract: A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9628086
    Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: April 18, 2017
    Assignee: Case Western Reserve University
    Inventors: Ting He, Fengchao Zhang, Swarup Bhunia, Philip X. -L. Feng
  • Patent number: 9613881
    Abstract: A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Heui Gyun Ahn, Sang Wook Ahn, Yong Woon Lee, Huy Chan Jung, Sung Chun Jun
  • Patent number: 9564417
    Abstract: A multi-stacked structure of semiconductor packages includes a plurality of substrates stacked in a vertical direction, semiconductor packages mounted on each substrate of the plurality of the substrates, a heat release column extending commonly through the plurality of the substrates and overlapping at least one semiconductor package serving as a heat generation source among the semiconductor packages in the vertical direction, and a heat dissipation part thermally connected to one end of the heat release column.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: February 7, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Bum Byun, Cheol Kwon, Jong-Yun Yun, Do-Il Kong, Sung-Chul Hur
  • Patent number: 9559110
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: January 31, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Thomas H. Lee
  • Patent number: 9530460
    Abstract: An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 27, 2016
    Assignee: EMEMORY TECHNOLOGY INC.
    Inventors: Wei-Ren Chen, Wen-Hao Lee
  • Patent number: 9490259
    Abstract: An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 8, 2016
    Assignee: SK Hynix Inc.
    Inventor: Yong Sun Jung
  • Patent number: 9384995
    Abstract: A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide is utilized as an etch-stop layer in place of a conventionally used aluminum oxide to form channel pillars having a high aspect ratio. Use of the tungsten salicide is useful for eliminating an undesired etch-stop recess and an undesired floating gate that is formed when an Al oxide etch-stop layer is conventionally used.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 5, 2016
    Assignee: Intel Corporation
    Inventors: Fatma Arzum Simsek-Ege, Krishna K Parat
  • Patent number: 9368567
    Abstract: Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kuo-Chi Tu
  • Patent number: 9349686
    Abstract: Systems and methods are directed to an integrated circuit comprising a reduced height M1 metal line formed of an exemplary material with lower mean free path than Copper, for local routing of on-chip circuit elements of the integrated circuit, wherein the height of the reduced height M1 metal line is lower than a minimum allowed or allowable height of a conventional M1 metal line formed of Copper. The exemplary materials for forming the reduced height M1 metal line include Tungsten (W), Molybdenum (Mo), and Ruthenium (Ru), wherein these exemplary materials also exhibit lower capacitance and lower RC delays than Copper, while providing high electromigration reliability.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: May 24, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Stanley Seungchul Song, Choh Fei Yeap, Zhongze Wang, Niladri Mojumder, Mustafa Badaroglu
  • Patent number: 9312306
    Abstract: According to an embodiment, a first impurity diffusion layer is provided in a region lower than a drain region and the first impurity diffusion layer diffuses impurities of a second conductivity type. A second impurity diffusion layer is provided between the drain region and the first impurity diffusion layer, and the second impurity diffusion layer diffuses impurities of a first conductivity type or the second conductivity type, and a concentration of the second impurity diffusion layer is lower than that of the first conductivity type of the drain region and that of the second conductivity type of the first impurity diffusion layer.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshinori Nakakubo, Shigeki Kobayashi, Takeshi Yamaguchi
  • Patent number: 9293357
    Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Takehito Tamura
  • Patent number: 9276057
    Abstract: A capacitor structure includes a substrate with a plurality of dielectric layers sequentially formed thereon, a trench formed in the dielectric layers, wherein the trench is composed of at least two interconnected dual damascene recesses, each dual damascene recess formed in one dielectric layer; and a capacitor multilayer disposed on the sidewall of the trench.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 1, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Duan Quan Liao, Yikun Chen, Ching Hwa Tey, Xiao Zhong Zhu
  • Patent number: 9263383
    Abstract: An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: February 16, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sung Su Kim
  • Patent number: 9263518
    Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: February 16, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Christian Rivero, Guilhem Bouton, Pascal Fornara
  • Patent number: 9252156
    Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: February 2, 2016
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Yi-Hsuan Hsiao, Chih-Ping Chen
  • Patent number: 9202589
    Abstract: There is provided a non-volatile memory including: plural zener zap devices, each including a cathode region and an anode region formed in a well; and a metal wiring line that is formed above the plural zener zap devices, that is commonly connected to each of the cathode regions, and that supplies a write voltage to each of the zener zap devices.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: December 1, 2015
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masayuki Otsuka
  • Patent number: 9196380
    Abstract: A method for measuring data retention characteristic of an RRAM device includes: a) controlling a temperature of a sample stage to maintain the RRAM device at a predetermined temperature; b) setting the RRAM device to a high-resistance state or a low-resistance state; c) measuring data retention time by applying a predetermined voltage to the RRAM device so that a resistive state failure of the RRAM device occurs; d) repeating the steps a)-c) to perform a plurality of measurements; e) calculating a resistive state failure probability F(t) of the RRAM device from the data retention time in the plurality of measurements; and f) fitting the resistive state failure probability F(t), and calculating predicted data retention time tE by using parameters obtained from the fitting. The data retention time of the RRAM device may be predicted by combining voltage acceleration and temperature acceleration.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: November 24, 2015
    Assignee: Peking University
    Inventors: Lifeng Liu, Bin Gao, Jinfeng Kang, Xiaoyan Liu, Yi Wang
  • Patent number: 9165828
    Abstract: A semiconductor device comprises a semiconductor substrate, an anorganic isolation layer on the semiconductor substrate and a metallization layer on the anorganic isolation layer. The metallization layer comprises a fuse structure. At least in an area of the fuse structure the metallization layer and the anorganic isolation layer have a common interface.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 20, 2015
    Assignee: Infineon Technologies AG
    Inventors: Gabriele Bettineschi, Uwe Seidel, Wolfgang Walter, Michael Schrenk, Hubert Werthmann
  • Patent number: 9159768
    Abstract: A semiconductor device includes: a vertical electrode provided over a substrate; a variable resistance layer provided at least a sidewall of the vertical electrode; a plurality of horizontal electrodes extending from the sidewall of the vertical electrode and having the variable resistance layer interposed; a transition metal oxide layer provided (i) between the vertical electrode and the variable resistance layer or (ii) between the plurality of horizontal electrodes and the variable resistance layer; and a threshold voltage switching layer provided in the transition metal oxide layer and selectively between the vertical electrode and the any of the plurality of horizontal electrodes.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Moon-Sig Joo, Woo-Young Park
  • Patent number: 9153773
    Abstract: A contact fuse is provided. The contact fuse includes a metal oxide semiconductor (MOS) transistor and a control circuit having outputs coupled to a plurality of terminals of the MOS transistor. The control circuit is operable to forward bias a body-source junction during a programming operation and operable to short the body-source junction during a sensing operation. A method of operating a contact fuse is also provided.
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: October 6, 2015
    Assignee: Altera Corporation
    Inventors: Cheng-Hsiung Huang, Shih-Lin Lee, Shuang Xie
  • Patent number: 9129687
    Abstract: A one time programmable memory cell having twin wells to improve dielectric breakdown while minimizing current leakage. The memory cell is manufactured using a standard CMOS process used for core and I/O (input/output) circuitry. A two transistor memory cell having an access transistor and an anti-fuse device, or a single transistor memory cell 100 having a dual thickness gate oxide 114 & 116, are formed in twin wells 102 & 104. The twin wells are opposite in type to each other, where one can be an N-type well 102 while the other can be a P-type well 104. The anti-fuse device is formed with a thin gate oxide and in a well similar to that used for the core circuitry. The access transistor is formed with a thick gate oxide and in a well similar to that used for I/O circuitry.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: September 8, 2015
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 9105802
    Abstract: A method of making a photovoltaic device is presented. The method includes disposing an absorber layer on a window layer. The method further includes treating at least a portion of the absorber layer with a first solution including a first metal salt to form a first component, wherein the first metal salt comprises a first metal selected from the group consisting of manganese, cobalt, chromium, zinc, indium, tungsten, molybdenum, and combinations thereof. The method further includes treating at least a portion of the first component with cadmium chloride to form a second component. The method further includes treating at least a portion of the second component with a second solution including a second metal salt to form an interfacial layer on the second component, wherein the second metal salt comprises a second metal selected from the group consisting of manganese, cobalt, nickel, zinc, and combinations thereof.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: August 11, 2015
    Assignee: First Solar, Inc.
    Inventors: Hongbo Cao, Donald Franklin Foust
  • Patent number: 9105638
    Abstract: In an embodiment of the present invention, a semiconductor device comprises a non-fuse area that has a non-fuse via, a non-fuse line, and a non-fuse dielectric stack. The semiconductor device further comprises a fuse area that has a fuse via, a fuse line, and a fuse dielectric stack. The fuse dielectric stack comprises at least a first dielectric and a second dielectric material. The fuse via is at least partially embedded in the first dielectric material and the fuse line is embedded in the second dielectric material.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Wai-Kin Li, Naftali E. Lustig, Andrew H. Simon
  • Patent number: 9096059
    Abstract: There are provided a substrate for an inkjet head, an inkjet head, and an inkjet printing apparatus wherein in a case where current is carried through a protection layer for heating resistors, electrical connection to its periphery is prevented without fail. The substrate for the inkjet head includes a first protection layer disposed to cover a heating resistor layer and having an insulation property and a second protection layer disposed to contact the first protection layer and having conductivity. The second protection layer includes a plurality of individual sections provided to correspond to the plurality of heating resistors, a common section connecting the plurality of individual sections, and fuse sections connecting the individual sections and the common section, the fuse sections being formed to be thinner than the individual sections.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 4, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takuya Hatsui, Yuzuru Ishida, Kazuaki Shibata, Takeru Yasuda
  • Patent number: 9076723
    Abstract: A nonvolatile memory device includes: a first interconnection extending in a first direction; a second interconnection extending in a second direction, and a lower end of the second interconnection being located above the first interconnection; a plurality of third interconnections extending in a third direction, and the third interconnections being arranged in the second direction; a current limitation layer provided between the second interconnection and the third interconnections; a metal ion source layer provided between the current limitation layer and the third interconnections; a resistance change layer provided between the current limitation layer and the third interconnections; and a selector provided between the first interconnection and the lower end of the second interconnection.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: July 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Matsunami, Masayuki Ichige, Takuya Konno, Kikuko Sugimae
  • Patent number: 9040370
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Publication number: 20150130509
    Abstract: An antifuse apparatus can include a cantilever extending from a first electrode portion to terminate in a distal end. A second electrode portion can be spaced apart from the cantilever by an air gap. In response to a program voltage across the first and second electrode portions, the cantilever can be adapted to move from an unprogrammed condition, corresponding to an open circuit condition where the cantilever is spaced apart from the second electrode portion, to at least one permanent programmed condition, corresponding to a short circuit condition between the first and second electrode portions where the cantilever engages the second electrode portion.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 14, 2015
    Inventors: Ting He, Fengchao Zhang, Swarup Bhunia, Philip X.-L. Feng
  • Publication number: 20150115401
    Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo