Comprising Antifuses, I.e., Connections Having Their State Changed From Nonconductive To Conductive (epo) Patents (Class 257/E23.147)
  • Patent number: 10424907
    Abstract: An electrical junction box has a switch connected between a first connection terminal and a second connection terminal to which a fuse is mounted, and a control circuit configured to perform opening/closing control of the switch, has a storage unit for storing a standard resistance value in an initial state of the fuse and an amount of change in a resistance value of the fuse over time, and detects a first terminal voltage at the first connection terminal and a second terminal voltage at the second connection terminal. The control circuit opens the switch at a time of startup based on a control signal, calculates the resistance value of the fuse, calculates a reference resistance value, determines whether the fuse is correct by comparing the calculated resistance value of the fuse with the calculated reference resistance value, and outputs a first error signal if the fuse is incorrect.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: September 24, 2019
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Tooru Kumagai
  • Patent number: 10037801
    Abstract: A memory device includes a plurality of resistive memory cells and a plurality of word lines. Each resistive memory cell includes a resistive memory element, a first switching element electrically coupled in series with the resistive memory element, and a second switching element electrically coupled in series with the first switching element. The first switching element and the second switching element in each resistive memory cell is coupled to different ones of the word lines.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: July 31, 2018
    Assignee: Hefei Reliance Memory Limited
    Inventors: Deepak Chandra Sekar, Wayne Frederick Ellis, Brent Steven Haukness, Gary Bela Bronner, Thomas Vogelsang
  • Patent number: 9870886
    Abstract: A protective element includes: a rectangurarly shaped insulating substrate; a heat-generating element formed on the insulating substrate; first and second electrodes laminated on a surface of the insulating substrate; first and second connecting terminals provided on a back surface of the insulating substrate and being continuous with the first and second electrodes; a heat-generating element extracting electrode provided on a current path between the first and the second electrodes and electrically connected to the heat-generating element; and a meltable conductor laminated on a region extending from the heat-generating element extracting electrode to the first and second electrodes and to be melted by heat to interrupt the current path between the first electrode and the second electrodes; wherein at least one of the corner portions of the insulating substrate is chamfered.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: January 16, 2018
    Assignee: DEXERIALS CORPORATION
    Inventors: Yuji Furuuchi, Takashi Fujihata, Koichi Mukai
  • Patent number: 9842802
    Abstract: One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to a dielectric breakdown voltage VBD of the antifuse is applied to the first conductor plate and the second conductor plate. The first conductor plate has a total edge length that is greater than two times the sum of its maximum width and maximum length dimensions. The first conductor plate's top surface area may also be less than the product of its maximum length and maximum width.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: December 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, John Jianhong Zhu, Xia Li
  • Patent number: 9754903
    Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj K. Patil, Min-hwa Chi, Ajey Poovannummoottil Jacob
  • Patent number: 9607895
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having an upper surface and a bottom surface; and forming a deep hole in the substrate from the upper surface. The method also includes forming an amorphous silicon layer on a side surface and a bottom surface of the deep hole to promote a preferred crystal orientation in subsequently formed layers. Further, the method includes forming a barrier layer having a preferred orientation along the (111) crystal face on the barrier layer. Further, the method also includes forming a metal layer having a preferred orientation along the (111) crystal face on the barrier layer to fill the through hole.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: March 28, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Zuopeng He, Hongbo Zhao
  • Patent number: 9344076
    Abstract: A bypass circuit is provided. The bypass circuit is integrated in a single chip. The bypass circuit includes a first pin set, a second pin set, an output pin set, and a switching circuit. The first pin set receives a first input signal from outside of the single chip. The switching circuit is coupled to the first pin set and transmits the first input signal to the second pin set or the output pin set.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: May 17, 2016
    Assignee: ACCTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Che Hsieh
  • Patent number: 9293221
    Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
    Type: Grant
    Filed: February 26, 2015
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Derrick Liu, Chun-Chen Yeh
  • Patent number: 9287000
    Abstract: A technique is provided for programming a transistor having a source, a drain, a gate, and a channel region between the source and the drain. The gate is above dielectric above the channel region. A gate voltage is about equal to or greater than a breakdown voltage of the gate dielectric in order to break down the gate dielectric into a breakdown state. Current flows between the source and the drain as a result of breaking down the gate dielectric. In response to the transistor being programmed, the current flowing between the source and the drain is not based on the gate voltage at the gate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Derrick Liu, Chun-Chen Yeh
  • Patent number: 9040370
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 9007838
    Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichiro Zaitsu, Kosuke Tatsumura
  • Patent number: 9006741
    Abstract: A memory device is provided, which includes a first conductive layer, a second conductive layer, and a memory layer interposed between the first conductive layer and the second conductive layer. The memory layer includes a first portion and a second portion, each of which includes at least a nanoparticle. The nanoparticle includes a conductive material coated with an organic film. The first portion is in contact with the first conductive layer and the second conductive layer, and a side surface of the first portion is surrounded by the second portion.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kensuke Yoshizumi, Noriko Harima
  • Patent number: 8981524
    Abstract: An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Tajima, Hajime Tokunaga
  • Patent number: 8975122
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: March 10, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8969141
    Abstract: According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Broadcom Corporation
    Inventor: Laurentiu Vasiliu
  • Patent number: 8937357
    Abstract: According to one embodiment, a one-time programmable (OTP) semiconductor device includes a programming dielectric under a patterned electrode and over an implant region, where the programming dielectric forms a programming region of the OTP semiconductor device. The OTP semiconductor device further includes an isolation region laterally separating the programming dielectric from a coupled semiconductor structure, where the isolation region can be used in conjunction with the patterned electrode and the implant region to protect the coupled semiconductor structure. In one embodiment, the programming dielectric comprises a gate dielectric. In another embodiment, the electrode and implant regions are doped to be electrochemically similar.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: January 20, 2015
    Assignee: Broadcom Corporation
    Inventors: Frank Hui, Xiangdong Chen
  • Patent number: 8896092
    Abstract: An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: November 25, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yutaka Takeshima, Toshiyuki Nakaiso, Shinsuke Tani
  • Patent number: 8889490
    Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshinobu Asami
  • Patent number: 8884398
    Abstract: A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chu-Fu Lin, Chien-Li Kuo, Ching-Li Yang
  • Patent number: 8878291
    Abstract: A semiconductor device includes a first buried gate structure in a peripheral circuit area of a semiconductor substrate, and a second gate structure formed on the semiconductor substrate. A gate insulating layer of a program transistor is thinly formed to be easily ruptured, and a gate insulating layer of a select transistor is thickly formed to improve reliability of the select transistor.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: November 4, 2014
    Assignee: SK Hynix Inc.
    Inventor: Yong Sun Jung
  • Patent number: 8866257
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Ll, Ping-Chaun Wang
  • Patent number: 8759946
    Abstract: A semiconductor device which does not reduce writing property of a memory element and a method for manufacturing the same are proposed even in the case of forming a silicon film at a step portion formed by a surface of a substrate and a wiring formed over the substrate. The semiconductor device includes a plurality of the memory elements comprising a first electrode formed over a substrate having an insulating surface, sidewall insulating layer formed on side surface of the first electrode, a silicon film formed to cover the first electrode and the sidewall insulating layer, and a second electrode formed over the silicon film, and at least one of the first electrode and the second electrode is formed with a material being capable of being alloyed with the silicon film.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: June 24, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Tokunaga
  • Patent number: 8754498
    Abstract: A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: June 17, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yue-Der Chih, Chrong Jung Lin
  • Patent number: 8749020
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; a metal fuse in the dielectric layer; a dummy pattern adjacent the metal fuse; and a metal line in the dielectric layer, wherein a thickness of the metal fuse is substantially less than a thickness of the metal line.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Shin-Puu Jeng, Shih-Hsun Hsu
  • Patent number: 8742457
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 8716071
    Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: May 6, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
  • Patent number: 8674475
    Abstract: Provided are an antifuse and methods of operating and manufacturing the same. The antifuse may include first and second conductors separate from each other; a dielectric layer for an antifuse between the first and second conductors; and a diffusion layer between one of the first and second conductors and the dielectric layer.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Deok-kee Kim, Jung-hun Sung, Sang-moo Choi, Soo-jung Hwang
  • Publication number: 20140070363
    Abstract: An electronic anti-fuse structure, the structure including an Mx level comprising a first Mx metal and a second Mx metal, a dielectric layer located above the Mx level, an Mx+1 level located above the dielectric layer; and a metallic element in the dielectric layer and positioned between the first Mx metal and the second Mx metal, wherein the metallic element is insulated from both the first Mx metal and the second Mx metal.
    Type: Application
    Filed: September 10, 2012
    Publication date: March 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Griselda Bonilla, Samuel S. Choi, Ronald G. Filippi, Naftali Eliahu Lustig, Andrew H. Simon
  • Publication number: 20140061852
    Abstract: In one general aspect, an apparatus can include a semiconductor substrate, and a first conductive fuse bus having a triangular-shaped portion with a bottom surface aligned along a plane substantially parallel to a surface of the semiconductor substrate. The apparatus can include a second conductive fuse bus having a bottom surface aligned along the plane, and a plurality of fuse links coupled between the triangular-shaped portion of the first conductive fuse bus and the second conductive fuse bus.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 6, 2014
    Inventor: William R. Newberry
  • Patent number: 8664744
    Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers on the upper and lower surfaces of the insulation layer; and an extraction electrode formed so as to make contact with a section of the electrode layers that form electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section including short circuit sections that are short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by engulfing the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. Furthermore, the extraction electrode has at least two or more sections in contact with the electrode layer.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 4, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Toshiyuki Nakaiso
  • Patent number: 8638589
    Abstract: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: January 28, 2014
    Assignee: eMemory Technology Inc.
    Inventors: Hau-Yan Lu, Hsin-Ming Chen, Ching-Sung Yang
  • Publication number: 20140021581
    Abstract: An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Chao Yang, Stephen M. Gates
  • Patent number: 8633567
    Abstract: A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO2, Al2O3, ZrO2, TiO2, La2O3, Ta2O5, RuO2, ZrSiOx, AlSiOx, HfSiOx, HfAlOx, HfSiON, ZrSiAlOx, HfSiAlOx, HfSiAlON, and ZrSiAlON. Numerous other aspects are provided.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 21, 2014
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Publication number: 20140015095
    Abstract: According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Frank Hui, Neal Kistler
  • Patent number: 8624299
    Abstract: An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: January 7, 2014
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8610245
    Abstract: An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 17, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shinsuke Tani, Toshiyuki Nakaiso
  • Publication number: 20130307115
    Abstract: A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 21, 2013
    Applicant: International Business Machines Corporation
    Inventors: Ronald G. Filippi, Naftali Lustig, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 8575719
    Abstract: Silicon nitride antifuses can be advantageously used in memory arrays employing diode-antifuse cells. Silicon nitride antifuses can be ruptured faster and at a lower breakdown field than antifuses formed of other materials, such as silicon dioxide. Examples are given of monolithic three dimensional memory arrays using silicon nitride antifuses with memory cells disposed in rail-stacks and pillars, and including PN and Schottky diodes. Pairing a silicon nitride antifuse with a low-density, high-resistivity conductor gives even better device performance.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 5, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Mark G. Johnson, N. Johan Knall, S. Brad Herner
  • Patent number: 8569755
    Abstract: An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Yan Zun Li, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran
  • Patent number: 8542517
    Abstract: An antifuse can include an insulated gate field effect transistor (“IGFET”) having an active semiconductor region including a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is electrically connected with the body. The first regions have opposite conductivity (i.e., n-type or p-type) from the body. The IGFET can be configured such that a programming current through at least one of the first regions and the body contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In such way, the programming current can permanently reduce electrical resistance by one or more orders of magnitude between the at least one first region and the at least one other first region.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 24, 2013
    Assignee: International Business Machines Corporation
    Inventor: Yan Zun Li
  • Patent number: 8519508
    Abstract: A semiconductor device has a conventional NMOS transistor and an NMOS transistor functioning as an anti-fuse element and having an n type channel region. The conventional NMOS transistor is equipped with an n type extension region and a p type pocket region, while the anti-fuse element is not equipped with an extension region and a pocket region. This makes it possible to improve the performance of the transistor and at the same time improve the characteristics of the anti-fuse element after breakdown of its gate dielectric film.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: August 27, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshitaka Kubota, Hiroshi Tsuda, Kenichi Hidaka, Takuji Onuma, Hiromichi Takaoka
  • Patent number: 8513768
    Abstract: Under one aspect, a non-volatile nanotube diode device includes first and second terminals; a semiconductor element including a cathode and an anode, and capable of forming a conductive pathway between the cathode and anode in response to electrical stimulus applied to the first conductive terminal; and a nanotube switching element including a nanotube fabric article in electrical communication with the semiconductive element, the nanotube fabric article disposed between and capable of forming a conductive pathway between the semiconductor element and the second terminal, wherein electrical stimuli on the first and second terminals causes a plurality of logic states.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 20, 2013
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, X. M. Henry Huang, Ramesh Sivarajan, Eliodor G. Ghenciu, Steven L. Konsek, Mitchell Meinhold, Jonathan W. Ward, Darren K. Brock
  • Patent number: 8513769
    Abstract: Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: August 20, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li, Anthony K. Stamper, Haining S. Yang
  • Patent number: 8493767
    Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: July 23, 2013
    Assignee: Broadcom Corporation
    Inventors: Akira Ito, Xiangdong Chen
  • Patent number: 8476157
    Abstract: An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.?doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.?doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.?doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.
    Type: Grant
    Filed: July 22, 2010
    Date of Patent: July 2, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8471355
    Abstract: An AND-type anti-fuse memory cell, and a memory array consisting of AND-type anti-fuse memory cells. Chains of AND type anti-fuse cells are connected in series with each other, and with a bitline contact, in order to minimize the area occupied by the memory array. Each AND type anti-fuse cell includes an access transistor serially connectable to the bitline or the access transistors of other AND type anti-fuse cells, and an anti-fuse device. The channel region of the access transistor is connected to the channel region of the anti-fuse device, and both channel regions are covered by the same wordline. The wordline is driven to a programming voltage level for programming the anti-fuse device, or to a read voltage level for reading the anti-fuse device.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: June 25, 2013
    Assignee: Sidense Corp.
    Inventor: Wlodek Kurjanowicz
  • Patent number: 8471356
    Abstract: Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: June 25, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Louis L. Hsu, William R. Tonti, Chih-Chao Yang
  • Publication number: 20130153960
    Abstract: A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsiao-Lan Yang
  • Patent number: 8455973
    Abstract: A region divided substrate includes a substrate, a plurality of trenches, a conductive layer, and an insulating member. The substrate has a first surface and a second surface opposed to each other. The trenches penetrate the substrate from the first surface to the second surface and divide the substrate into a plurality of partial regions. The conductive layer is disposed on a sidewall of each of the trenches from a portion adjacent to the first surface to a portion adjacent to the second surface. The conductive layer has an electric conductivity higher than an electric conductivity of the substrate. The insulating member fills each of the trenches through the conductive layer.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: June 4, 2013
    Assignee: DENSO CORPORATION
    Inventors: Tetsuo Fujii, Masaya Tanaka, Keisuke Gotoh
  • Patent number: 8395232
    Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: March 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Shinichi Horiba, Nobuyuki Nakamura, Eiji Kitamura