TRENCH MOSEFT WITH TRENCH GATES UNDERNEATH CONTACT AREAS OF ESD DIODE FOR PREVENTION OF GATE AND SOURCE SHORTATE

Abstract

A trench DMOS transistor having overvoltage protection and prevention for shortage between gate and source when contact trenches are applied includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trench gates extend through the body region and the substrate. An insulating oxide layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer defining the Zener diode region. A plurality of cathode regions of the first conductivity type is formed in undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions. Trench gates underneath the Zener diode act as the buffer layer for prevention of shortage between gate and source.

Description

FIELD OF THE INVENTION

This invention relates generally to the cell structure, device configuration and fabrication process of MOSFET transistors. More particularly, this invention relates to a novel and improved cell configuration and processes to manufacture DMOS transistors with electrostatic discharge (ESD) protection having the characteristics of preventing for gate and source shortage.

BACKGROUND

Conventional technologies still have technical difficulties in dealing with the electrostatic discharge (ESD) problems in designing, manufacturing and implementing the semiconductor power devices. Specially, the high voltage transient signal from static discharge in a DMOS device can impose a voltage bias higher than 10,000 volts. The high electric field induced by the bias voltage when imposed on a relatively thin layer of gate dielectric layer often leads to hazardous conditions to the DMOS device. The thin layer of gate dielectric is most commonly implemented as an oxide layer. Under a high electric field, rapture is induced in the oxide layer that functions as an insulator. A permanent damage is thus introduced into a system implemented with the power semiconductor device. The reliability of system performance and operations suffer due this ESD problem. This problem is particularly pronounced in high voltage DMOS devices. Many ESD protective measures are implemented. DMOS devices are often designed and manufactured with self-contained ESD protection systems comprising multiple back to back Zener diodes as shown in FIG. 1. The ESD protection circuits can be implemented either as a discrete circuit or as an integrated part of the semiconductor power devices.

FIG. 1 shows the circuit equivalent for a typical N-channel DMOS in which a back to back Zener diode as ESD (Electrostatic Discharge) protection diode is located between the source and gate of the DMOS. The ESD protection diode breaks down when the gate to source voltage exceeds a specified voltage value.

FIG. 2 and FIG. 3 illustrate an example of a conventional trench DMOS structure having ESD protection and its disadvantage.

Refer to FIG. 2, which is about U.S. Pat. No. 6,657,256 and U.S. Pat. No. 6,884,683, the structure includes an n+ substrate 200 on which is grown a lightly n-doped region 204. Within doped epitaxial layer 204, a body region 216 of opposite conductivity is provided. An n-doped layer 240 that overlies most of the body region 216 serves as the source. A rectangularly shaped trench 224 is provided in the epitaxial layers. A gate oxide layer 230 lines the sidewalls of the trench 224. The trench 224 is filled with polysilicon 252. An ESD protection poly diode is two back to back Zener diode comprising two cathodes 245 and one anode 248. A thin layer of oxide is formed underneath the ESD protection diode acting as the insulating layer, as shown in FIG. 2.

FIG. 3 shows the disadvantage of the DMOS structure of FIG. 2 when trench contacts into epitaxial layer are applied. The ESD protection diode is shorted with body-source region as a result of the doped poly over-etching region 260, and the insulator etch-through caused by poor etching selectivity of the oxide over the doped poly.

One problem with the device shown in the previously mentioned patent is that if trench contacts are applied for source and gate which requires additional Si trench etch, the prior art shown in FIG. 2 will encounter the ESD diode shorting with body-source, causing low yield and reliability issues, as shown in FIG. 3. The shortage is resulted from etch through ESD diode poly and thin oxide underneath mentioned above, which will lead to a permanent damage to the device.

Accordingly, it would be desirable to provide a trench DMOS transistor having overvoltage protection from ESD resolving the shortage issues when trench contacts are applied.

SUMMARY OF THE INVENTION

The present invention provides a trench DMOS transistor having overvoltage protection and the ability to avoid ESD shorting with source when trench contacts are applied.

The transistor includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trenches extend through the body region and substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. A doped polysilicon layer overlies a portion of the insulating layer as an ESD protection diode comprising multiple back to back Zener diodes. The ESD protection diode comprising an array of doped regions comprising doped regions doped alternately with a first conductivity type and a second conductivity type with a first and last doped regions doped with a first conductivity type wherein one of the two doped regions connected to the source metal and another one of the two doped regions connected to the gate metal of the semiconductor power device. Specially, underneath contact areas of the ESD diode in FIG. 4, trench gates are formed. The trench gate serves as a buffer layer to avoid ESD shorting source and gate.

In accordance with aspect of the invention, the doped polysilicon layer overlies a portion of the insulating layer that is vertically displaced from the body region.

In accordance with another aspect of the invention, the ESD protection diode formed with plurality of the first conductivity and second conductivity doped regions is disposed in the portion of the insulating layer vertically displaced from the trench.

In accordance with yet another aspect of he invention, the plurality of the second conductivity doped region include Boron implanted therein.

In accordance with yet another aspect of the invention, the source region and plurality of the first conductivity type regions in the second conductivity type doped poly are formed in simultaneous deposition steps.

These and other objects and advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment, which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein:

FIG. 1 shows the circuit equivalent for a typical N-channel DMOS in which a back to back Zener diode is located between the source and gate of the DMOS.

FIG. 2 shows a cross-section of a conventional trench DMOS structure with ESD protection.

FIG. 3 shows the shortage issue of the conventional trench DMOS structure when trench contacts into epitaxial layer are applied.

FIG. 4 shows a cross-sectional of trench DMOS structure of this invention.

FIG. 5 shows the advantage of the trench DMOS structure of this invention.

FIGS. 6A to 6G illustrate a sequence of process steps forming a DMOS transistor having overvoltage protection without ESD shorting issues constructed in accordance with the present invention as shown in FIG. 4.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 4 illustrates the DMOS structure of this invention in cross-section. In FIG. 4, the ESD protection diode comprises cathodes 145 and anode 148. Trench gates are formed underneath contact areas of the ESD protection diode in order to resolve the problems discussed above. Besides these, the structure shown in FIG. 4 is advantageous because the source region 140 of the DMOS transistor and n+ cathode regions 145 of the Zener diode can be formed in the same mask and implantation steps, and all the trenches gate can be formed in the same mask and in the same step.

FIG. 5 illustrates the function of this invention when trenches are overetched. The ESD diode does not short to body-source as result of the trench gate underneath the contact area as buffer layer. The ESD diode will touch to the trench gates underneath without shorting source area.

FIGS. 6A-6G show a series of exemplary steps that are performed to form the inventive trench DMOS devices. In FIG. 6A, an N− doped epitaxial layer 104 is grown on a conventionally N+ doped substrate 100. Epitaxial layer 104 is typically 5.5 microns in thickness for a 30V device. A mask layer is formed by covering the surface of epitaxial layer 104 with an oxide layer, which is then conventionally exposed and patterned to leave mask portions. The patterned mask portions define the trench sidewalls. Trenches 124 are dry Si etched through the mask opening to a depth that typically ranger from 0.9 to 2.5 microns. Then, the mask portion is removed. In FIG. 6B, the gate oxide layer 130 with thickness from 100 to 1000 A is then deposited on the entire structure. Next, the trenches 124 are filled with doped polysilicon 152. Then, the polysilicon 152 is etched back to expose the portion of the gate oxide layer 130 that extends over the surface of P-body 116, that followed by a step of P-body Ion Implantation, and then the diffusion step for P-body drive-in, and oxidation for formation of oxide layer 135 over the doped polysilicon 152.

In FIG. 6C, a undoped polysilicon layer 160 is deposited over the oxide layer 135. The undoped polysilicon layer 160, which defines the layer in which the ESD protection diode will be formed, typically has a thickness in the range of 5,000 to 10,000 angstroms. Then a step of blank Boron Ion Implantation is implemented.

In FIG. 6D, the doped polysilicon layer 160 is etched back with a poly mask so that it is completely removed from the region in which the DMOS transistor is defined. That is, doped polysilicon layer 160 is removed in such a way that it does not overlie the trench and body regions of the DMOS. Accordingly, the doped polysilicon layer 160 only remains in the region in which the ESD protection diode will be formed.

Next, in FIG. 6E, a photoresist masking process is used to form patterned masking layer 170. Patterned masking layer 170 defines source regions 140 of the trench DMOS transistor and n+ cathode regions 145 of the Zener diode. Source and cathode regions 140 and 145 are then formed by an Arsenic implantation and diffusion process. After implantation, the Arsenic is diffused to a depth of approximately 0.3˜0.5 microns.

In FIG. 6F, the masking layer 170 is removed in a conventional manner and a layer of oxide 135 is deposited over the structure to define oxide regions associated with the source and gate electrode. Then, a contact mask is used to define contact areas. After exposed, trenched contacts 333 are formed by dry oxide and Si etched. Finally, a step of Boron Ion Implantation is implemented to form P+ 148 around the contact trench bottom for achieving ohmic contact between P-body and metal plug filled into the trench contacts 333.

In FIG. 6G, a Ti/TiN/W layer is deposited onto the top layer that filled in the contact as the metal plug 223 in trench contacts 333. Then a tungsten etch is carried out to etch back the tungsten layer and a layer of metal 225 is deposited over the top surface and a metal mask is applied to carry out a metal layer followed by a dry metal etch via metal mask. And the final structure is finished.

Although the present invention has been described in terms of the presently preferred embodiment, it is to be understood that such disclosure is not to be interpreted as limiting. Various alternations and modifications will no doubt become apparent to those skilled in the art after reading the above disclosure. Accordingly, it is intended that the appended claims be interpreted as covering all alternations and modifications as fall within the true spirit and scope of the invention.

Claims

1. A trench DMOS transistor having overvoltage protection with prevention of shortage between gate and source from ESD, comprising:

a substrate of a first conductivity type;

a body region on the substrate, said body region having a second conductivity type;

a source region of the first conductivity type in said body region adjacent to each trench in DMOS area;

a conductive electrode in the trench overlying the insulating layer;

a gate oxide layer that lines along the trench and an insulating layer overlies said body region;

a ESD protection diode on top of said insulating layer; and

trench gates underneath contact areas of said ESD diode;

2. The transistor of claim 1, wherein the ESD protection diode is consisted of multiple in-series back to back Zener poly diodes.

3. The transistor of claim 1, wherein said insulating layer has a thickness ranging from 150 angstroms to 1500 angstroms.

4. The transistor of claim 1, wherein said conductive electrode is doped polysilicon.

5. The transistor of claim 1, wherein said trench gates underneath contact areas of the ESD diode act as buffer layer for prevention of shortage between gate and source.

6. The transistor of claim 1, wherein said contact trenches of source and gate is formed with dry oxide and Si etches and filled with metal plug.

7. The transistor of claim 1, wherein further comprising a drain electrode disposed on a bottom surface of the substrate.

8. The transistor of claim 7, wherein further comprising a source electrode contacted to the source and the body regions.