In Combination With Diode, Resistor, Or Capacitor (epo) Patents (Class 257/E27.016)
  • Patent number: 10672714
    Abstract: A fan-out semiconductor package includes: a first semiconductor chip having an active surface having first connection pads disposed thereon and an inactive surface opposing the active surface; a second semiconductor chip having an active surface having second connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of each of the first and second semiconductor chips; and a connection member disposed on the active surface of each of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second connection pads, wherein the first and second semiconductor chips are physically integrated with each other, and the first and second semiconductor chips have internal circuits, respectively.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Sek Jang, Sang Jin Lee
  • Patent number: 10644206
    Abstract: A lighting device is specified. The lighting device comprises a phosphor having the general molecular formula (MA)a(MB)b(MC)c(MD)d(TA)e(TB)f(TC)g(TD)h(TE)i(TF)j(XA)k(XB)l(XC)m(XD)n:E. In this case, MA is selected from a group of monovalent metals, MB is selected from a group of divalent metals, MC is selected from a group of trivalent metals, MD is selected from a group of tetravalent metals, TA is selected from a group of monovalent metals, TB is selected from a group of divalent metals, TC is selected from a group of trivalent metals, TD is selected from a group of tetravalent metals, TE is selected from a group of pentavalent elements, TF is selected from a group of hexavalent elements, XA is selected from a group of elements which comprises halogens, XB is selected from a group of elements which comprises O, S and combinations thereof, XC=N and XD=C and E=Eu, Ce, Yb and/or Mn. The following furthermore hold true: a+b+c+d=t; e+f+g+h+i+j=u; k+l+m+n=v; a+2b+3c+4d+e+2f+3g+4h+5i+6j?k?2l?3m?4n=w; 0.8?t?1; ?3.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: May 5, 2020
    Assignee: OSRAM OLED GMBH
    Inventors: Markus Seibald, Dominik Baumann, Stefan Lange, Hubert Huppertz, Thorsten Schroeder, Daniel Bichler, Gudrun Plundrich, Simon Peschke, Gregor Hoerder, Gina Maya Achrainer, Klaus Wurst
  • Patent number: 10535989
    Abstract: A semiconductor apparatus is provided, comprising: a power semiconductor element which is connected between a first terminal on a high-potential side and a second terminal on a low-potential side; a first gate control section which controls a gate potential of the power semiconductor element according to a control signal; a discharge circuit which is discharges charges that are charged by the gate of the power semiconductor element; a second gate control section which controls the gate potential of the power semiconductor element according to a collector current of the power semiconductor element; a feedback section which feedbacks the charges to the gate of the power semiconductor element according to the collector potential of the power semiconductor element; and a current cutting off section which cuts off currents flowing from the first terminal to the gate of the power semiconductor element according to the control signal.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: January 14, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shigemi Miyazawa
  • Patent number: 10078143
    Abstract: A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: September 18, 2018
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Micah Sandvik, Stanislav Ivanovich Soloviev, Sergei Ivanovich Dolinsky, James Jay McMahon, Sabarni Palit
  • Patent number: 10037950
    Abstract: It is desirable to design and manufacture electronic chips that are resistant to modern reverse engineering techniques. Disclosed is a method and device that allows for the design of chips that are difficult to reverse engineer using modern teardown techniques. The disclosed device uses devices having the same geometry but different voltage levels to create different logic devices. Alternatively, the disclosed uses devices having different geometries and the same operating characteristics. Also disclosed is a method of designing a chip using these devices.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 31, 2018
    Assignee: VERISITI, LLC
    Inventor: William Eli Thacker, III
  • Patent number: 9786657
    Abstract: A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor material over the electrically insulating layer and a transistor. The transistor includes an active region, a gate electrode region and an isolation junction region. The active region is provided in the active layer of semiconductor material and includes a source region, a channel region and a drain region. The gate electrode region is provided in the bulk semiconductor substrate and has a first type of doping. The isolation junction region is formed in the bulk semiconductor substrate and has a second type of doping opposite the first type of doping. The isolation junction region separates the gate electrode region from a portion of the bulk semiconductor substrate other than the gate electrode region that has the first type of doping.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Uwe Dersch, Ricardo Pablo. Mikalo
  • Patent number: 9537394
    Abstract: A resonant power converter comprising electrical safety components comprising a combination of a diodes and a zener diodes coupled between DC conductors and an auxiliary switching circuit, the diodes being adapted to hinder the current from flowing from the auxiliary switching circuit to the negative DC conductor, and the zener diodes being adapted to allow current to flow from the negative DC conductor to the auxiliary switching circuit when the potential difference between the negative DC conductor and the phase conductor is above a threshold voltage. The Zener diodes being selected such that the threshold voltage of the Zener diodes is below the maximum blocking voltage of the transistors.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 3, 2017
    Assignee: COMSYS AB
    Inventors: Dan Liljegren, Oscar Haraldsson
  • Patent number: 9536644
    Abstract: A composite resistor includes a thin film resistor element having a first temperature coefficient of resistance and a metal resistor element having a second temperature coefficient of resistance. A portion of the metal resistor element overlaps a portion of the thin film resistor element such that the portion of the metal resistor element is in thermal communication with the portion of the thin film resistor element to compensate for a resistance drift arising during operation of the composite resistor.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: January 3, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventor: Ronald R. Gobbi
  • Patent number: 9012297
    Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Helmut Horst Tews
  • Patent number: 9012966
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacito includes depositing a first middle of line (MOL) conductive layer over a shallow trench isolation (STI) region of a semiconductor substrate. The first MOL conductive layer provides a first plate of the MIM capacitor as well as a first set of local interconnects to source and drain regions of a semiconductor device. The method also includes depositing an insulator layer on the first MOL conductive layer as a dielectric layer of the MIM capacitor. The method further includes depositing a second MOL conductive layer on the insulator layer as a second plate of the MIM capacitor.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: April 21, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: PR Chidambaram, Bin Yang
  • Patent number: 9012293
    Abstract: A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Chang Yong Xiao, Roderick Miller, Jie Chen
  • Patent number: 9007099
    Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: April 14, 2015
    Assignee: Suzhou Poweron IC Design Co., Ltd
    Inventors: Yangbo Yi, Haisong Li, Ping Tao, Wengao Chen, Lixin Zhang
  • Patent number: 9006771
    Abstract: An exemplary embodiment of the present invention provides an organic light emitting diode, comprising a substrate, a first electrode, an organic material layer, and a second electrode, wherein a trench comprising a concave part and a convex part is provided on the substrate, the first electrode is provided on the substrate on which the trench is formed by being deposited, and an auxiliary electrode is provided on the first electrode. The organic light emitting diode according to the exemplary embodiment of the present invention may increase surface areas of the first electrode and the auxiliary electrode formed on the substrate, thereby implementing a low resistance electrode. In addition, since a line width of the electrode is not increased, it is possible to prevent a decrease of an opening ratio of the organic light emitting diode.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 14, 2015
    Assignee: LG Chem, Ltd.
    Inventors: Jung-Hyoung Lee, Jung-Bum Kim
  • Patent number: 9000564
    Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 7, 2015
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation, GlobalFoundries, Inc., Samsung Electronics Co., Ltd.
    Inventors: Pietro Montanini, Gerald Leake, Jr., Brett H. Engel, Roderick Mason Miller, Ju Youn Kim
  • Patent number: 8987820
    Abstract: A LDMOS device includes a substrate having opposite first and second surfaces; a well region in a portion of the substrate; a gate structure over a portion of the substrate; a first doped region disposed in a portion of the well region from a first side; a second doped region disposed in the well region from a second side; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a first trench in the third doped region, the first doped region, the well region, and the substrate adjacent to the first surface; a conductive contact in the first trench; a second trench in the substrate adjacent to the second surface; a first conductive layer in second trench; and a second conductive layer over the second surface of the substrate and the first conductive layer.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 24, 2015
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang
  • Patent number: 8981489
    Abstract: Semiconductor devices including a resistor structure is provided. The semiconductor device may include a gate structure on an active region, a resistor structure on a field region and a first interlayer insulating layer on the gate structure and the resistor structure. The semiconductor devices may also include a resistor trench plug vertically penetrating through the first interlayer insulating layer and contacting the resistor structure and a second interlayer insulating layer on the first interlayer insulating layer and the resistor trench plug. Further, the semiconductor devices may include a resistor contact plug vertically penetrating through the first and second interlayer insulating layers and contacting the resistor structure.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junjie Xiong, Yoon-Hae Kim, Hong-Seong Kang, Yoon-Seok Lee, You-Shin Choi
  • Patent number: 8981451
    Abstract: A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 17, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
  • Patent number: 8980703
    Abstract: A method of forming a semiconductor structure is provided. A substrate having a cell area and a periphery area is provided. A stacked structure including a gate oxide layer, a floating gate and a first spacer is formed on the substrate in the cell area and a resistor is formed on the substrate in the periphery area. At least two doped regions are formed in the substrate beside the stacked structure. A dielectric material layer and a conductive material layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the substrate to cover the stacked structure and a portion of the resistor. The dielectric material layer and the conductive material layer not covered by the patterned photoresist layer are removed, so as to form an inter-gate dielectric layer and a control gate on the stacked structure, and simultaneously form a salicide block layer on the resistor.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 17, 2015
    Assignee: Maxchip Electronics Corp.
    Inventors: Chen-Chiu Hsu, Tung-Ming Lai, Kai-An Hsueh, Ming-De Huang
  • Patent number: 8975133
    Abstract: One illustrative integrated circuit product disclosed herein includes a metal-1 metallization layer positioned above a semiconducting substrate, a capacitor positioned between a surface of the substrate and a bottom of the metal-1 metallization layer, wherein the capacitor includes a plurality of conductive plates that are oriented in a direction that is substantially normal relative to the surface of the substrate, and at least one region of insulating material positioned between the plurality of conductive plates.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: March 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kok Yong Yiang, Patrick R. Justison
  • Patent number: 8975748
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 10, 2015
    Assignee: Secure Silicon Layer, Inc.
    Inventor: William Eli Thacker, III
  • Patent number: 8962420
    Abstract: An embedded or buried resistive structure may be formed by amorphizing a semiconductor material and subsequently re-crystallizing the same in a polycrystalline state, thereby providing a high degree of compatibility with conventional polycrystalline resistors, such as polysilicon resistors, while avoiding the deposition of a dedicated polycrystalline material. Hence, polycrystalline resistors may be advantageously combined with sophisticated transistor architectures based on non-silicon gate electrode materials, while also providing high performance of the resistors with respect to the parasitic capacitance.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andreas Kurz, Roman Boschke, James Buller, Andy Wei
  • Patent number: 8937307
    Abstract: A semiconductor device including a capacitor with increased charge capacity and having a high aperture ratio and low power consumption is provided for a semiconductor device including a driver circuit. The semiconductor device includes a driver circuit which includes a first transistor including gate electrodes above and below a semiconductor film so as to overlap with the semiconductor film; a pixel which includes a second transistor including a semiconductor film; a capacitor which includes a dielectric film between a pair of electrodes in the pixel; and a capacitor line electrically connected to one of the pair of electrodes. In the semiconductor device, the gate electrode over the semiconductor film of the first transistor is electrically connected to the capacitor line.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8928030
    Abstract: An A-NPC circuit is configured so that the intermediate potential of two connected IGBTs is clamped by a bidirectional switch including two RB-IGBTs. Control is applied to the turn-on di/dt of the IGBTs during the reverse recovery of the RB-IGBTs. The carrier life time of an n? drift region in each RB-IGBT constituting the bidirectional switch is comparatively longer than that in a typical NPT structure device. A low life time region is also provided in the interface between the n? drift region and a p collector region, and extends between the n? drift region and the p collector region. Thus, it is possible to provide a low-loss semiconductor device, a method for manufacturing the semiconductor device and a method for controlling the semiconductor device, in which the reverse recovery loss is reduced while the reverse recovery current peak and the jump voltage peak during reverse recovery are suppressed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: January 6, 2015
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Hong-fei Lu
  • Patent number: 8928043
    Abstract: A high voltage FET device provides drain voltage information with less overall silicon area consumption by forming a spiral resistance poly structure over a drift region of the high voltage FET device. The spiral resistance poly structure has an inner most end coupled to a drain region, and an outer most end coupled to a reference ground.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: January 6, 2015
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Joseph Urienza
  • Patent number: 8883621
    Abstract: Provided is a semiconductor structure including a gate structure, a first spacer, and a second spacer. The gate structure is formed on a substrate and includes a gate material layer, a first hard mask layer disposed on the gate material layer, and a second hard mask layer disposed on the first hard mask layer. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed adjacent to the first spacer. The etch rate of the first hard mask layer, the etch rate of the first spacer, and the etch rate of the second spacer are substantially the same and significantly smaller than the etch rate of the second hard mask layer in a rinsing solution.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jung Li, Po-Chao Tsao
  • Patent number: 8872269
    Abstract: An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 28, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Hang Yang, Chun-Fu Chen, Pin-Dai Sue, Hui-Zhong Zhuang
  • Patent number: 8866201
    Abstract: A high-voltage device structure comprises a resistor coupled to a tap transistor that includes a JFET in a configuration wherein a voltage provided at a terminal of the JFET is substantially proportional to an external voltage when the external voltage is less than a pinch-off voltage of the JFET. The voltage provided at the terminal being substantially constant when the external voltage is greater than the pinch-off voltage. One end of the resistor is substantially at the external voltage when the external voltage is greater than the pinch-off voltage. When the external voltage is negative, the resistor limits current injected into the substrate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: October 21, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Sujit Banerjee, Vijay Parthasarathy
  • Patent number: 8860110
    Abstract: Semiconductor devices including spacers on sidewalls of conductive lines are provided. The semiconductor device includes bit lines on a semiconductor substrate, a storage node contact plug penetrating an insulation layer between the bit lines, triple-layered bit line spacers between the bit lines and the storage node contact plugs, and storage node electrodes on the storage node contact plugs. Each of the triple-layered bit line spacers includes a first spacer adjacent to one of the bit lines, a third spacer adjacent to the storage node contact plugs and a second spacer between the first and third spacers. The second spacer includes a lower portion having a lower dielectric constant than the first and third spacers and an upper portion having the same material as the first and third spacers. Related methods are also provided.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 14, 2014
    Assignee: SK hynix Inc.
    Inventor: Jong Pil Lee
  • Patent number: 8860145
    Abstract: A semiconductor device incorporates a resistor on a structure that uses diffusion layers for sustaining the breakdown voltage thereof to realizes a very resistive element that exhibits a high breakdown voltage and high electrical resistance, includes a spiral very resistive element buried in an interlayer insulator film. A first end of the very resistive element is connected to a drain electrode wiring and the second end of the very resistive element is grounded. An intermediate point of the very resistive element is connected to ae voltage comparator of a control IC. The semiconductor device according to the invention facilitates reducing the components parts costs, assembly costs and size of a switching power supply that includes a very resistive element.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: October 14, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Masaru Saito
  • Patent number: 8853045
    Abstract: A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: GlobalFoundries, Inc.
    Inventor: Steven R. Soss
  • Patent number: 8836027
    Abstract: The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (VGS) of the LDMOS device may be stably controlled through a current source and resistances, the characteristics of a switch may be maintained regardless of the voltages of both terminals (A and B) by using an N-type LDMOS and a P-type LDMOS in a complementary manner, and the current generated by the current source is offset inside the switch without flowing to the outside of the switch.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Silicon Works Co., Ltd.
    Inventors: Young Jin Woo, Kong Soon Park, Young Sik Kim
  • Patent number: 8835246
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. The at least one transistor includes a first gate dielectric structure disposed over a substrate. A work-function metallic layer is disposed over the first gate dielectric structure. A conductive layer is disposed over the work-function metallic layer. A source/drain (S/D) region is disposed adjacent to each sidewall of the first gate dielectric structure. At least one resistor structure is formed over the substrate. The at least one resistor structure includes a first doped semiconductor layer disposed over the substrate. The at least one resistor structure does not include any work-function metallic layer between the first doped semiconductor layer and the substrate.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh
  • Patent number: 8835251
    Abstract: A semiconductor device includes a transistor, a capacitor and a resistor wherein the capacitor includes a doped polysilicon layer to function as a bottom conductive layer with a salicide block (SAB) layer as a dielectric layer covered by a Ti/TiN layer as a top conductive layer thus constituting a single polysilicon layer metal-insulator-polysilicon (MIP) structure. While the high sheet rho resistor is also formed on the same single polysilicon layer with differential doping of the polysilicon layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 16, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: YongZhong Hu, Sung-Shan Tai
  • Patent number: 8823071
    Abstract: Disclosed is a pixel electrode which is electrically connected to a scanning line electrically connected to a gate electrode, a data line electrically connected to a data line side source and drain region, and a pixel electrode side source and drain region; and a capacitance element which has a first capacitance electrode which is electrically connected to a capacitance line, a second capacitance electrode which is provided to oppose the first capacitance electrode, and a dielectric layer which is interposed between the first capacitance electrode and the second capacitance electrode, where the first capacitance electrode is arranged to be covered with the dielectric layer and the second capacitance electrode between a layer where the transistor, the scanning line, and the data line are provided and a layer where the pixel electrode is provided.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: September 2, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Shin Oyamada
  • Patent number: 8823053
    Abstract: The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Sakiyama, Kohei Morizuka
  • Patent number: 8816417
    Abstract: A semiconductor device includes a back bias dielectric including a negative fixed charge, a gate electrode overlapping the back bias dielectric, a semiconductor layer disposed between the gate electrode and the back bias dielectric, and a gate dielectric disposed between the semiconductor layer and the gate electrode, wherein the negative fixed charge accumulates holes at a surface of the semiconductor layer facing the back bias dielectric.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: August 26, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghun Jeon, Jong-Hyuk Kang, Heungkyu Park, Jongwook Lee
  • Patent number: 8816348
    Abstract: A trench shielded gate MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage, lower cost and improved performance. The present semiconductor device achieve low Vf and reverse leakage current for embedded Schottky rectifier, having over-voltage protection and avalanche protection between gate and source and between gate and drain.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: August 26, 2014
    Assignee: Force Mos Technology Co., Ltd.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 8809866
    Abstract: An organic EL device as a light emitting device includes: a first light emitting element that is disposed on a first surface of a substrate and that has a first pixel electrode; a second light emitting element that has a second pixel electrode; and an insulating layer that is provided with a first opening which exposes the first pixel electrode and a second opening which exposes the second pixel electrode. Further, in the organic EL device, the first opening is configured so that the insulating layer covers equal to or more than 50% of the circumferential edge portion of the first pixel electrode, and the second opening is configured so that the insulating layer covers less than 50% of the circumferential edge portion of the second pixel electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: August 19, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Masanori Iwasaki, Shin Fujita
  • Patent number: 8803226
    Abstract: A trench gate type MISFET and a diode are formed in a semiconductor substrate. First and second trenches are formed in the semiconductor substrate. A gate electrode is formed in the first trench through a gate insulating film. A dummy gate electrode is formed in the second trench through a dummy gate insulating film. A cathode n+-type semiconductor region and an anode p-type semiconductor region are formed in the semiconductor substrate and the second trench is formed so as to surround the n+-type semiconductor region in a planar view. A part of the anode p-type semiconductor region is formed directly below the n+-type semiconductor region, so that a PN junction is formed between the part of the anode p-type semiconductor region and the n+-type semiconductor region. Thereby a diode is formed. The dummy gate electrode is electrically coupled to one of an anode and a cathode.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 12, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroaki Katou, Taro Moriya, Hiroyoshi Kudou, Satoshi Uchiya
  • Patent number: 8796807
    Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 5, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rolf Stephan, Markus Forsberg, Gert Burbach, Anthony Mowry
  • Patent number: 8796697
    Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
  • Patent number: 8796772
    Abstract: Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Jeng-Ya D. Yeh, Peter J. Vandervoorn, Walid M. Hafez, Chia-Hong Jan, Curtis Tsai, Joodong Park
  • Patent number: 8791512
    Abstract: An imaging device is formed in a semiconductor substrate. The device includes a matrix array of photosites. Each photosite is formed of a semiconductor region for storing charge, a semiconductor region for reading charge specific to said photosite, and a charge transfer circuit configured so as to permit a transfer of charge between the charge storage region and the charge reading region. Each photosite further includes at least one buried first electrode. At least one part of that buried first electrode bounds at least one part of the charge storage region. The charge transfer circuit for each photosite includes at least one second buried electrode.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: July 29, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Francois Roy, Julien Michelot
  • Patent number: 8785270
    Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yi Su, Daniel Ng, Anup Bhalla, Hong Chang, Jongoh Kim, John Chen
  • Patent number: 8785968
    Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: July 22, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Mayank Shrivastava, Harald Gossner
  • Patent number: 8779526
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: July 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Wei Hsu, Po-Cheng Huang, Ren-Peng Huang, Jie-Ning Yang, Chia-Lin Hsu, Teng-Chun Tsai, Chih-Hsun Lin, Chang-Hung Kung, Yen-Ming Chen, Yu-Ting Li
  • Patent number: 8779550
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: July 15, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Patent number: 8779405
    Abstract: A resistive random access memory (ReRAM) cell comprising a first conductive electrode and a dielectric storage material layer over the first conductive electrode. The dielectric storage material layer is conducive to the formation of conductive filaments during the application of a filament forming voltage to the cell. The cell includes a second conductive electrode over the dielectric storage material layer and a layer of conductive nanoclusters (911, 1211) including a plurality of nanoclusters in contact with the dielectric storage material layer and in contact with the first conductive electrode or the second conductive electrode.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Feng Zhou, Frank K. Baker, Jr., Ko-Min Chang, Cheong Min Hong
  • Patent number: 8779516
    Abstract: A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Toshikatsu Kawachi
  • Patent number: 8772850
    Abstract: A method of forming a memory cell including forming trenches in a layered semiconductor structure, each trench having an inner sidewall adjacent a section of the layered semiconductor structure between the trenches and an outer sidewall opposite the inner sidewall. The trenches are filled with polysilicon and the patterning layer is formed over the layered semiconductor structure. An opening is then patterned through the patterning layer, the opening exposing the section of the layered semiconductor structure between the trenches and only a vertical portion of the polysilicon along the inner sidewall of each trench. The layered semiconductor structure is then etched. The patterning layer prevents a second vertical portion of the polysilicon along the outer sidewall of each trench from being removed.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: July 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, David M. Dobuzinsky, Byeong Y. Kim, Munir D. Naeem