With Additional Contacted Control Electrode Patents (Class 257/316)
  • Patent number: 11004947
    Abstract: The object of the present invention is to provide a nonvolatile storage element capable of suppressing retention degradation. A nonvolatile storage element is provided with a semiconductor substrate and a floating gate provided above the semiconductor substrate, in which the floating gate has an area of 30 ?m2 or more.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 11, 2021
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomohiro Gunji, Yuukou Tsushima
  • Patent number: 11004948
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode having a two-sided staircase shape above the substrate, a blocking layer on the gate electrode, a plurality of discrete charge trapping layers each extending laterally on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of discrete channel layers each extending laterally on the tunneling layer. The plurality of charge trapping layers are disposed corresponding to stairs of the two-sided staircase shape of the gate electrode, respectively. The plurality of channel layers are disposed corresponding to the stairs of the two-sided staircase shape, respectively.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: May 11, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Hongbin Zhu
  • Patent number: 11004865
    Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 11, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
  • Patent number: 10998450
    Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yong-Sheng Huang, Ming-Chyi Liu
  • Patent number: 10978159
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sau Ching Wong
  • Patent number: 10978463
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: ShihKuang Yang, Yong-Shiuan Tsair, Po-Wei Liu, Hung-Ling Shih, Yu-Ling Hsu, Chieh-Fei Chiu, Wen-Tuo Huang
  • Patent number: 10964793
    Abstract: Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Ramanathan Gandhi
  • Patent number: 10957707
    Abstract: The dosimeter has two vertical field effect transistors (VFETs), each VFET with a bottom and top source/drain and channel between them. An implanted charge storage region material lies between and in contact with each of the vertical channels. A trapped charge is within the implanted charge storage region. The amount of the trapped charge is related to an amount of radiation that passes through the implanted charge storage region.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 10950703
    Abstract: A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chien Hung Liu
  • Patent number: 10943996
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate and having one of a silicon oxide layer, a silicon nitride layer and multilayers of silicon oxide and silicon nitride, and an erase gate and a select gate. The erase gate and the select gate include a stack of a bottom polysilicon layer and an upper metal layer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei Cheng Wu, Li-Feng Teng
  • Patent number: 10937652
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 10930339
    Abstract: Techniques for voltage bitline high (VBLH) regulation for a computer memory are described herein. An aspect includes generating, by a resistor ladder and a diode compensation footer, a VBLH reference signal based on a high voltage (VPP) in a computer memory module. Another aspect includes regulating a VBLH signal based on the VBLH reference signal. Another aspect includes regulating a wordline driver voltage of the computer memory module based on the VBLH signal.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gregory J. Fredeman, Bishan He, Dinesh Kannambadi, Kenneth J. Reyer, Donald W. Plass
  • Patent number: 10930551
    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hsiang-Wei Liu, Tai-I Yang, Chia-Tien Wu, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 10930671
    Abstract: A vertical memory device includes a substrate having a cell array region and a staircase region. Gate electrodes are spaced apart from each other in first and third directions. A channel extends through the gate electrodes in the first direction on the cell array region. Each of the gate electrodes extends in a second direction. End portions in the second direction of one or more of the gate electrodes form a first stair structure on the staircase region of the substrate. The first stair structure includes first steps, a second step, and a third step sequentially disposed in the third direction. Each of the first steps has a first length, the second step has a second length greater than the first length, and the third step has a third length greater than the second length.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Jun Shin, Bong-Hyun Choi
  • Patent number: 10903233
    Abstract: A semiconductor device according to an embodiment includes first conductors, a second conductor, a first semiconductor, a multi-layered body, and a third conductor. The second conductor is provided above the first conductors. The multi-layered body is provided between the first semiconductor and the first conductors, and between the first semiconductor and the second conductor. The third conductor is provided between the multi-layered body and the second conductor. The first semiconductor includes a first portion facing an uppermost first conductor and a second portion facing the second conductor. The first semiconductor is continuous at least from the first portion to the second portion.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Nakaki
  • Patent number: 10896910
    Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Wen-Yueh Jang
  • Patent number: 10892348
    Abstract: A method of rounding fin-shaped structures includes the following steps. A substrate including fin-shaped structures, and pad oxide caps and pad nitride caps covering the fin-shaped structures from bottom to top are provided. An isolation structure fills between the fin-shaped structures. A removing process is performed to remove a top part of the isolation structure and expose top parts of the fin-shaped structures. An oxidation process is performed to oxidize sidewalls of the top parts of the fin-shaped structures, thereby forming oxidized parts covering sidewalls of the top parts of the fin-shaped structures. The pad nitride caps are removed. The pad oxide caps and the oxidized parts are removed at the same time, thereby forming rounding fin-shaped structures.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Hsuan Chang, Bin-Siang Tsai, Ting-An Chien, Yi-Liang Ye
  • Patent number: 10879174
    Abstract: A semiconductor device includes a substrate, a semiconductor fin, first and second source/drains, a gate electrode, and a gate contact. The semiconductor fin is disposed on the substrate. The first and second source/drains is disposed on the semiconductor fin. The gate electrode is across the semiconductor fin and exposes the first and second source/drains. The gate contact is disposed on the gate electrode and has an elliptical profile with a major axis extending along a lengthwise direction of the gate electrode when viewed from above the gate contact.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 10877673
    Abstract: An apparatus includes an interface circuit and a monitor circuit communicatively coupled to the interface circuit. The monitor circuit is configured to identify a command issued to a memory communicatively coupled to the monitor circuit through the interface circuit, determine whether the command is authorized, and, based on a determination that the command is not authorized, cancel the command.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 29, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Brian J. Marley, Richard E. Wahler
  • Patent number: 10861707
    Abstract: A method for manufacturing a semiconductor device includes forming a sacrificial member on a foundation layer, the sacrificial member extending in a first direction along a front surface of the foundation layer; forming a line and space pattern including a plurality of structures on the foundation layer and the sacrificial member, the structures extending along the front surface of the foundation layer in a second direction crossing the first direction; and forming communication passages between the foundation layer and the structures by selectively removing the sacrificial member via spaces between the structures, the spaces being in communication with each other through the communication passages.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: December 8, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinichi Furukawa
  • Patent number: 10854628
    Abstract: A three-dimensional (3D) memory device and a manufacturing method thereof are provided. The method includes the following steps. An alternating dielectric stack is formed on a substrate. A vertical structure is formed penetrating the alternating dielectric stack in a vertical direction. A bottom dielectric layer of the alternating dielectric stack is removed. An epitaxial layer is formed between the substrate and the alternating dielectric stack after removing the bottom dielectric layer. An insulating layer is formed on the epitaxial layer. The insulating layer is located between the epitaxial layer and the alternating dielectric stack. The influence of the step of forming the vertical structure on the epitaxial layer may be avoided, and defects at the interface between the epitaxial layer and the bottom dielectric layer may be avoided accordingly.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 1, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lan Yao, Lei Xue
  • Patent number: 10855196
    Abstract: A semiconductor device including a main board; a first board provided on the main board; first and second semiconductor elements provided on the first board; a first positive terminal provided on the first board; a first negative terminal provided on the first board; a first output terminal provided on the first board; a second board provided on the main board; third and fourth semiconductor elements provided on the second board; a second positive terminal provided on the second board; a second negative terminal provided on the second board; a second output terminal provided on the second board; a first terminal plate connecting the first positive terminal and the second positive terminal, a second terminal plate connecting the first negative terminal and the second negative terminal, and a third terminal plate connecting the first output terminal and the second output terminal.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: December 1, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Eitaro Miyake, Hiroshi Matsuyama, Tatsuya Hirakawa, Kazuya Kodani
  • Patent number: 10854758
    Abstract: The present invention provides a non-volatile memory and a manufacturing method for the same. In the non-volatile memory, a floating gate structure has a first sharp portion and a second sharp portion, and a corner formed by a side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by a control gate structure. The corner is connected between the first sharp portion and one end of the second sharp portion. A tunneling dielectric layer of an erasing gate structure covers the first sharp portion, the second sharp portion, and a tip part of the corner.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 1, 2020
    Assignee: NEXCHIP SEMICONDUCTOR CO., LTD.
    Inventor: Geeng-Chuan Chern
  • Patent number: 10833127
    Abstract: A method for fabricating a semiconductor device including three-dimensional and planar memory device co-integration includes forming trenches within a horizontal electrode stack to expose portions of a conductive layer, forming vertical electrodes including conductive material within the trenches, forming a planar memory device stack across the device, and patterning the planar memory device stack to form a planar memory device.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger
  • Patent number: 10832966
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Patent number: 10803972
    Abstract: A flash memory module includes a flash memory and a controller. The controller acquires information indicating reliability of monitoring target data of the flash memory, specifies a first cell, which is a cell having a threshold voltage level lower than a threshold voltage level of a corresponding cell in expected value data obtained by correcting an error bit of the monitoring target data, among cells in which error bits have occurred of the monitoring target data when it is determined that the reliability indicated by the acquired information is lower than a predetermined condition, and transmits rewrite correction target cell data, which is data corresponding to data of the first cell in the expected value data, to the flash memory. The flash memory injects an electron into the first cell based on a threshold voltage indicated by the rewrite correction target cell data.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 13, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Akifumi Suzuki, Junji Ogawa
  • Patent number: 10797134
    Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a device isolation film on the substrate. An active region of the substrate is defined by the device isolation film on the substrate and has a first width in a horizontal direction. A gate electrode is on the active region and has a second width equal to or less than the first width of the active region in the horizontal direction. The integrated circuit device includes an insulating spacer over the device isolation film and the active region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung-soo Kim
  • Patent number: 10790292
    Abstract: A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 29, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jinho Kim, Xian Liu, Feng Zhou, Parviz Ghazavi, Steven Lemke, Nhan Do
  • Patent number: 10788375
    Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 29, 2020
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventors: Yakov Roizin, Menachem Vofsy, Alexey Heiman, Yossi Rosenwaks, Klimentiy Shimanovich, Yhonatan Vaknin
  • Patent number: 10777651
    Abstract: Some embodiments disclose a gate stack having a gate (e.g., polysilicon (poly) material) horizontally between shallow trench isolations (STIs), a tungsten silicide (WSix) material over the gate and the STIs, and a tungsten silicon nitride (WSiN) material on a top surface of the WSix material. Some embodiments disclose a gate stack having a gate between STIs, a first WSix material over the gate and the STIs, a WSiN interlayer material on a top surface of the first WSix material, and a second WSix material on a top surface of the WSiN interlayer material. Additional embodiments are disclosed.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yushi Hu, John Mark Meldrim, Eric Blomiley, Everett Allen McTeer, Matthew J. King
  • Patent number: 10756102
    Abstract: A three-dimensional (3D) memory structure and a manufacturing method thereof are provided. The method includes the following steps. A 3D memory unit is formed on a first region of a substrate. A first insulation layer is formed on the first region and a second region of the substrate. A first planarization process is performed to the first insulation layer. The top surface of the first insulation layer on the first region and the top surface of the first insulation layer on the second region are coplanar after the first planarization process. A peripheral circuit is formed on the second region after the first planarization process. The influence of the process for forming the 3D memory unit on the peripheral circuit may be avoided. The manufacturing yield, the electrical performance, and the reliability of the 3D memory structure may be enhanced accordingly.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 25, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zongliang Huo, Deqin Yu, Wenbin Zhou, Yong Hui Gao
  • Patent number: 10734405
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a plurality of electrode films arranged along a first direction with an air gap interposed, the first direction crossing a surface of the substrate, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and each of the electrode films, and a high dielectric constant film provided along an outer surface of the air gap, a relative dielectric constant of the high dielectric constant film being higher than a relative dielectric constant of silicon oxide.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 4, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Nayuta Kariya
  • Patent number: 10734398
    Abstract: In some embodiments, the present disclosure relates to a flash memory structure. The flash memory structure has a source region and a drain region disposed within a substrate. A select gate is disposed over the substrate between the source region and the drain region, and a floating gate is disposed over the substrate between the select gate and the source region. A control gate is disposed over the floating gate. The floating gate has sidewalls that define protrusions extending downward from a lower surface of the floating gate to define a recess within a bottom of the floating gate.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Shu Huang, Ming Chyi Liu
  • Patent number: 10727313
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Jeffrey S. Leib, Jenny Hu, Anindya Dasgupta, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 10726894
    Abstract: The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.
    Type: Grant
    Filed: November 25, 2018
    Date of Patent: July 28, 2020
    Assignee: Nexchip Semiconductor Co., Ltd
    Inventor: Geeng-Chuan Chern
  • Patent number: 10727118
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Tang Wu, Pao-Sheng Chen, Pei-Hsuan Lee, Szu-Hua Wu, Chih-Chien Chi
  • Patent number: 10727248
    Abstract: A first alternating stack of first insulating layers and first sacrificial material layers is formed with a first stepped surfaces located in a staircase region. A second alternating stack of second insulating layers and second sacrificial material layers with second stepped surfaces is formed over the first alternating stack. Areas of the second stepped surfaces overlap areas of the first stepped surfaces to reduce the size of the staircase region. The sacrificial material layers are subsequently replaced with electrically conductive layers. Laterally-insulated staircase region via structures contacting a respective one of the electrically conductive layers may be provided by forming stepped via cavities such that an annular surface of a respective sacrificial material layer is physically exposed at an annular step of the stepped via cavities. Laterally-insulated staircase region via structures may be formed in the stepped via cavities tot provide electrical connections to the electrically conductive layers.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 28, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Michimoto Kaminaga
  • Patent number: 10720522
    Abstract: The invention relates to a device, named four-terminal switch, and a switching lattice comprising four-terminal switches. A four-terminal switch operates and can be fabricated according to the principles of complementary metal oxide semiconductor (CMOS) technology. However, it has four source/drain terminals as opposed to two terminals in conventional MOS devices; it is able to conduct current in two dimensions between four terminals as opposed to one-dimensional current flow in conventional MOS devices; and it is able to form dense switching lattice structures for area efficiency.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: July 21, 2020
    Assignee: ISTANBUL TEKNIK UNIVERSITESI
    Inventors: Mustafa Altun, Serzat Safaltin, Ismail Cevik
  • Patent number: 10720524
    Abstract: A split-gate enhanced power MOS device includes a substrate and an epitaxial layer formed on an upper surface of the substrate. A control gate trench is provided in the epitaxial layer. The control gate trench includes a gate electrode and a split-gate electrode. The gate electrode includes a first gate electrode and a second gate electrode. The first gate electrode and the second gate electrode are located in an upper half portion of the control gate trench and are separated by a first dielectric layer. The first gate electrode and the second gate electrode are located above the split-gate electrode and are separated from the split-gate electrode by a second dielectric layer. The first gate electrode and the second gate electrode are separated from a body region in the epitaxial layer by a gate dielectric.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 21, 2020
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Ming Qiao, Zhengkang Wang, Dong Fang, Ruidi Wang, Bo Zhang
  • Patent number: 10700087
    Abstract: Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 30, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinhai Han, Deenesh Padhi, Er-Xuan Ping, Srinivas Guggilla
  • Patent number: 10692734
    Abstract: Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 23, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jong Mun Kim, Chentsau Chris Ying, He Ren, Srinivas D. Nemani, Ellie Yieh
  • Patent number: 10686073
    Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun Hom Paak, Sung Min Kim
  • Patent number: 10685695
    Abstract: A semiconductor device includes a memory cell region including memory cells arranged along channel holes, the channel holes being provided on a substrate to extend in a direction perpendicular to an upper surface of the substrate, and a peripheral circuit region disposed outside of the memory cell region and including low voltage transistors and high voltage transistors. The low voltage transistors include first transistors including a first gate dielectric layer and a first gate electrode layer including a metal, and the high voltage transistors include second transistors including a second gate dielectric layer having a dielectric constant lower than a dielectric constant of the first gate dielectric layer, and a second gate electrode layer including polysilicon.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Hoon Jeon, Yong Seok Kim, Jun Hee Lim
  • Patent number: 10680113
    Abstract: A thin-film transistor and a manufacturing method thereof, a display substrate and a display device are disclosed. The thin-film transistor includes a control gate, a floating gate, an injection layer, an active layer, a gate electrode, and a source electrode and a drain electrode, which are provided on the base substrate, in which the source electrode and the drain electrode are opposite to each other and electrically connected to the active layer. The injection layer is provided between the floating gate and the active layer; the active layer is provided between the control gate and the gate electrode; and the floating gate is provided between the control gate and the active layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: June 9, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Song, Guoying Wang
  • Patent number: 10672777
    Abstract: A method for manufacturing a semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a silicon substrate. A first structure and a second structure are respectively formed on the silicon substrate and connected to each other. A limiting block is formed on the second structure and near an edge of the second structure beside the first structure. A bottom anti-reflection coating (BARC) layer is formed to blanketly cover the first structure, the second structure and the limiting block, in which the BARC layer includes a low-viscosity material, and the BARC layer overlying the top surface of the second structure has an external surface substantially parallel to the top surface of the second structure. Control gates are formed on the external surface of the BARC layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Kun-Tsang Chuang, Chiang-Ming Chuang, Chia-Yi Tseng
  • Patent number: 10672788
    Abstract: A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 2, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuya Maeda, Hidenori Miyagawa
  • Patent number: 10665282
    Abstract: A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RCi) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 26, 2020
    Assignee: Tohoku University
    Inventors: Hiroki Koike, Tetsuo Endoh
  • Patent number: 10665469
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 10651192
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Yangtze Memory Technologies Co, Ltd.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Patent number: 10651183
    Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 12, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang