With Additional Contacted Control Electrode Patents (Class 257/316)
  • Patent number: 10665469
    Abstract: A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Gordon A. Haller, Tom J. John, Anish A. Khandekar, Christopher Larsen, Kunal Shrotri
  • Patent number: 10665282
    Abstract: A memory circuit (11) includes: a memory cell (MCij) including a variable-resistance element in which a resistance value varies substantially between two levels; a resistance-voltage conversion circuit that converts the resistance value of a memory cell (MCij) to be read into a data voltage; a reference circuit (RCi) including a series circuit of a variable-resistance element and a linear resistor, the variable-resistance element including substantially the same configuration as the configuration of the variable-resistance element included in the memory cell MCij and being set to a lower resistance of two levels; a reference voltage conversion circuit that converts the resistance value of the reference circuit (RCi) into a reference voltage; and a sense amplifier (SA) that determines data stored in the memory cell (MCij) by comparing the data voltage with the reference voltage.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: May 26, 2020
    Assignee: Tohoku University
    Inventors: Hiroki Koike, Tetsuo Endoh
  • Patent number: 10651183
    Abstract: A manufacturing method of a semiconductor device includes: providing a substrate having memory and high voltage regions; sequentially forming a floating gate layer and a hard mask layer on the substrate; patterning the hard mask layer to form a first opening exposing a portion of the floating gate layer in the range of the memory region; patterning the hard mask layer and the floating gate layer to form a second opening overlapped with the high voltage region; performing a first thermal growth process to simultaneously form a first oxide structure on the portion of the floating gate layer exposed by the first opening, and to form a second oxide structure on a portion of the substrate overlapped with the second opening; removing the hard mask layer; and patterning the floating gate layer by using the first oxide structure as a mask.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 12, 2020
    Assignee: United Microelectronics Corp.
    Inventors: Jianjun Yang, Cheng-Hua Yang, Fan-Chi Meng, Chih-Chien Chang, Shen-De Wang
  • Patent number: 10651192
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate, a first tier of conductor layers of a first length comprising a first plurality of conductor layers extending along a first direction over the substrate. The first direction is substantially parallel to a top surface of the substrate. In some embodiments, the memory device also includes at least one connection portion conductively connecting two or more conductor layers of the first tier, and a first metal contact via conductively shared by connected conductor layers of the first tier and connected to a first metal interconnect.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Yangtze Memory Technologies Co, Ltd.
    Inventors: Qiang Xu, Fandong Liu, Zongliang Huo, Zhiliang Xia, Yaohua Yang, Peizhen Hong, Wenyu Hua, Jia He
  • Patent number: 10644146
    Abstract: A vertical bi-directional device includes first and second conductive gates in a semiconductor layer with a first vertical gate oxide on a sidewall of the first conductive gate and a second vertical gate oxide on a sidewall of the second conductive gate. A first heavily doped region of a first conductivity type is at the surface adjacent the first conductive gate, and a second heavily doped region of the first conductive type is at the surface adjacent to the second conductive gate. Doped regions of the first conductivity type extend below the conductive gates towards a substrate. A doped region of a second conductivity type extends laterally from the first vertical gate oxide to the second vertical gate oxide, and a heavily doped region of the second conductivity type is at the surface of the semiconductor layer, between the first and second heavily doped regions of the first conductivity type.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 5, 2020
    Assignee: NXP USA, Inc.
    Inventors: Moaniss Zitouni, Vishnu Khemka, Ganming Qin, Tanuj Saxena, Raghuveer Vankayala Gupta, Mark Edward Gibson
  • Patent number: 10636801
    Abstract: A split-gate non-volatile memory and a fabrication method thereof. The method comprises the following steps: 1) forming a plurality of shallow trench isolation structures in a semiconductor substrate; 2) forming word lines on the semiconductor substrate; 3) forming a source and a drain in the semiconductor substrate, and forming a floating gate on a sidewall of the word line on a side close to the source, a portion of the floating gate that contacts with the word lines presents as a sharp tip; 4) removing part of the word lines by adopting an etching process such that the sharp tip of the top portion of the floating gate is higher than the word lines; 5) forming a tunneling dielectric layer and an erasing gate at the top portion of the floating gate; and 6) forming a conductive plug on the drain and forming metal bit lines on the conductive plug.
    Type: Grant
    Filed: November 25, 2018
    Date of Patent: April 28, 2020
    Inventor: Geeng-Chuan Chern
  • Patent number: 10634715
    Abstract: A method for determining a margin of use of an integrated circuit includes monitoring at least one sensor so as to determine at least one physical parameter representative of use of the integrated circuit, evaluating the at least one physical parameter to determine an instantaneous state of aging of the integrated circuit as a function of the at least one physical parameter, and calculating the margin of use for the integrated circuit from a comparison of the instantaneous state of aging with a presumed state of aging. If operation of the integrated circuit is outside the margin of use, at least one operating performance point of the integrated circuit is adjusted so as to bring operation of the integrated circuit back within the margin of use.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: April 28, 2020
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Vincent Huard, Chittoor Parthasarathy
  • Patent number: 10636809
    Abstract: A semiconductor memory device includes a plurality of electrode films and a plurality of first insulating films stacked alternately along a first direction, a semiconductor member extending in the first direction, a charge storage member provided between the semiconductor member and the electrode films, and a second insulating film provided between the charge storage member and the electrode films. At least one of the plurality of first insulating films includes one or more types of a first material selected from the group consisting of silicon nitride, hafnium oxide, silicon oxynitride, and aluminum oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Patent number: 10636803
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Patent number: 10622450
    Abstract: A 3D memory structure including a modified floating gate and dielectric layer geometry is described. In embodiments, a memory cell includes a channel region and a floating gate where a length of the floating gate along a direction of the channel region is substantially longer than a length of the floating gate along an orthogonal direction along the channel region. A control gate adjacent to the floating gate extends at least as long as the control gate along the direction of the channel region and includes a tapered edge extending away from the channel region towards the control gate. In embodiments, a dielectric layer between the control gate and the floating gate may follow the tapered edge along the floating gate and form a discrete region proximate to the floating gate to at least partially insulate the floating gate from an adjacent memory cell. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Randy Koval, Srikant Jayanti, Hiroyuki Sanda, Meng-Wei Kuo, Srivardhan Gowda, Krishna Parat
  • Patent number: 10622452
    Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 14, 2020
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
  • Patent number: 10608090
    Abstract: A method of forming a memory device with memory cells in a memory area, and logic devices in first and second peripheral areas. The memory cells each include a floating gate, a word line gate and an erase gate, and each logic device includes a gate. The oxide under the word line gate is formed separately from a tunnel oxide between the floating and erase gates, and is also the gate oxide in the first peripheral area. The word line gates, erase gates and gates in both peripheral areas are formed from the same polysilicon layer. The oxide between the erase gate and a source region is thicker than the tunnel oxide, which is thicker than the oxide under the word line gate.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 31, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Chun-Ming Chen, Man-Tang Wu, Chen-Chih Fan, Nhan Do
  • Patent number: 10608005
    Abstract: Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Ronald A. Weimer, Kyu S. Min, Thomas M. Graettinger, Durai Vishak Nirmal Ramaswamy
  • Patent number: 10600795
    Abstract: After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 24, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10593766
    Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10593697
    Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: March 17, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Hu, Teng-Hao Yeh, Yu-Wei Jiang, Kuo-Pin Chang
  • Patent number: 10586595
    Abstract: A method and apparatus are disclosed for reducing the coupling that otherwise can arise between word lines and control gate lines in a flash memory system due to parasitic capacitance and parasitic resistance. The flash memory system comprises an array of flash memory cells organized into rows and columns, where each row is coupled to a word line and a control gate line.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 10, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Xiaozhou Qian, Kai Man Yue, Guang Yan Luo
  • Patent number: 10586801
    Abstract: 3D NAND memory cells can include a source layer, a dielectric layer disposed on the source layer, and a select gate source (SGS) layer disposed on the dielectric layer. A plurality of alternating layers of conducting material and insulating material can be disposed on the SGS layer. A conductive channel can be formed within a cell pillar trench. The conductive channel can be in contact with the source layer and the plurality of alternating layers. The cell pillar trench can be positioned in a substantially perpendicular orientation with respect to the plurality of alternating layers.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Prakash Rau Mokhna Rau, Wesly McKinsey, Rithu Bhonsle
  • Patent number: 10580782
    Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wei Yeeng Ng, Ian Laboriante, Joseph Neil Greeley, Tom J. John, Ho Yee Hui
  • Patent number: 10573721
    Abstract: Protective dielectrics are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory may include a protective dielectric material. A device may include an etch stop material, a first control gate (CG) over the etch stop material, a first CG recess adjacent the first CG, a trench adjacent the first CG recess, and an at least partially oxidized polysilicon on at least a portion of the etch stop material. The at least partially oxidized polysilicon may line a sidewall of the trench and may line the first CG recess.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Hopkins, Darwin Franseda Fan
  • Patent number: 10566335
    Abstract: A semiconductor device includes a stacked structure, channel layers passing through the stacked structure, a well plate located under the stacked structure, a source layer located between the stacked structure and the well plate, a connection structure coupling the channel layers to each other and including a first contact contacting the source layer and a second contact contacting the well plate, and an isolation pattern insulating the source layer and the well plate from each other.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • Patent number: 10566333
    Abstract: A method of fabricating a semiconductor device includes forming a device isolation layer in a substrate to define active regions, forming a conductive layer on the active regions, forming first mask patterns intersecting the active regions on the conductive layer, etching the conductive layer using the first mask patterns as etch masks to form bit lines, growing second mask patterns from top surfaces of the first mask patterns, and performing a patterning process using the second mask patterns as etch masks to form contact holes exposing the active regions between the bit lines.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Heon Lee, Munjun Kim, ByeongJu Bae
  • Patent number: 10553729
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takamitsu Ishihara, Koichi Muraoka
  • Patent number: 10546643
    Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yasushi Nagadomi
  • Patent number: 10541245
    Abstract: A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate, a second dielectric layer disposed between the floating gate and the control gate, sidewall spacers disposed on opposing sides of a stacked structure including the floating gate, the second dielectric layer and the control gate, and an erase gate and a select gate disposed on sides of the stacked structure, respectively. An upper surface of the erase gate and one of the sidewall spacers in contact with the erase gate form an angle ?1 at a contact point of the upper surface of the erase gate and the one of the sidewall spacers, where 90°<?1<115° measured from the upper surface of the erase gate.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: January 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: ShihKuang Yang, Yong-Shiuan Tsair, Po-Wei Liu, Hung-Ling Shih, Yu-Ling Hsu, Chieh-Fei Chiu, Wen-Tuo Huang
  • Patent number: 10535672
    Abstract: A well of a first conductivity type is insulated from a substrate of the same first conductivity type by a structure of a triple well type. The structure includes a trench having an electrically conductive central part enclosed in an insulating sheath. The trench supports a first electrode of a decoupling capacitor, with a second electrode provided by the well.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Abderrezak Marzaki
  • Patent number: 10535675
    Abstract: The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-? metal gate) integrated circuit which includes a high-voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Ya-Chen Kao, Yi Hsien Lu
  • Patent number: 10529728
    Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 7, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Martin Gerhardt
  • Patent number: 10529729
    Abstract: Non-volatile memory devices and methods of fabricating thereof are disclosed herein. An exemplary non-volatile memory device includes a heterostructure disposed over a substrate. A gate structure traverses the heterostructure, such that the gate structure separates a source region and a drain region of the heterostructure and a channel region is defined between the source region and the drain region. The non-volatile memory device further includes a nanocrystal floating gate disposed in the channel region of the heterostructure between a first nanowire and a second nanowire. The first nanowire and the second nanowire extend between the source region and the drain region.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jean-Pierre Colinge, Carlos H Diaz
  • Patent number: 10529733
    Abstract: According to an embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a second insulating film and a plurality of contacts. The stacked body is provided on the substrate and includes a plurality of electrode films stacked with spacing from each other. An end part of the stacked body is shaped like a staircase in which a terrace is formed in each of the plurality of electrode films. The first insulating film is provided on the end part. The second insulating film is provided on the first insulating film and located along the end part. At least part of the second insulating film extends with inclination. The plurality of contacts extends in a stacking direction of the plurality of electrode films in the first insulating film and the second insulating film and is located on the terraces of the plurality of electrode films.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: January 7, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Koichi Yamamoto
  • Patent number: 10522225
    Abstract: A semiconductor device, the device including: a plurality of non-volatile memory cells, where at least one of the non-volatile memory cells includes at least one channel facet, where the at least one channel facet is modified by at least two gates, where the at least one channel facet includes at least two storage locations oriented perpendicular to the at least two gates.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: December 31, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 10504768
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contact structures to deep trench isolation structures and methods of manufacture. The structure includes: a deep trench structure lined with insulator material on sidewalls thereof; conductive material filling the deep trench structure; a local oxide extending above the trench on exposed portions of the insulator material; an interlevel dielectric material on the local oxide and the conductive material filling the deep trench structure; and a contact in the interlevel dielectric material, extending to the conductive material and on a side of the local oxide.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 10, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ke Dong, Purakh R. Verma, Shiang Yang Ong, Namchil Mun
  • Patent number: 10504913
    Abstract: A semiconductor device includes a substrate, a trap storage structure, a control gate, a cap structure, a word line well, a source line, spacers, a gap oxide layer, a word line and a gate oxide layer. The trap storage structure includes a first oxide layer, a nitride layer and a second oxide layer stacked on the substrate. The control gate is directly on the trap storage structure. The cap structure is stacked on the control gate to form a stacked structure. The word line well and the source line are disposed in the substrate at opposite sides of the stacked structure. The spacers are on sidewalls of the stacked structure. The gap oxide layer is on a sidewall of one spacer. The word line is on the word line well and the gap oxide layer. The gate oxide layer is between the word line and the word line well.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Yang, Chung-Jen Huang
  • Patent number: 10504917
    Abstract: An array of elevationally-extending strings of memory cells comprises a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control-gate regions. Charge-storage material of individual memory cells extend elevationally along individual of the control-gate regions of the wordline levels and do not extend elevationally along the insulative levels. A charge-blocking region of the individual memory cells extends elevationally along the individual control-gate regions of the wordline levels laterally through which charge migration between the individual control-gate regions and the charge-storage material is blocked. Channel material extends elevationally along the stack and is laterally spaced from the charge-storage material by insulative charge-passage material.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Richard J. Hill, John A. Smythe
  • Patent number: 10497626
    Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Chia-Lin Hsu
  • Patent number: 10461094
    Abstract: A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: October 29, 2019
    Assignee: Trinandable S.r.l.
    Inventor: Sabrina Barbato
  • Patent number: 10453522
    Abstract: Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semicoductor Manufacturing Co., Ltd.
    Inventors: Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge, Ta-Pen Guo
  • Patent number: 10453745
    Abstract: A semiconductor device is provided. The semiconductor device includes a stack structure comprising insulating patterns and electrode structures alternately stacked on a substrate, and a vertical channel structure vertically penetrating the stack structure. Each of the electrode structures includes a conductive pattern having a first sidewall and a second sidewall opposite to the first sidewall, a first etching prevention pattern on the first sidewall, and a second etching prevention pattern on the second sidewall.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hoon Choi, Jung Ho Kim, Dongkyum Kim, Seulye Kim, Jintae Noh, Hyun-Jin Shin, SeungHyun Lim
  • Patent number: 10453855
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more charge trap structures for use in a variety of electronic systems and devices, where each charge trap structure includes a dielectric barrier between a gate and a blocking dielectric on a charge trap region of the charge trap structure. In various embodiments, a void is located between the charge trap region and a region on which the charge trap structure is disposed. In various embodiments, a tunnel region separating a charge trap region from a semiconductor pillar of a charge trap structure, can be arranged such that the tunnel region and the semiconductor pillar are boundaries of a void. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Chris M Carlson, Ugo Russo
  • Patent number: 10446569
    Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tamotsu Ogata
  • Patent number: 10415605
    Abstract: In one embodiment, a computer-implemented method for calculating the price of a corporate loan comprises receiving, by a server, a first data input regarding a particular corporate loan; receiving, by the server, a second data input regarding market data; generating a pricing lattice for the corporate loan, wherein the pricing lattice has a first axis for a credit rating and a second axis for a time period; and deriving, by a server, using backward induction, a value for the corporate loan.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: September 17, 2019
    Assignee: Citigroup Global Markets, Inc.
    Inventor: Terry Benzschawel
  • Patent number: 10377203
    Abstract: The twist axle assembly includes a pair of spaced apart trailing arms and a twist beam of which extends in a first direction between the trailing arms. The twist beam includes a pair of end portions and a middle portion. The twist beam further has a pair of side walls and at least one additional wall that extends between the side walls. The side walls in the middle portion are generally parallel with the side walls of the end portions. The twist beam is generally hour-glass shaped with the middle portion having a first width and the end portions have a greater second width. The twist beam also tapers from the first width of the middle portion to the second widths of the end portions for gradually increasing a torsional stiffness from the middle portion to the end portions.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: August 13, 2019
    Assignee: Magna International Inc.
    Inventors: Abhinand Chelikani, Patrick Daniel Moritz, Johannes Peter Halbauer, Sukhdeep Singh, Kevin Richard Langworthy
  • Patent number: 10381088
    Abstract: A memory device that generates a unique identifying number, and includes a plurality of memory cells and a controller. Each of the memory cells includes first and second regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the first and second regions, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region. The controller is configured to apply one or more positive voltages to the first regions of the memory cells while the memory cells are in a subthreshold state for generating leakage current through each of the channel regions, measure the leakage currents, and generate a number based on the measured leakage currents.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 13, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Vipin Tiwari, Mark Reiten
  • Patent number: 10347660
    Abstract: The present disclosure discloses an array substrate, the array substrate comprises a substrate as well as a thin film transistor and a pixel electrode formed on the substrate, wherein the top of the thin film transistor is formed a floating gate electrode, at least portion of the floating gate electrode and the pixel electrode are made of the same material. The present disclosure also discloses a manufacturing method of an array substrate. Through this way, the present disclosure simultaneously forms a floating gate electrode in the manufacturing process of the pixel electrode, the pixel electrode and the floating gate electrode is formed by a mask, there is no need to add a mask, thus achieving the manufacture of the dual gate thin film transistor and the array substrate, briefing the process, reducing the production costs.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 9, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yang Liu
  • Patent number: 10340010
    Abstract: In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 2, 2019
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari, Nhan Do
  • Patent number: 10332875
    Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: June 25, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Ping Chen, Chien-Hung Chen
  • Patent number: 10332597
    Abstract: A method of forming a FG OTP/MTP cell with a P+ drain junction at the NCAP region and the resulting device are provided. Embodiments include forming MVPW regions laterally separated in a p-sub; forming a MVNW region in the p-sub between the MVPW regions; forming a first RX, a second RX, and a third RX in the MVPW and MVNW regions, respectively; forming a first and a second pair of floating gates separated over and perpendicular to the first and second RX and the second and third RX, respectively; forming a N+ source region between and adjacent to each FG of the first and the second pair in the second RX; and forming a pair of P+ drain regions in the second RX, each P+ drain region adjacent to a FG of the first pair and a FG of the second pair and remote from the N+ source region.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: June 25, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shyue Seng Tan, Danny Pak-Chum Shum, Eng Huat Toh
  • Patent number: 10319728
    Abstract: In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 11, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chaw Sing Ho, Reynaldo V. Villavelez, Xin Ping Cao
  • Patent number: 10312252
    Abstract: A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 4, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiyuki Kawashima
  • Patent number: 10311958
    Abstract: A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do