PLATING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PLATE PROCESSING SYSTEM

Abstract

A plating film is formed by the steps of applying a direct current between a cathode and an anode (S10); superimposing an alternating current component on the direct current between the cathode and the anode and detecting a displacement current flowing between the cathode and the anode (S12 to S16); calculating a variation of a surface area of the plating film based on the displacement current (S18 and S20); and controlling the value of the direct current based on the variation of the surface area of the plating film so that the local area current density for the surface area does not change (S22 and S24). Consequently favorable film properties are provided to the plating film.

Description

The present application is based on Japanese Patent Application No. 2008-090250.

BACKGROUND OF THE INVENTION

The present invention relates to a plating method, a semiconductor device manufacturing method and a plate processing system.

As finer wiring patterns are provided as a result of providing smaller design rules for copper wiring-used semiconductor devices, there is an increasing demand for enhancing the performance of filling vias and trenches by means of a copper plating process. Copper wirings are formed by a damascene process. In a damascene process, recesses such as interconnect trenches and via holes are formed in an insulating film such as an interlayer insulating film, a barrier metal film is formed in the recesses, a thin film containing copper is formed on the barrier metal film as a seed film, the recesses are filled in with a copper film by means of plating using the seed film as a cathode electrode for electrolytic plating, and -the portions of barrier metal film, the seed film and the plating copper film that are exposed to the outside of the recesses are removed by means of chemical mechanical polishing (CMP).

Japanese Patent Laid-Open No. 2005-264271 describes a semiconductor device manufacturing method including the steps of: acquiring a proportion of fine recesses having a width not exceeding a first reference width in a layer formed with a plurality of recesses with respect to the layer; determining an integrated current amount to be supplied for filling the plurality of recesses with the conductive material, according to the proportion; and forming a conductive pattern by electrolytic plating based on the integrated current amount. It states that the method enables formation of an electrolytic plating film with a proper film thickness.

Japanese Patent Laid-Open No. 2006-283151 describes the process of applying a direct current electric field with an alternating current electric field having a frequency of not less than 100 Hz superimposed thereon to a semiconductor substrate including an insulating film with a trench pattern and a metal layer in the trench pattern to form a metal film on the metal layer.

Japanese Patent Laid-Open No. 2007-23368 describes a technique for formation of filled vias in which when a region whose dimensions on a plane perpendicular to the axis of each filled via vary and whose conductor crystal grain sizes are required to be substantially uniform, a current supplied to a surface of a conductor that is being formed, the surface being exposed to a plating solution, is increased according to predetermined conditions following expansion of the area of the exposed surface to maintain the current density of the current supplied to the exposed surface.

Japanese Patent Laid-Open No. 2001-123298 describes a technique in which the relational expression between the electrode potential and the current density is obtained in advance using an electrode made of the same material as that of an object to be plated, the object to be plated is polarized at an arbitrary potential or current value in a plating bath, the current value and potential in this condition are obtained, the area of the object to be plated is calculated from the relational expression, and the current value and the potential, and electrolytic plating is performed at a current value enabling provision of plating with a predetermined film thickness based on the calculated area.

However, the present inventors have noticed the following problems arising when plating is performed using these techniques.

With the miniaturization of devices, numerous fine recesses are formed, and thus, a plating film especially at the beginning of plating has a surface area increased by the amount of recesses and projections. As the surface area is increased, the current density on the seed film surface is decreased. Since the plating film growth rate is proportional to the current density, where the surface area is large, the film growth rate will be decreased, which may cause problems such as film quality deterioration including, e.g., void formation. Furthermore, the surface area is decreased during plating film forming, which may cause problems in deterioration of filling capability and film quality. Accordingly, control of the current density according to the surface area is needed. However, conventionally, it has been impossible to control the current density substantially in real time according to a variation of the plating film.

SUMMARY

The present Invention provides a plating method including the steps of:

applying a direct current between a cathode and an anode to form a plating film on the cathode;

superimposing an alternating current component on the direct current between the cathode and the anode, and detecting a displacement current flowing between the cathode and the anode;

calculating a variation of the surface area of the plating film based on the displacement current; and

controlling a value of the direct current based on the variation of the surface area of the plating film so that a current density for the plating film does not change in the step of forming a plating film.

The present invention provides a semiconductor device manufacturing method, the method including a plating step of filling a plurality of recesses provided in an insulating film formed on a substrate with a conductive material via plate processing,

the plating processing step including the steps of:

applying a direct current between a cathode and an anode to form a plating film on the conductive material formed on a surface of the recesses, using the conductive material as the cathode;

superimposing an alternating current component on the direct current between the cathode and the anode, and detecting a displacement current flowing between the cathode and the anode;

calculating a variation of the surface area of the plating film based on the displacement current; and

controlling a value of the direct current based on the variation of the surface area of the plating film so that a current density for the plating film does riot change in the step of forming a plating film.

The present invention provides a plate processing system including:

a direct current source that applies a direct current between a cathode and an anode to form a plating film on the cathode;

an alternating current source that superimposes an alternating current component on the direct current between the cathode and the anode;

a surface area calculation unit that detects a displacement current flowing between the cathode and the anode, based on the alternating current component and calculates a variation of the surface area of the plating film that is being subjected to plate processing, based on the displacement current; and

a current control unit that controls a current value of the direct current based on the variation of the surface area of the plating film so that a current density for the plating film that is being subjected to the plate processing does not change.

In the plating method, the semiconductor device manufacturing method and the plate processing system according to the present invention, the direct current for plate processing is changed based on a variation of the surface area of the plating film during plate processing, and thus, it is possible to control the current density substantially in real time so as to be constant. Consequently, the properties, such as, e.g., grain diameter and/or orientation, of the plating film to be formed can also be made to be uniform, enabling provision of favorable film properties. Here, the alternating current component can be a sine wave or a triangle wave.

Any combinations of the aforementioned elements and any methods, apparatuses, systems, recording mediums and computer programs, etc., to which the spirit of the present invention is applied are effective as aspects of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

FIGS. 1A to 1C are cross-sectional process diagrams illustrating a procedure of manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a schematic view of a configuration of an electrochemical processing apparatus according to an embodiment of the present invention;

FIGS. 3A and 3B are diagrams illustrating a state in which a current is applied between an anode and a cathode in the electrochemical processing apparatus illustrated in FIG. 2;

FIGS. 4A and 4B are diagrams schematically illustrating a voltage value V of an alternating current applied from an alternating current source and a current value I of a displacement current;

FIG. 5 is a flowchart illustrating a processing procedure of plate processing according to an embodiment of the present invention;

FIG. 6 is a diagram illustrating an example configuration of a plate processing system according to an embodiment of the present invention, which includes an electrochemical processing apparatus and a control system.

FIG. 7 is a diagram illustrating another example configuration of a plate processing system according to an embodiment of the present invention, which includes an electrochemical processing apparatus and a control system;

FIGS. 8A, 8B, 8C and 8D are diagrams illustrating a timing control unit, which is illustrated in FIG. 7, controlling timing for changing a current value of a current applied from a direct current source; and

FIG. 9 is a flowchart illustrating a processing procedure of a plate processing system according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all of the drawings, similar components are provided with the same reference numerals, and the description thereof will not be repeated as appropriate.

FIGS. 1A to 1C are cross-sectional process diagrams illustrating a procedure of manufacturing a semiconductor device 200 according to an embodiment of the present invention.

In the present embodiment, the process of forming a wiring in an interlayer insulating film 206 by means of a damascene process will be described.

A semiconductor device 200 includes a semiconductor substrate (substrate) 202 with transistors, etc., formed therein, an interlayer insulating film 204 formed on the semiconductor substrate 202 and an interlayer insulating film 206 (insulating film) formed on the interlayer insulating film 204. In the interlayer insulating film 204 and the interlayer insulating film 206, wirings and vias are formed.

In the semiconductor device 200 configured as described above, first, interconnect trenches 208 are formed in the interlayer insulating film 206. Here, as illustrated in the Figures, a plurality of interconnect trenches 208 (recesses) having different wiring widths are formed in the interlayer insulating film 206.

The procedure for filling such interconnect trenches 208 with a wiring material will be described below. First, a barrier metal film is formed in the interconnect trenches 208 of the interlayer insulating film 206. The barrier metal film may be of a material used for a barrier metal film for ordinary copper wiring, such as TaN/Ta, for example. Subsequently, a seed film (conductive material) for plating is formed on the barrier film. Here, the seed film may be, e.g., a copper film formed by, e.g., a CVD process.

Subsequently, plate processing is performed. In the present embodiment, a plating solution may be the same one as that is used for forming a plating film for ordinary copper wiring formation. In the present embodiment, plate processing is performed through a first step for filling a fine pattern and a second step performed at a current value for plating, which is higher than that of the first step.

In the present embodiment, plate processing is performed while calculating a variation of the surface area of the plating film. Then, the current value of the direct current for forming the plating film is changed according to the variation of the surface area of the plating film, and at each of the first step and the second step, plate processing is performed so that the local area current density (A/wf), which is a value obtained by dividing the current value by the area ratio of the surface to be plated to the flat wafer surface, is substantially constant. The procedure according to the present embodiment is different from ordinary procedures on this point.

For example, where the wafer has a diameter of 300 mm, at the first step, the local area current density can be made to be 1 to 10 A/wf. Also, at the second step, the local area current density can be made to be 20 to 50 A/wf. The local area current density can arbitrarily be changed according to, e.g., the wafer size.

FIG. 2 is a schematic view illustrating the configuration of an electrochemical processing apparatus 100 according to the present embodiment. The electrochemical processing apparatus 100 includes a chamber 101, and an anode 102 arranged in the chamber 101 Also, the chamber 101 contains a plating solution 104. The plating solution 104 may include, e.g., a copper sulfate solution The plating solution 104 may contain a leveler, an accelerator and a suppressor, etc, as additives. Also, although not illustrated in the figure, the electrochemical processing apparatus 100 includes a mounting table for mounting the semiconductor device 200, which is a substrate to be processed, and the semiconductor device 200 is placed on the mounting table. Here, the copper film 210 (seed film) of the semiconductor device 200 functions as a cathode 106. Also, although not illustrated in the figure, between the anode 102 and the cathode 106, an ion exchange film, etc., can be provided.

The electrochemical processing apparatus 100 further includes a direct current source 150 that applies a direct current between the anode 102 and the cathode 106, an alternating current source 152 that applies an alternating current, which is to be superimposed on the direct current, and an ammeter 154 that measures a current flowing between the anode 102 and the cathode 106.

FIG. 3 is a diagram illustrating a state in which a current is applied between the anode 102 and the cathode 106 in such an electrochemical processing apparatus 100. First, when a direct current is applied between the anode 102 and the cathode 106, as illustrated in FIG. 3A, cations such as copper ions in the plating solution 104 adhere to the surface of the cathode 106, forming an electrical double layer. Since this electrical double layer is formed on the surface of the cathode 106, the capacitance value varies according to the surface area of the cathode 106. In other words, when, with the progress of plating, the recesses are getting filled, thereby the surface area of the plating film varying, the capacitance value of the electrical double layer also varies. Accordingly, calculation of the capacitance value of the electrical double layer enables calculation of the surface area of the plating film based on the capacitance value.

FIG. 3B is a diagram illustrating a current path when a direct current having a current value I0 with an alternating current having a voltage value V superimposed thereon is applied between the anode 102 and the cathode 106. Here, the resistance of the anode 102 is RA, the resistance of the interconnect trenches 208 is RC, the resistance of the plating solution 104 is RE, the capacitance of the electrical double layer on the surface of the cathode 106 is C, and a resistance component parallel to the capacitance C is r. As a result of the superimposition of the alternating current, a displacement current (current value I), which depends on the capacitance of the electrical double layer on the surface of the cathode 106, is generated. The alternating current applied from the alternating current source 152 may have, for example, a sine wave of 0.005 to 5 V. Also, the alternating current may have a frequency of not less than 10 kHz, more preferably, around 100 kHz to 1 MHz. As a result of the alternating current component having a high frequency as described above, the effect of the displacement current generated by changing the current value of the direct current during plate processing can be reduced.

In this case, formulae (1) and (2) below can be established.

$\begin{array}{cc}\left[\mathrm{Formula}1\right]& \\ \frac{I}{V}=\frac{1+{\omega }^2r^2C^2}{\sqrt{{\left(r+R+{\omega }^2{\mathrm{Rr}}^2C^2\right)}^2+{\omega }^2r^4C^2}}{}^{-\varphi }& \left(1\right)\\ \left[\mathrm{Formula}2\right]& \\ \varphi ={\tan }^{-1}\frac{\omega r^2C}{r+R+{\omega }^2{\mathrm{Rr}}^2C^2}& \left(2\right)\end{array}$

The current value I of the displacement current can be calculated by deducting I0 from the current value detected by the ammeter 154. Also, R=RA+RE+RC. R can be approximated to the value of RE, and can be assumed to be substantially constant during plate processing. Since ω=2πf, the value of ω can be calculated from the frequency f of the alternating current to be superimposed.

FIG. 4 is a diagram schematically illustrating the voltage value V of the alternating current applied from the alternating current source 152 and the current value I of the displacement current. Here, the value of φ can be calculated from the phase difference between the voltage value V of the alternating current and the current value I of the displacement current. Here, the value of φ is increased as time advances, providing the relationship of φ1<φ2<φ3. The value of the capacitance C and the value of the resistance r can be obtained by assigning the values of V, I, R and φ to formulae (1) and (2) above. For the value of φ, the average value of a plurality of the values of φ (for example, φ1 to φ3) for a predetermined period of time can be used. Here, the predetermined period of time may arbitrarily be determined according to, for example, the frequency of the alternating current and the time of filling the recesses such as interconnect trenches. The predetermined period of time may be, for example, around 2 to 100 times the reciprocal of the frequency of the alternating current (i.e., the cycle) Where the cycle is sufficiently short relative to the time of filling the recesses, the predetermined period of time may also be 100 times or more the cycle.

Here, it is possible that a similar measurement is performed assuming that the surface area of the wafer with no recesses is S0 and the capacitance C0 in this condition is measured, thereby obtaining the relationship between the surface area S0 and the capacitance C0 in advance. The value S0 of the surface area of the wafer with no recesses may be obtained from either the design data or actual measurement data. As a result of comparing this value with the capacitance C measured as described above, the surface area S of the plating film at that moment can be calculated. According to the surface area S, the current value I0 of the direct current applied from the direct current source 150 is changed to make the local area current density at each step constant. Consequently, the properties, such as grain diameter and/or orientation, of the plating film to be formed may be made to be uniform, enabling provision of favorable film properties.

It is possible to perform the above-described processing, for example, until the end of the first step in which the surface area S has a large variation. It is also possible to change the value of the direct current only when the variation of the surface area of the plating film exceeds a predetermined reference value. Furthermore, it is possible to terminate the processing when the variation of the surface area of the plating film becomes lower than a predetermined reference value since the variation of the surface area of the plating film gradually becomes smaller after the recesses being filled.

FIG. 5 is a flowchart illustrating the procedure of this processing. First, a direct current is applied from the direct current source 150 (S10). Subsequently, an alternating current component is applied from the alternating current source 152 (S12) In this condition, the current value is measured by means of the ammeter 154 (S14). The measured current value is corrected using the current value I0 of the current applied from the direct current source 150 to calculate the current value I, and the phase difference φ between the current value I and the alternating current component applied from the alternating current source 152 is detected (S16). Subsequently, the capacitance C is calculated based on the phase difference φ (S18). Then, the surface area S is calculated based on the capacitance value C (S20). Subsequently, according to the variation of the surface area S, a new current value I0 for the direct current applied from the direct current source 150 is determined (S22), the current value of the current applied from the direct current source 150 is changed to the new current value I0 determined at step S22, and the direct current is applied (S24). As a result of repeating the aforementioned processing, a plating film can be formed with the current density kept constant.

After the processing at step S24, the subsequent current value correction according to calculation of the surface area ratio halts until fluctuations in the displacement current, which have occurred as a result of changing the direct current value, disappears. Consequently, the fluctuations can be prevented from being reflected in calculation of the surface area ratio. As a result of the alternating current to be superimposed having a frequency of no less than 10 kHz, more preferably, around 100 kHz to 1 MHz as described above, the effect of fluctuations in the displacement current, which have occurred as a result of changing the direct current value, can be reduced/enabling the current value correction processing to be successively performed without halting.

FIG. 6 is a diagram illustrating the configuration of a plate processing system 180 including the electrochemical processing apparatus 100 and a control system 160 that performs the above-described processing. The plate processing system 180 further includes a control system 160 in addition to the above-described configuration of the electrochemical processing apparatus 100. The control system 160 includes a feedback circuit that calculates a current value for making a local area current density constant according to the surface area of the plating film, and feeds the calculated current value back to a direct current source 150. More specifically, the control system 160 includes a surface area calculation unit 162, a current value calculation unit 164, a current control unit 166, and a setting storage unit 170.

The setting storage unit 170 stores, for example, the current value I0 of a direct current applied from the direct current source 150, the voltage value V and frequency of an alternating current applied from an alternating current source 152, and setting information such as the relationship between a capacitance C0 and a surface area S0 obtained in advance by performing similar measurement using a wafer with no recesses. The setting storage unit 170 also stores various kinds of calculation formulae, etc.

The surface area calculation unit 162 calculates the current value I of a displacement current from a value measured by the ammeter 154. Also, it calculates the surface area S of a plating film from the current value I of the displacement current with reference to the setting storage unit 170.

The current value calculation unit 164 determines the current value of the direct current applied from the direct current source 150 based on the surface area S of the plating film calculated by the surface area calculation unit 162 so that the local area current density is constant. When the current value calculation unit 164 determines a new current value, such information is stored in the setting storage unit 170.

The current control unit 166 actually controls the direct current source 150 so that the direct current of the current value determined by the current value calculation unit 164 is applied from the direct current source 150.

FIG. 7 is a diagram illustrating another example configuration of the plate processing system 180 illustrated in FIG. 6. The control system 160 further includes a timing control unit 168 in addition to the configuration illustrated in FIG. 6. The timing control unit 168 controls the timing for feedback to the direct current source 150.

FIGS. 8A to 8D are diagrams illustrating timing control performed by the timing control unit 168. FIG. 8A indicates the voltage value V of the alternating current applied from the alternating current source 152, FIG. 8B indicates the current value I of the displacement current, and FIG. 8C indicates timings for changing the current value I0 of the direct current applied from the direct current source 150.

As illustrated in FIGS. 8B and 8C, immediately after changing the current value I0 of the direct current applied from the direct current source 150, fluctuations in the current value I of the displacement current occur based on the change of the current value I0 of the direct current. Thus, even though the current value I of the displacement current is measured in this duration, a correct phase difference φ cannot be obtained. Accordingly, in the present embodiment, during the time from the timing control unit 168 changing the current value I0 of the direct current until the elapse of a predetermined period of time, control is performed so that monitoring for detecting the phase difference φ is not performed. Here, monitoring being not performed means that the current value I of the displacement current during this predetermined period of time is not used as the basis for calculating the phase difference φ. Here, the predetermined period of time is around 0.1 to 1000 msec, although it varies according to, e.g., the resistance values of the respective components and/or the capacitance value of the electrical double layer.

FIG. 9 is a flowchart illustrating the processing procedure of the plate processing system 180 illustrated in FIG. 7.

First, a direct current is applied from the direct current source 150 (S100). Subsequently, an alternating current component is applied from the alternating current source 152 (S102). In this condition, the current value is measured by the ammeter 154 (S104) The surface area calculation unit 162 corrects the current value measured by the ammeter 154 using the current value I0 of the direct current applied from the direct current source 150 to calculate the current value I, and detects the phase difference φ between the current value I and the alternating current applied from the alternating current source 152 (S106). Subsequently, the surface area calculation unit 162 calculates the capacitance value C based on the phase difference φ (S108). Then, the surface area calculation unit 162 calculates the surface area S based on the capacitance value C (S110) Subsequently, the current control unit 166 determines whether or not to change the current value of the direct current (S112) The determination can be made based on, for example, whether or not plate processing at the first step has finished, or whether or riot the variation of the surface area of the plating film exceeds a predetermined reference value.

If it is determined to change the current value of the direct current (S112: YES), the current value calculation unit 164 determines a new current value I0 for the direct current applied from the direct current source 150, according to the variation of the surface area S (S114), and the current control unit 166 controls the direct current source 150 to change the current value applied from the direct current source 150 to the new current value I0 determined at step S114, and makes the direct current with the current value I0 flow (S116).

Subsequently, whether or not to terminate the processing (S118) is determined, and if it is determined not to terminate the processing (S118: NO), the timing control unit 168 determines whether or not the predetermined period of time has passed from the change of the value of the direct current (S120), and if it is determined that the predetermined period of time has passed (S120: YES), the processing returns to step S104, and similar processing is repeated.

Meanwhile, if it is determined at step S112 not to change the value of the direct current (S112: NO), whether or not to terminate the processing is determined (S122), and if it is determined not to terminate the processing (S122: NO), the processing returns to step S104, and similar processing is repeated. As a result of repeating the above-described processing, a plating film can be formed with the current density kept constant.

The respective components of the control system 160 in FIGS. 6 and 7 are illustrated riot as hardware components, but as functional blocks. The respective components of the control system 160 can be provided by an arbitrary combination of hardware and software mainly including an arbitrary computer CPU, a memory, programs for providing the components in these figures, the programs being loaded in the memory, a storage unit, such as a hard disk that stores these programs, and a network connection interface. It should be understood by persons skilled in the art that various modifications are possible for the method and apparatus for providing the components.

Next, advantageous effects of the plating method, the semiconductor device manufacturing method and the plate processing system according to the present embodiment will be described. Japanese Patent Laid-Open No. 2006-283151 describes measuring the phrase difference at the beginning of plating to monitor the plating film formation status, thereby obtaining information on inclusion of additives that influence the phase difference and the plating film formation status. However, the information obtained as described above is only used for the subsequent plate processing, and is not used for the processing for making the local area current density constant during the relevant plate processing. Meanwhile, in the plating method, the semiconductor device manufacturing method and the plate processing system according to the present embodiment, a direct current for plate processing is changed during the plate processing, based on a variation of the surface area of the plating film that being subjected to the plate processing. Accordingly, control can he performed substantially in real time so that the current density is made to be constant. Consequently, the properties, such as grain diameter and/or orientation, for example, of the plating film to be formed can be made to be uniform, enabling provision of favorable film properties.

Although embodiments of the present invention have been described above with reference to the drawings, these are examples of the present invention, and various configurations other than those described above can also be employed.

Although the above embodiments have been described using a sine wave as an example of an alternating current component, the alternating current component may be, e.g., a triangle wave.

Although the above embodiments have been described using a procedure for filing a plurality of recesses provided in an insulating film formed on a semiconductor substrate with a conductive material by means of plate processing, as an example, the plating method and the plate processing system according to the present invention can also be applied to plate processing other than that for semiconductor devices.

Claims

1. A plating method comprising the steps of:

applying a direct current between a cathode and an anode to form a plating filter on the cathode;

superimposing an alternating current component on the direct current between the cathode and the anode, and

detecting a displacement current flowing between the cathode and the anode;

calculating a variation of a surface area of the plating film based on the displacement current; and

controlling a value of the direct current based on the variation of the surface area of the plating film so that a current density for the plating film does not change in the step of forming a plating film.

2. The plating method according to claim 1, wherein the step of controlling a value of the direct current comprises controlling timing so as to prevent subsequent processing for changing the direct current from being performed for a predetermined period of time after changing the direct current.

3. The plating method according to claim 1, wherein the step of controlling a value of the direct current comprises changing the value of the direct current when the variation of the surface area of the plating film exceeds a predetermined reference value as a result of the step of calculating a variation of the surface area of the plating film.

4. The plating method according to claim 1, wherein the step of calculating a variation of a surface area of the plating film comprises calculating the variation of the surface area of the plating film based on an average variation value of the displacement current for a predetermined period of time.

5. The plating method according to claim 1, wherein the alternating current component has a frequency of not less than 10 kHz.

6. A semiconductor device manufacturing method, the method comprising a plating step of filling a plurality of recesses provided in an insulating film formed on a substrate with a conductive material via plate processing,

the plating processing step including:

applying a direct current between a cathode and an anode to form a plating film on the conductive material formed on a surface of the recesses, using the conductive material as the cathode;

superimposing an alternating current component on the direct current between the cathode and the anode, and detecting a displacement current flowing between the cathode and the anode;

calculating a variation of a surface area of the plating film based on the displacement current; and

controlling a value of the direct current based on the variation of the surface area of the plating film so that a current density for the plating film does not change in the step of forming a plating film.

7. The semiconductor device manufacturing method according to claim 6, wherein the step of controlling a value of the direct current comprises controlling timing so as to prevent subsequent processing for changing the direct current from being performed for a predetermined period of time after changing the direct current.

8. The semiconductor device manufacturing method according to claim 6, wherein the step of controlling a value of the direct current comprises changing the value of the direct current when the variation of the surface area of the plating film exceeds a predetermined reference value as a result of the step of calculating a variation of the surface area of the plating film.

9. The semiconductor device manufacturing method according to claim 6, wherein the step of calculating a variation of a surface area of the plating film comprises calculating the variation of the surface area of the plating film based on an average variation value of the displacement current for a predetermined period of time.

10. The semiconductor device manufacturing method according to claim 6, wherein the alternating current component has a frequency of not less than 10 kHz.

11. A plate processing system comprising:

a direct current source that applies a direct current between a cathode and an anode to form a plating film on the cathode;

an alternating current source that superimposes an alternating current component on the direct current between the cathode and the anode;

a surface area calculation unit that detects a displacement current flowing between the cathode and the anode, based on the alternating current component and calculates a variation of a surface area of the plating film that is being subjected to plate processing, based on the displacement current; and

a current control unit that controls a current value of the direct current based on the valuation of the surface area of the plating film so that a current density for the plating film that is being subjected to the plate processing does not change.

12. The plate processing system according to claim 11, further comprising a timing control unit that controls timing for performing subsequent processing for changing the direct current after the current control unit changing the direct current.

13. The plate processing system according to claim 11 wherein the current control unit changes the value of the direct current when the variation of the surface area of the plating film calculated by the surface area calculation unit exceeds a predetermined reference value.

14. The plate processing system according to claim 11, wherein the surface area calculation unit calculates the variation of the surface area of the plating film based on an average variation value of the displacement current for a predetermined period of time.

15. The plate processing system according to claim 11, wherein the alternating current component superimposed by the alternating current source has a frequency of not less than 10 kHz.

16. The plate processing system according to claim 11, wherein the cathode comprises a conductive material formed on a surface of a plurality of recesses provided in an insulating film formed on a substrate.