Variable Threshold (e.g., Floating Gate Memory Device) Patents (Class 257/314)
  • Patent number: 10777574
    Abstract: According to one embodiment, in a semiconductor device, a stacked body is disposed above a substrate. In the stacked body, a conductive film and an insulating layer are alternately disposed in a stacking direction. A semiconductor columnar member penetrates the stacked body in a stacking direction. An insulating film surrounds the semiconductor columnar member. The insulating film penetrates the stacked body in the stacking direction. A pattern is disposed at a position adjacent to or close to a region. The region includes a penetration plug. The penetration plug extends from a position same as or above an upper end of the stacked body to a position below a lower end of the stacked body in the stacking direction. The pattern has a quadrangular or disjoined quadrangular shape.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masayuki Shishido, Tatsuya Fujishima, Nozomi Kido, Tomonori Kajino
  • Patent number: 10777575
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Yanli Zhang
  • Patent number: 10770538
    Abstract: A method of forming an electronic device includes forming an opening through a dielectric layer located over a first resistive layer, the first resistive layer having a first sheet resistance. A second resistive layer is deposited over the dielectric layer and into the opening. The second resistive layer has a second sheet resistance different from the first sheet resistance. A portion of the second resistive layer is removed, thereby forming first and second noncontiguous portions of the second resistive layer, wherein the second portion of the second resistive layer contacts the first resistive layer.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Christoph Andreas Othmar Dirnecker, Wolfgang Schwartz, Doug Weiser, Joel Martin Halbert, Joseph Anthony DeSantis, Karsten Jens Spinger
  • Patent number: 10770469
    Abstract: In a method of manufacturing a semiconductor device, the semiconductor device includes a non-volatile memory formed in a memory cell area and a ring structure area surrounding the memory cell area. In the method, a protrusion of a substrate is formed in the ring structure area. The protrusion protrudes from an isolation insulating layer. A high-k dielectric film is formed, thereby covering the protrusion and the isolation insulating layer. A poly silicon film is formed over the high-k dielectric film. The poly silicon film and the high-k dielectric film are patterned. Insulating layers are formed over the patterned poly silicon film and high-k dielectric film, thereby sealing the patterned high-k dielectric film.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chin Wen Chan
  • Patent number: 10763271
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 1, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani, Jayavel Pachamuthu
  • Patent number: 10763275
    Abstract: A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: September 1, 2020
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Huayong Hu, Lei Ye
  • Patent number: 10748929
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 10748630
    Abstract: An artificial neural network device that utilizes analog neuromorphic memory that comprises one or more non-volatile memory arrays. The embodiments comprise improved mechanisms and algorithms for tuning the non-volatile memory arrays such that the floating gates of the memory cells can be quickly and accurately injected with the desired amount of charge to signify an analog value utilized as a weight by the artificial neural network.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Vipin Tiwari, Nhan Do, Steven Lemke, Santosh Hariharan, Stanley Hong
  • Patent number: 10748920
    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of electrode films, a semiconductor member, a tunneling insulating film, a charge storage member, and a blocking insulating film. The plurality of electrode films are arranged to be separated from each other along a first direction. The semiconductor member extends in the first direction. The tunneling insulating film is provided between the semiconductor member and the electrode films. The charge storage member is provided between the tunneling insulating film and the electrode films. The blocking insulating film is provided between the charge storage member and the electrode films. The blocking insulating film includes a first film contacting the charge storage film and including carbon-containing silicon oxide, and a second film contacting the electrode films and including hafnium oxide or aluminum oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Keisuke Nakatsuka
  • Patent number: 10748894
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: August 18, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Kwang-Ho Kim, James Kai, Johann Alsmeier
  • Patent number: 10748923
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
  • Patent number: 10749042
    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk Kim, Dae Hyun Jang, Seung Pil Chung, Sung II Cho
  • Patent number: 10741678
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Carlos H. Diaz, Chih-Sheng Chang, Cheng-Yi Peng, Ling-Yen Yeh, Chien-Hsing Lee
  • Patent number: 10741574
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure including conductive layers stacked on the substrate. Moreover, the semiconductor device includes a dummy structure penetrating a stepped region of the stack structure. A portion of the dummy structure includes a first segment and a second segment. The first segment extends in a first direction in a plane parallel to an upper surface of the substrate. The second segment protrudes from the first segment in a second direction, in the plane, that intersects the first direction.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangyoung Jung, Jongwon Kim, Dongseog Eun, Joonhee Lee
  • Patent number: 10741258
    Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis
  • Patent number: 10734404
    Abstract: A semiconductor device includes a cell structure; n first pad structures formed on one side of the cell structure and each configured to have a step form in which 2n layers form one stage; and n second pad structures formed on the other side of the cell structure each configured to have a step form in which 2n layers form one stage, wherein n is a natural number of 1 or higher, and the first pad structures and the second pad structures have asymmetrical step forms having different heights.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Sung Ik Moon
  • Patent number: 10726924
    Abstract: A semiconductor memory device includes a plurality of bit lines electrically coupled to a memory cell array and extending in a first direction; bit line contact pads formed on a first plane over a substrate and respectively coupled to the bit lines through bit line contacts; and first contact pads formed on the first plane, respectively coupled to the bit line contact pads through redistribution lines, and electrically coupled to a page buffer circuit which is disposed on the substrate, through first contacts, wherein at least two first contact pads corresponding to at least two bit line contact pads which are disposed in a line in a second direction crossing with the first direction are disposed in a line in the first direction.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Dong-Hyuk Kim, Sung-Lae Oh, Soo-Nam Jung
  • Patent number: 10727242
    Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Matthew Park, Joseph Neil Greeley, Chet E. Carter, Martin C. Roberts, Indra V. Chary, Vinayak Shamanna, Ryan Meyer, Paolo Tessariol
  • Patent number: 10727115
    Abstract: Provided is a semiconductor device including a lower layer structure on a substrate, the lower layer structure having different thicknesses on first and second regions of the substrate, the lower layer structure including an electrode layer at a top and an insulating layer thereunder, an etch stop layer on the lower layer structure, an upper layer structure on the etch stop layer, the etch stop layer having an etch selectivity to the upper and lower layer structures, first and second contact plugs filling first and second openings defined in the upper layer structure and the etch stop layer on the first and second regions, respectively, and contacting corresponding electrode layers of the lower layer structure, respectively, such that one of the first and second contact plugs downwardly extends further with respect to a bottom of the etch stop layer than the other one of the first and second contact plugs.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics co., Ltd.
    Inventors: Phil Ouk Nam, Jaeyoung Ahn, Sangsoo Lee
  • Patent number: 10727278
    Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film on a first substrate. The method further includes performing a first process of processing a portion of the first film with plasma of first gas and a second process of removing the portion of the first film with plasma of second gas after the first process.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tsubasa Imamura
  • Patent number: 10720446
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Fei Wang, Chet E. Carter, Ian Laboriante, John D. Hopkins, Kunal Shrotri, Ryan Meyer, Vinayak Shamanna, Kunal R. Parekh, Martin C. Roberts, Matthew Park
  • Patent number: 10714634
    Abstract: A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 14, 2020
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Chien-Sheng Su, Nhan Do
  • Patent number: 10714491
    Abstract: A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: July 14, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chien-Lan Chiu, Chun-Min Cheng
  • Patent number: 10707307
    Abstract: A semiconductor storage device includes a substrate, a plurality of first gate electrodes on the substrate and arranged in a thickness direction of the substrate, and a first semiconductor pillar extending in the thickness direction of the substrate through the plurality of first gate electrodes, the first semiconductor pillar including a first portion facing the plurality of first gate electrodes and a second portion farther from the substrate than the first portion. The semiconductor storage device also includes a second gate electrode on the substrate farther from the substrate than the plurality of first gate electrodes, and a second semiconductor pillar extending in the thickness direction of the substrate through the second gate electrode, and connected to the first semiconductor pillar at the second portion of the first semiconductor pillar. The second portion of the first semiconductor pillar contains carbon (C).
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroyasu Sato
  • Patent number: 10700089
    Abstract: Fabricating a three-dimensional memory device may include forming an alternating stack of insulating layers and sacrificial material layers over a substrate. Stepped surfaces are formed by patterning the alternating stack. Sacrificial pads are formed on physically exposed horizontal surfaces of the sacrificial material layers. A retro-stepped dielectric material portion is formed over the sacrificial pads. After memory stack structures extending through the alternating stack are formed, the sacrificial material layers and the sacrificial pads can be replaced with replacement material portions that include electrically conductive layers. The electrically conductive layers can be formed with thicker end portions. Contact via structures can be formed on the thicker end portions.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naoto Hojo, Takahiro Tabira, Yoshitaka Otsu
  • Patent number: 10685975
    Abstract: A vertical memory device includes a substrate having a peripheral circuit interconnection, lower word lines stacked on the substrate, vertical channel structures passing through the lower word lines, a first cell contact plug including a bottom end lower than a bottom surface of a first lower word line and being connected to the first lower word line, and lower insulating layers and first lower mold patterns positioned beneath the first lower word line and stacked alternately on each other from the substrate.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Seok Cheon Baek
  • Patent number: 10685959
    Abstract: An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 16, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kak Lee, Joon Kim, Bong-hyun Kim, Han-Jin Lim
  • Patent number: 10686046
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 16, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Julien Delalleau
  • Patent number: 10680010
    Abstract: Embodiments of 3D memory devices having zigzag slit structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, an array of memory strings each extending vertically through the memory stack, and a plurality of slit structures laterally dividing the array of memory strings into a plurality of memory regions. Each of the plurality of slit structures extends vertically through the memory stack and extends laterally in a first zigzag pattern in a plan view.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: June 9, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Wenyu Hua
  • Patent number: 10680003
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Jun Chen, Xiaowang Dai, Jifeng Zhu, Qian Tao, Yu Ru Huang, Si Ping Hu, Lan Yao, Li Hong Xiao, A Man Zheng, Kun Bao, Haohao Yang
  • Patent number: 10680037
    Abstract: A cross-point memory array includes a plurality of variable resistance memory cell pillars. Adjacent memory cell pillars are separated by a partially filled gap that includes a buried void. In addition, adjacent memory cell pillars include storage material elements that are at least partially interposed by the buried void.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Cristina Casellato, Fabio Pellizzer
  • Patent number: 10680007
    Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 9, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Jun Shin, Hyun Mog Park, Joong Shik Shin
  • Patent number: 10679985
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, and a semiconductor layer above the memory stack. The channel structure includes a channel plug in a lower portion of the channel structure, a memory film along a sidewall of the channel structure, and a semiconductor channel over the memory film and in contact with the channel plug. The semiconductor layer includes a semiconductor plug above and in contact with the semiconductor channel.
    Type: Grant
    Filed: November 17, 2018
    Date of Patent: June 9, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Shasha Liu, Li Hong Xiao, EnBo Wang, Feng Lu, Qianbin Xu
  • Patent number: 10672655
    Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: June 2, 2020
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Basoene Briggs, Ivan Zyulkov, Katia Devriendt
  • Patent number: 10665510
    Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Alexander Kalnitsky, Kong-Beng Thei
  • Patent number: 10658373
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a split gate stack having a main gate and a select gate and forming a logic gate stack having a logic gate over a semiconductor substrate. The main gate and the logic gate is respectively replaced with a metal memory gate and a metal logic gate, in which the main gate and the logic gate are replaced simultaneously.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 10658230
    Abstract: A semiconductor device includes a comprise a substrate including a main zone and an extension zone, vertical channels on the main zone, and an electrode structure including gate electrodes stacked on the substrate. The vertical channel structures extend in a first direction perpendicular to a top surface of the substrate. The gate electrodes include line regions and contact regions. The line regions extend from the main zone toward the extension zone along a second direction the second direction that is perpendicular to the first direction. The contact regions are on ends of the line regions and are thicker than the line regions. A spacing distance in the second direction between the contact regions is greater than a spacing distance in the first direction between the line regions.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Il Hyun, Semee Jang, Sung Yun Lee
  • Patent number: 10650900
    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shimada, Fumitaka Arai, Tatsuya Kato
  • Patent number: 10650891
    Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Amitava Majumdar, Rajesh Kamana, Hongmei Wang, Shawn D. Lyonsmith, Ervin T. Hill, Zengtao T. Liu, Marlon W. Hug
  • Patent number: 10651187
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a peripheral interconnect layer disposed above the peripheral device, a first source plate disposed above and electrically connected to the peripheral interconnect layer, a first memory stack disposed on the first source plate, a first memory string extending vertically through the first memory stack and in contact with the first source plate, and a first bit line disposed above and electrically connected to the first memory string and the peripheral device.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: May 12, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Jun Liu
  • Patent number: 10651194
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hoon Choi, Sung Gil Kim, Seulye Kim, Jung Ho Kim, Hong Suk Kim, Phil Ouk Nam, Jae Young Ahn, Han Jin Lim
  • Patent number: 10651311
    Abstract: A method includes forming an opening in a dielectric to reveal a protruding semiconductor fin, forming a gate dielectric on sidewalls and a top surface of the protruding semiconductor fin, and forming a conductive diffusion barrier layer over the gate dielectric. The conductive diffusion barrier layer extends into the opening. The method further includes forming a silicon layer over the conductive diffusion barrier layer and extending into the opening, and performing a dry etch on the silicon layer to remove horizontal portions and vertical portions of the silicon layer. After the dry etch, a conductive layer is formed over the conductive diffusion barrier layer and extending into the opening.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Han Fang, Po-Chi Wu
  • Patent number: 10644105
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a channel to conduct current, the channel including a first channel portion and a second channel portion, a first memory cell structure located between a first gate and the first channel portion, a second memory cell structure located between a second gate and the second channel portion, and a void located between the first and second gates and between the first and second memory cell structures.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chris M. Carlson
  • Patent number: 10644020
    Abstract: A three-dimensional semiconductor device includes: A peripheral circuit, distributed on a substrate; a plurality of memory cells above the peripheral circuit, each of which includes: a common source region, between the memory cell and the peripheral circuit; a channel layer, distributed in a direction perpendicular to the surface of the substrate; at least one substrate contact layer, extending horizontally from the central portion of the channel layer parallel to the surface of the substrate, each comprising at least one substrate contact region; a plurality of insulating layers, located on sidewalls of the channel layer; a plurality of control gates, sandwiched between adjacent insulating layers; a gate dielectric layer, located between the channel layer and the control gates; a drain region, located at top of the channel layer; a substrate contact lead-out line, electrically connected to the substrate contact regions; and a bit line wiring, electrically connected to the drain region of each memory cell and
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: May 5, 2020
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Zongliang Huo, Tianchun Ye
  • Patent number: 10636814
    Abstract: A 3D memory device, comprising a plurality of rows of strings of memory cells, each row of strings of memory cells comprising an array of strings of memory cells extending along a first direction, the rows following one another along a second direction. Each string of memory cells comprises a stack of memory cells, and the strings of memory cells of the stack extend in a third direction from a first end to a second end. A source region is provided at the second end of the strings of memory cells. Consecutive rows of strings of memory cells along the second direction are spaced apart from each other of a pitch. Between pairs of strings of a row of memory cells along the second direction there is formed a slit extending in the third direction from the first end down to the source region. The slit has dimension, along the second direction, smaller than, equal to or greater than the pitch, sufficient to the formation, in the slit, of an electrical contact to the source region.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 28, 2020
    Assignee: Trinandable, S.r.l.
    Inventor: Sabrina Barbato
  • Patent number: 10636782
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 10636808
    Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Byoung Taek Kim, Jun Hee Lim
  • Patent number: 10629606
    Abstract: A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nobutoshi Sugawara, Shigeyuki Sugihara
  • Patent number: 10629611
    Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Mitsuteru Mushiga, Hisakazu Otoi, Kenji Sugiura
  • Patent number: 10629801
    Abstract: A laminated structure includes a ferromagnetic layer, a multiferroic layer provided on one surface of the ferromagnetic layer, and a ferroelectric layer which is provided on the multiferroic layer opposite to the ferromagnetic layer and has a permittivity greater than that of the multiferroic layer.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 21, 2020
    Assignee: TDK CORPORATION
    Inventors: Eiji Suzuki, Katsuyuki Nakada, Shogo Yonemura