Variable Threshold (e.g., Floating Gate Memory Device) Patents (Class 257/314)
  • Patent number: 11121141
    Abstract: A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Kun-Tsang Chuang, Hung-Che Liao, Hsin-Chi Chen
  • Patent number: 11119917
    Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 14, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Shyue Seng Tan, Xinshu Cai, Fan Zhang, Soh Yun Siah, Tze Ho Simon Chan
  • Patent number: 11114456
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 7, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Li Hong Xiao
  • Patent number: 11114463
    Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Jun Shin, Hyun Mog Park, Joong Shik Shin
  • Patent number: 11114152
    Abstract: A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventors: Dong Hyuk Kim, Sung Lae Oh, Yeong Taek Lee, Tae Sung Park, Soo Nam Jung
  • Patent number: 11107920
    Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Michael Jackson, Anand Murthy, Glenn Glass, Saurabh Morarka, Chandra Mohapatra
  • Patent number: 11095216
    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: August 17, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yung-Chung Lo, Gang Zhang, Yiping Han, Frederic Bossu, Tsai-Pi Hung, Jae-Hong Chang
  • Patent number: 11088162
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 10, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kotaro Fujii, Satoshi Nagashima, Yumi Nakajima
  • Patent number: 11081493
    Abstract: A method for forming a semiconductor memory device is provided. The method includes forming a sacrificial via in a dielectric layer over a substrate, forming a first active layer over the dielectric layer, forming an insulating layer over the first active layer, and forming a second active layer over the insulating layer. The method also includes forming a trench through the second active layer, the insulating layer and the first active layer and corresponding to the sacrificial via, removing the sacrificial via to form a via hole in the dielectric layer, and filling the trench and the via hole with a conductive material.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Patent number: 11075220
    Abstract: A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 27, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Ken Komiya
  • Patent number: 11075214
    Abstract: An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: July 27, 2021
    Assignee: GREENLIANT IP, LLC
    Inventor: Bing Yeh
  • Patent number: 11069742
    Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line; a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.
    Type: Grant
    Filed: November 23, 2019
    Date of Patent: July 20, 2021
    Assignee: TetraMem Inc.
    Inventor: Ning Ge
  • Patent number: 11069745
    Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: July 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kenichi Murooka
  • Patent number: 11063058
    Abstract: A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 11061146
    Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: July 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeng-Bang Yau, Alexander Reznicek, Karthik Balakrishnan, Bahman Hekmatshoartabari
  • Patent number: 11063063
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 13, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Dong-il Moon, Raghuveer S. Makala, Peng Zhang, Wei Zhao, Ashish Baraskar
  • Patent number: 11056571
    Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ankit Sharma, Akira Goda
  • Patent number: 11050022
    Abstract: A radio frequency (RF) switch includes a heating element and a thermally resistive material adjacent to sides of the heating element. A thermally conductive and electrically insulating material is situated on top of the heating element. A phase-change material (PCM) is situated over the thermally conductive and electrically insulating material. The PCM has an active segment overlying the thermally conductive and electrically insulating material, and passive segments underlying input/output contacts of the RF switch. The RF switch may include a bulk substrate heat spreader, a silicon-on-insulator (SOI) handle wafer heat spreader, or an SOI top semiconductor heat spreader under the heating element.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 29, 2021
    Assignee: Newport Fab, LLC
    Inventors: Nabil El-Hinnawy, Gregory P. Slovin, Jefferson E. Rose, David J. Howard
  • Patent number: 11049808
    Abstract: A semiconductor storage device of an embodiment includes: a stacked body in which a plurality of conductive layers are stacked with an insulating layer interposed therebetween, the stacked body having a memory portion in which a plurality of memory cells are disposed and a stepped portion in which ends of the plurality of conductive layers form a step shape; and a conductive portion which extends in the memory portion in a stacking direction of the stacked body inside the plurality of conductive layers from an uppermost conductive layer among the plurality of conductive layers, extends in the stepped portion in the stacking direction of the stacked body inside at least some layers among the plurality of conductive layers, and extends from the memory portion to the stepped portion in a direction intersecting the stacking direction of the stacked body. A height of the conductive portion in the stepped portion is lower than a height of the conductive portion in the memory portion.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hisashi Nishimura
  • Patent number: 11049875
    Abstract: A semiconductor memory device according to embodiments described herein, includes a first stacked body, a second stacked body, a first memory hole, a second memory hole, and a joint. In the first stacked body, a plurality of first conductive layers and a plurality of first insulating layers are alternately stacked. The second stacked body is disposed above the first stacked body, and a plurality of second conductive layers and a plurality of second insulating layers are alternately stacked therein. The first memory hole extends in the first stacked body in a first direction that is a stacking direction of the first stacked body. The second memory hole extends in the second stacked body in the first direction. The joint communicates the first memory hole and the second memory hole. The joint includes an inner wall surface and a sidewall insulating layer. The inner wall surface has a plane continuous with the inner wall of the first memory hole.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 29, 2021
    Assignee: Kioxia Corporation
    Inventor: Shunsuke Hazue
  • Patent number: 11037830
    Abstract: After the step of polishing, a part of each of each gate electrode is removed such that the upper surface of each gate electrode is located closer than the damaged region formed in the gate insulating film located between the gate electrodes to the main surface of the semiconductor substrate in cross-section view. Thus, it is possible to suppress the occurrence of a short-circuit defect during the operation of the semiconductor device.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 15, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoki Takizawa, Tatsuyoshi Mihara
  • Patent number: 11031069
    Abstract: Techniques are disclosed for writing, programming, holding, maintaining, sampling, sensing, reading and/or determining a data state of a memory cell of a memory cell array, such as a memory cell array having a plurality of memory cells each comprising an electrically floating body transistor. In one aspect, the techniques are directed to controlling and/or operating a semiconductor memory cell having an electrically floating body transistor in which an electrical charge is stored in the body region of the electrically floating body transistor. The techniques may employ bipolar transistor currents to control, write and/or read a data state in such a memory cell. In this regard, the techniques may employ a bipolar transistor current to control, write and/or read a data state in/of the electrically floating body transistor of the memory cell.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 8, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Serguei Okhonin, Mikhail Nagoga
  • Patent number: 11031416
    Abstract: According to one embodiment, a semiconductor storage device includes: a first stacked body in which a plurality of conductive layers are stacked via a first insulating layer, the first stacked body having a first stepped portion and a second stepped portion in which end portions of the plurality of conductive layers are formed in a step shape in a lower layer; a second stacked body in which a plurality of second insulating layers are stacked via a third insulating layer, the second stacked body having a third stepped portion in which end portions of the plurality of second insulating layers in an identical level as the conductive layers forming the first stepped portion are formed in a step shape. The first stepped portion and the third stepped portion oppose each other, and the second stepped portion and the third stepped portion overlap each other at least partially in a top view.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 8, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Maki Miyazaki
  • Patent number: 11024580
    Abstract: Methods and devices are described herein for random cut patterning. A first metal line and a second metal line are formed within a cell of a substrate and extend in a vertical direction. A third metal line and a fourth metal line are formed within the cell and are perpendicular to the first metal line and the second metal line, respectively. A first circular region at one end of the first metal line is formed using a first patterning technique and a second circular region at one end of the second metal line is formed using a second patterning technique. The first circular region is laterally extended using a second patterning technique to form the third metal line and the second circular region is laterally extended using the second patterning technique to form the fourth metal line.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wei Peng, Wei-Cheng Lin, Chih-Ming Lai, Jiann-Tyng Tzeng
  • Patent number: 11023061
    Abstract: A panel is provided, including a first conductive pattern and a second conductive pattern. The first conductive pattern includes a first portion and a second portion; the second conductive pattern connects the first portion to the second portion, and an insulation pattern substantially covering a side surface of the second conductive pattern. The insulation pattern is formed by thermally treating a mask pattern of an insulation material. A horizontal distance between an outer side surface of the insulation pattern and an inner side surface adjacent to the second conductive pattern is less than 3 micrometers.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 1, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Kai Pei
  • Patent number: 11024645
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Yasushi Dowaki, Yuki Kasai, Satoshi Shimizu, Jayavel Pachamuthu
  • Patent number: 11018154
    Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 25, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Chang Lu, Wen-Jer Tsai, Guan-Wei Wu, Yao-Wen Chang
  • Patent number: 11011532
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a plurality of U-shaped memory strings, each of the plurality of U-shaped memory strings including a first columnar body, a second columnar body, and a conductive connection body. The conductive connection body connects the first columnar body and the second columnar body. A plurality of first memory cells are connected in series in the first columnar body and are composed of a plurality of first conductive layers, a first inter-gate insulating film, a plurality of first floating electrodes, a first tunnel insulating film, and a first memory channel layer. The plurality of first floating electrodes are separated from the plurality of first conductive layers by the first inter-gate insulating film. A plurality of second memory cells are connected in series in the second columnar body, similarly to the plurality of first memory cells.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: May 18, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Keiichi Sawa
  • Patent number: 11004864
    Abstract: A semiconductor device includes a stack structure including alternately stacked interlayer insulating layers and electrode patterns. The semiconductor device also includes a plurality of contact plugs connected to the electrode patterns. The semiconductor device further includes a supporting structure penetrating the stack structure between two adjacent contact plugs of the plurality of contact plugs, wherein the supporting structure has a cross section extending in a zigzag shape.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyeok Jun Choi, Jun Yeong Hwang
  • Patent number: 10998326
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Patent number: 10998325
    Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 4, 2021
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Catherine Decobert, Hieu Van Tran, Nhan Do
  • Patent number: 10998336
    Abstract: Some embodiments include an integrated structure having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include primary regions of a first vertical thickness, and terminal projections of a second vertical thickness which is greater than the first vertical thickness. Charge-blocking material is adjacent the terminal projections. Charge-storage material is adjacent the charge-blocking material. Gate-dielectric material is adjacent the charge-storage material. Channel material is adjacent the gate-dielectric material. Some embodiments include NAND memory arrays. Some embodiments include methods of forming integrated structures.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, David Daycock
  • Patent number: 10998331
    Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 4, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Fei Zhou, Yingda Dong, Raghuveer S. Makala
  • Patent number: 10991716
    Abstract: A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Do Yeon Kim, Ki Hong Lee
  • Patent number: 10991717
    Abstract: A vertical memory device may include gate electrodes on a substrate, a merged pattern structure and a cell contact plug. The gate electrodes may be spaced apart in a first direction orthogonal to the substrate, and may extend in a second direction parallel to the substrate. The merged pattern structure may extend in the second direction while merging ends of the gate electrodes of each level. Edges of the merged pattern structure may have a step shape. The merged pattern structure may include pad patterns electrically connected to the gate electrodes. The cell contact plug may extend through the merged pattern structure and be electrically connected to one of the pad patterns. The cell contact plug may be electrically insulated from other gate electrodes. The cell contact plug may contact a conductive material underlying. An upper surface of the cell contact plug may only contact an insulation material.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: April 27, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Cheon Baek
  • Patent number: 10991689
    Abstract: A method includes forming a first region including a pair of first FinFETs and a second region including a pair of second FinFETs on a substrate. Each FinFET includes a metal gate having a first spacer adjacent thereto, and each first FinFET has a gate dielectric that is thicker than a gate dielectric of each second FinFET, such that the first FinFETs can be higher voltage input/output devices. The method forms a first contact between the metal gates of the pair of first FinFETs with a second spacer thereabout, the second spacer contacting a portion of each first spacer. The second spacer thus has a portion extending parallel to the metal gates, and a portion extending perpendicular to the metal gates. A second contact is formed between the metal gates of the pair of second FinFETs, and the second contact devoid of the second spacer.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Abu Naser M. Zainuddin, Christopher D. Sheraw, Sangameshwar Rao Saudari, Wei Ma, Kai Zhao, Bala S Haran
  • Patent number: 10991714
    Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Soo Kim, Jun Hyoung Kim, Si Wan Kim, Kyoung Taek Oh
  • Patent number: 10985177
    Abstract: A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: April 20, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, In Su Park
  • Patent number: 10985252
    Abstract: Some embodiments include a method of forming an integrated assembly. A first stack is formed over a conductive structure. The first stack includes a second layer between first and third layers. The first and third layers are conductive. A first opening is formed through the first stack. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. The second stack has alternating first and second levels. A second opening is formed through the second stack and through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack, through the third layer, and to the second layer. The second layer is removed, forming a conduit. Second semiconductor material is formed within the conduit. Dopant is out-diffused from the second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gordon A. Haller
  • Patent number: 10971685
    Abstract: A selective device includes a first electrode, a second electrode, a switch device, and a non-linear resistive device. The second electrode is disposed to face the first electrode. The switch device is provided between the first electrode and the second electrode. The non-linear resistive device contains one or more of boron (B), silicon (Si), and carbon (C). The non-linear resistive device is coupled to the switch device in series.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 6, 2021
    Assignee: SONY CORPORATION
    Inventors: Kazuhiro Ohba, Minoru Ikarashi
  • Patent number: 10971521
    Abstract: A three-dimensional semiconductor device includes: a peripheral circuit structure disposed on a lower substrate, and including an internal peripheral pad portion; an upper substrate disposed on the peripheral circuit structure; a stack structure disposed on the upper substrate, and including gate horizontal patterns; a vertical channel structure passing through the stack structure in a first region on the upper substrate; a first vertical support structure passing through the stack structure in a second region on the upper substrate; and an internal peripheral contact structure passing through the stack structure and the upper substrate, and electrically connected to the internal peripheral pad portion, wherein an upper surface of the first vertical support structure is disposed on a different level from an upper surface of the vertical channel structure, and is coplanar with an upper surface of the internal peripheral contact structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Vit Yang, Yong Hoon Son, Moon Jong Kang, Hyuk Ho Kwon, Sung Soo Ahn, So Yoon Lee
  • Patent number: 10971509
    Abstract: A semiconductor memory device according to the present technology includes a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern, a contact plug connected to the lower conductive pattern and extending in the first direction, and at least one lower dummy plug overlapping the lower conductive pattern.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Taek Kim
  • Patent number: 10964719
    Abstract: According to one embodiment, the semiconductor body of the first portion includes a first semiconductor part and a second semiconductor part. The first semiconductor part extends in the stacking direction. The second semiconductor part is provided between the first semiconductor part and the first electrode layer, and has an end located closer to the first electrode layer side than the first semiconductor part. The first insulating film of the second portion includes a first insulating part and a second insulating part. The first insulating part extends in the stacking direction. The second insulating part is provided between the first insulating part and the second electrode layer, and has an end located closer to the second electrode layer side than the first insulating part.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Kamigaichi
  • Patent number: 10964398
    Abstract: A memory device includes a memory cell region including a metal pad and first and second memory cells in a memory block, a peripheral circuit region including another metal pad and vertically connected to the memory cell region by the metal pads, a first word line in the memory cell region connected to the first memory cell, a second word line in the memory cell region connected to the second memory cell, an address decoder in the peripheral circuit region applying one of an erase voltage and an inhibit voltage to the first and second word lines, and control logic in the peripheral circuit region controlling an erasing operation on the memory block. During the erasing operation the inhibit voltage is applied to the first word line after the erase voltage, and the erase voltage is applied to the second word line after the inhibit voltage.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: March 30, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Wan Nam, Yong Hyuk Choi, Jun Yong Park, Jung No Im
  • Patent number: 10957706
    Abstract: A multi-tier three-dimensional memory array includes multiple alternating stacks of insulating layers and electrically conductive layers that are vertically stacked. Memory stack structures including memory films and semiconductor channels extend through the alternating stacks. The alternating stacks are formed as alternating stacks of insulating layers and sacrificial material layers, and are subsequently modified by replacing the sacrificial material layers with electrically conductive layers. Structural support during replacement of the sacrificial material layers with the electrically conductive layers is provided by the memory stack structures and dielectric support pillar structures. The dielectric support pillar structures may be formed only for a first-tier structure including a first-tier alternating stack of first insulating layers and first spacer material layers, or may vertically extend over multiple tiers.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshitaka Otsu, Kei Nozawa, Yashushi Doda, Naoto Hojo, Yoshinobu Tanaka, Koichi Ito
  • Patent number: 10957394
    Abstract: Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 23, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Han-Ping Chen, Wei Zhao, Henry Chin
  • Patent number: 10950613
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 16, 2021
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 10950621
    Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takanobu Ono, Yusuke Dohmae
  • Patent number: 10950619
    Abstract: A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Jung, Sunghan Cho
  • Patent number: 10943919
    Abstract: A semiconductor memory device includes a plurality of first conductor layers that are stacked in a first direction; a first pillar including a first semiconductor layer and extending through the first conductor layers in the first direction; a first charge storage layer that is provided between the first conductor layers and the first semiconductor layer; a plurality of second conductor layers that are stacked in the first direction above an uppermost conductor layer of the first conductor layers; a second pillar including a second semiconductor layer and extending through the second conductor layers in the first direction, the second semiconductor layer electrically connected to the first semiconductor layer; and a conductor pillar or film extending in the first direction through the second conductor layers other than a lowermost layer of the second conductor layers and being in contact with a respective upper surface of each of the second conductor layers.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shigeki Kobayashi, Taro Shiokawa, Masahisa Sonoda