Variable Threshold (e.g., Floating Gate Memory Device) Patents (Class 257/314)
  • Patent number: 11956960
    Abstract: A semiconductor device includes a gate stack with conductive layers and insulating layers that are stacked alternately with each other, a first channel pattern passing through the gate stack, a second channel pattern coupled to the first channel pattern, the second channel pattern protruding above a top surface of the gate stack, an insulating core formed in the first channel pattern, the insulating core extending into the second channel pattern, a gate liner with a first portion that surrounds a top surface of the gate stack and a second portion that surrounds a portion of a sidewall of the second channel pattern, and a barrier pattern coupled to the gate liner, the barrier pattern surrounding a remaining portion of the sidewall of the second channel pattern.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: April 9, 2024
    Assignee: SK hynix Inc.
    Inventor: Ki Hong Lee
  • Patent number: 11956959
    Abstract: A semiconductor memory device includes a semiconductor substrate including a diode formed in an upper layer portion of the semiconductor substrate, a first insulating film provided above the semiconductor substrate, a first conductive film provided above the first insulating film and coupled to the diode, a stacked body provided above the first conductive film, an insulator and an electrode film being stacked alternately in the stacked body, a semiconductor member piercing the stacked body and being connected to the first conductive film, and a charge storage member provided between the electrode film and the semiconductor member.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Jun Fujiki, Shinya Arai, Kotaro Fujii
  • Patent number: 11950426
    Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.
    Type: Grant
    Filed: March 27, 2023
    Date of Patent: April 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Eric S. Carman, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy, Richard E Fackenthal, Haitao Liu
  • Patent number: 11950417
    Abstract: A semiconductor device including a stack structure including gate layers and interlayer insulating layers spaced apart in a vertical direction, a channel hole penetrating the stack structure in the vertical direction, a core region extending within the channel hole, a channel layer disposed on a side surface of the core region, a first dielectric layer, a data storage layer and a second dielectric layer, which are disposed between the channel layer and the gate layers, and a pad pattern disposed on the core region, in the channel hole, and in contact with the channel layer. A first horizontal distance between a side surface of a first portion of an uppermost gate layer and an outer side surface of the channel layer is greater than a second horizontal distance between a side surface of a second portion of the uppermost gate layer and an outer side surface of the pad pattern.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wukang Kim, Sejun Park, Hyoje Bang, Jaeduk Lee, Junghoon Lee
  • Patent number: 11942136
    Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Kamal M. Karda, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11943926
    Abstract: A semiconductor device including a substrate; a horizontal conductive layer disposed on the substrate; a support layer disposed on the horizontal conductive layer; a stack structure including a plurality of gate electrodes, stacked to be spaced apart from each other in a direction perpendicular to an upper surface of the support layer, and a plurality of interlayer insulating layers stacked alternately with the plurality of gate electrodes; a channel structure penetrating through the stack structure; a separation structure penetrating through the horizontal conductive layer, the support layer, and the stack structure and extending in a first direction; and a conductive pattern disposed on a level between the horizontal conductive layer and a lowermost interlayer insulating layer, among the plurality of interlayer insulating layers, and protruding outwardly of the separation structure from a side surface of the separation structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 26, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonseok Cho, Seulbi Lee
  • Patent number: 11935598
    Abstract: A semiconductor storage device is provided. The semiconductor storage device includes a first voltage supply line coupled to a gate electrode of a first memory transistor through a first transistor, a first signal supply line coupled to a gate electrode of the first transistor, a first capacitor coupled to the gate electrode of the first memory transistor, and a first wiring coupled between the gate electrode of the first memory transistor and the first transistor through the first capacitor. In a write operation on the first memory transistor, at a second timing after a first timing, a voltage present on the first signal supply line decreases from a second voltage to a fourth voltage lower than the second voltage, and at a third timing after the second timing, the voltage present on the first wiring increases from a third voltage to a fifth voltage higher than the third voltage.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: March 19, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Kiyoshi Okuyama
  • Patent number: 11935574
    Abstract: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: March 19, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Michael Mutch, Ashonita A. Chavan, Sameer Chhajed, Beth R. Cook, Kamal Kumar Muthukrishnan, Durai Vishak Nirmal Ramaswamy, Lance Williamson
  • Patent number: 11923289
    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Roger W. Lindsay, Krishna K. Parat
  • Patent number: 11925019
    Abstract: A three-dimensional (3D) memory device includes a memory stack including conductive layers and dielectric layers interleaving the conductive layers, and a channel structure extending through the memory stack along a vertical direction. The channel structure has a plurality of protruding portions protruding along a lateral direction and facing the conductive layers, respectively, and a plurality of normal portions facing the dielectric layers, respectively, without protruding along the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions and over the plurality of blocking structures, respectively. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the storage structures over the blocking structure.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: March 5, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wanbo Geng, Lei Xue, Xiaoxin Liu, Tingting Gao
  • Patent number: 11923033
    Abstract: A semiconductor device includes: a first memory block having a first block pitch; and a second memory block belonging to a same plane as the first memory block, the second memory block located closer to a plane edge than the first memory block, the plane edge being an edge of the plane, wherein the second memory block has a second block pitch that is larger than the first block pitch.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: March 5, 2024
    Assignee: SK hynix Inc.
    Inventor: Jae Taek Kim
  • Patent number: 11917823
    Abstract: A first opening extending vertically through a dielectric stack is formed above a substrate. The dielectric stack includes vertically interleaved dielectric layers and sacrificial layers. Parts of the sacrificial layers facing the opening are removed to form a plurality of first recesses. A plurality of stop structures are formed along sidewalls of the plurality of first recesses. A plurality of storage structures are formed over the plurality of stop structures in the plurality of first recesses. The plurality of sacrificial layers are removed to expose the plurality of stop structures from a plurality of second recesses opposing the plurality of first recesses. The plurality of stop structures are removed to expose the plurality of storage structures. A plurality of blocking structures are formed over the plurality of storage structures in the plurality of second recesses.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: February 27, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Wanbo Geng, Lei Xue, Xiaoxin Liu, Tingting Gao
  • Patent number: 11910606
    Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Jordan D. Greenlee
  • Patent number: 11908522
    Abstract: In certain aspects, a memory device includes memory cells, and a peripheral circuit coupled to the memory cells. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cells, obtain a number of occurrences of one or more suspensions during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of the suspensions.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: February 20, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Huangpeng Zhang, Zhichao Du, Ke Jiang, Cong Luo, Daesik Song
  • Patent number: 11903196
    Abstract: A microelectronic device comprises a stack structure comprising a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, strings of memory cells vertically extending through the block structures of the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, an additional stack structure vertically overlying the stack structure and comprising a vertical sequence of additional conductive structures and additional insulative structures arranged in additional tiers, first pillars extending through the additional stack structure and vertically overlying the strings of memory cells, each of the first pillars horizontally offset from a center of a corresponding string of memory cells, second pillars extending through the additional stack structure and vertically ove
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Yoshiaki Fukuzumi, Jun Fujiki, Matthew J. King, Sidhartha Gupta, Paolo Tessariol, Kunal Shrotri, Kye Hyun Baek, Kyle A. Ritter, Shuji Tanaka, Umberto Maria Meotto, Richard J. Hill, Matthew Holland
  • Patent number: 11895839
    Abstract: A semiconductor storage device includes a stack, a channel layer, a first charge storage portion, and a second charge storage portion. The stack includes a plurality of conductive layers and a plurality of insulating layers, and the plurality of conductive layers and the plurality of insulating layers are alternately stacked one by one in a first direction. The channel layer extends in the first direction in the stack. The first charge storage portion is provided between the channel layer and each of the plurality of conductive layers in a second direction intersecting with the first direction. The second charge storage portion includes a portion interposed between two adjacent conductive layers in the plurality of conductive layers in the first direction.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Hideto Takekida
  • Patent number: 11895834
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 6, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiewei Chen, Jordan D. Greenlee, Mithun Kumar Ramasahayam, Nancy M. Lomeli
  • Patent number: 11894300
    Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: February 6, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11895845
    Abstract: A memory device and a method for manufacturing the same, and an electronic apparatus including the memory device are provided. The memory device may include: a substrate (1001); an electrode structure on the substrate (1001), in which the electrode structure includes a plurality of first electrode layers and a plurality of second electrode layers that are alternately stacked; a plurality of vertical active regions penetrating the electrode structure; a first gate dielectric layer and a second gate dielectric layer, in which the first gate dielectric layer is between the vertical active region and each first electrode layer of the electrode structure, and the second gate dielectric layer is between the vertical active region and each second electrode layer of the electrode structure, each of the first gate dielectric layer and the second gate dielectric layer constitutes a data memory structure.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: February 6, 2024
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 11894447
    Abstract: A method for manufacturing a semiconductor device includes: implanting a P-type impurity from a region where the first conductor film is formed toward an inside of the semiconductor substrate with a first acceleration energy; forming a nitride film provided with a first opening on the first conductor film; forming an insulating film with a second opening from which the first conductor film is exposed; forming a second conductor film to fill the second opening of the insulating film; removing the nitride film and a portion of the first conductor film positioned below the nitride film to expose the oxide film in a peripheral area of a formation region of the insulating film; and implanting the P-type impurity from a region from which the oxide film is exposed toward an inside of the semiconductor substrate with a second acceleration energy smaller than the first acceleration energy.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: February 6, 2024
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Tetsuya Yamamoto
  • Patent number: 11889672
    Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11882684
    Abstract: A semiconductor memory cell having an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: January 23, 2024
    Assignee: Zeno Semiconductor Inc.
    Inventors: Yuniarto Widjaja, Jin-Woo Han
  • Patent number: 11877450
    Abstract: A semiconductor memory device includes; a first stacked structure including a first staircase portion, a second stacked structure on the first stacked structure and including a second staircase portion overlapping the first staircase portion, a first contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the first stacked structure and not electrically connected to the second stacked structure, and a second contact plug penetrating the first stacked structure and the second stacked structure, electrically connected to the second stacked structure and not electrically connected to the first stacked structure.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 16, 2024
    Inventors: So Hyeon Lee, Sung Su Moon, Jae Duk Lee, Ik-Hyung Joo
  • Patent number: 11876076
    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 16, 2024
    Assignee: Adeia Semiconductor Technologies LLC
    Inventors: Javier A. DeLaCruz, Belgacem Haba, Rajesh Katkar, Pearl Po-Yee Cheng
  • Patent number: 11862282
    Abstract: A memory performing logic functions has two single transistor static ram memory (STSRAM) with drain, source, and gate terminal which can be written, read, and when read, generates an output current. The STSRAMs have drain and source connected in parallel, and when read, generate a current provided to a current comparator amplifier (CCA) which is compared to a reference current Iref to generate an output which is at least one of a logical AND, logical NAND, logical OR, logical NOR, or logical exclusive OR (XOR).
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: January 2, 2024
    Assignee: Ceremorphic, Inc.
    Inventors: Neelam Surana, Robert F. Wiser
  • Patent number: 11864380
    Abstract: Some embodiments include an integrated assembly having a memory array region which includes channel material pillars extending through a stack of alternating conductive and insulative levels. A second region is adjacent the memory array region. A conductive expanse is within the memory array region and electrically coupled with the channel material of the channel material pillars. A panel extends across the memory array region and the second region. The panel separates one memory block region from another. The panel has a first portion over the conductive expanse, and has a second portion adjacent the first portion. The panel has a bottom surface. A first segment of the bottom surface is adjacent an upper surface of the conductive expanse. A segment of the bottom surface within the second portion is elevationally offset relative to the first segment. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: January 2, 2024
    Inventor: Shuangqiang Luo
  • Patent number: 11864385
    Abstract: Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghwan Lee, Suhyeong Lee, Ju-Young Lim, Daehyun Jang, Sanghoon Jeong
  • Patent number: 11862691
    Abstract: A field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure having: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the change extending from the upper surface of the gate into the region between gate and the drain; and wherein the electric charge solely produces the electric field.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: January 2, 2024
    Assignee: Raytheon Company
    Inventors: Michael S. Davis, Eduardo M. Chumbes, Brian T. Appleton, Jr.
  • Patent number: 11856783
    Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Chun Liou, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin, Chia-En Huang
  • Patent number: 11856772
    Abstract: A nonvolatile memory device and method of fabricating same, the nonvolatile memory device including a substrate; a first semiconductor layer on the substrate; an etching stop film including a metal oxide on the first semiconductor layer; a mold structure including second semiconductor layers and insulating layers alternately stacked on the etching stop film; a channel hole penetrating through at least one of the mold structure, the etching stop film, the second semiconductor layer and the substrate; and a channel structure extending along a side wall of the channel hole, including an anti-oxidant film, a first blocking insulation film, a second blocking insulation film, a charge storage film, a tunnel insulating film and a channel semiconductor sequentially formed along the side wall of the channel hole. The first semiconductor layer contacts the first blocking insulation film, the second blocking insulation film, the charge storage film, and the tunnel insulating film.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: December 26, 2023
    Inventors: Seung Won Lee, Tae Hun Kim, Min Cheol Park, Hye Ri Shin, Jun Hee Lim, Si Yeon Cho
  • Patent number: 11856759
    Abstract: A semiconductor device includes: a semiconductor layer having a main surface; a first conductive type well region formed on a surface portion of the main surface of the semiconductor layer; a second conductive type source region formed on a surface portion of the well region; a second conductive type drain region formed on the surface portion of the well region at an interval from the source region; a planar gate structure formed on the main surface of the semiconductor layer so as to face a first conductive type channel region disposed between the source region and the drain region; and a memory structure disposed adjacent to a lateral side of the planar gate structure, and including an insulating film formed on the channel region and a charge storage film facing the channel region with the insulating film interposed between the charge storage film and the channel region.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 26, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Yushi Sekiguchi, Yasunobu Hayashi, Tadayuki Yamazaki
  • Patent number: 11855154
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Patent number: 11854789
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo, Cheng-Wei Lian
  • Patent number: 11856747
    Abstract: A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chi-Lung Lee, Chien-Chi Tien, Chiting Cheng
  • Patent number: 11856786
    Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Feng Young, Yi-Ching Liu, Sai-Hooi Yeong, Yih Wang, Yu-Ming Lin
  • Patent number: 11844215
    Abstract: Provided are a three-dimensional flash memory device supporting a bulk erase operation and a method of manufacturing the three-dimensional flash memory device. The three-dimensional flash memory device supporting a bulk erase operation includes: a string including a channel layer extending in one direction and a plurality of electrode layers stacked vertically with respect to the channel layer; an upper wiring layer on the string; at least one intermediate wiring layer arranged between the plurality of electrode layers through the channel layer in an intermediate region of the string; a lower wiring layer under the string; and at least one connector arranged in the at least one intermediate wiring layer and connecting, to each other, at least two channel layers divided by the at least one intermediate wiring layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: December 12, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yunheub Song
  • Patent number: 11830827
    Abstract: A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: November 28, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang
  • Patent number: 11825656
    Abstract: In a method for manufacturing a memory device, a plurality of first insulating layers and a bottom select gate (BSG) layer are formed over a substrate, where the first insulating layers are disposed between the substrate and the BSG layer. One or more first dielectric trenches are formed to pass through the BSG layer and the first insulating layers, and extend in a length direction of the substrate. A plurality of word line layers and a plurality of second insulating layers are formed over the BSG layer, where the second insulating layers are disposed between the BSG layer and the word line layers. One or more common source regions are formed over the substrate to extend in the length direction of the substrate, and further extend through the BSG layer, the first insulating layers, the word line layers, and the second insulating layers.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 21, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yali Song, Li Hong Xiao, Ming Wang
  • Patent number: 11824011
    Abstract: According to one embodiment, a memory device includes: a first layer stack provided in a first area of a substrate; second and third layer stacks provided in a second area of the substrate; a memory cell provided in the first layer stack; a first mark portion provided in the second layer stack; a second mark portion provided in the third layer stack; and a first portion provided between the second layer stack and the third layer stack.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: November 21, 2023
    Assignee: Kioxia Corporation
    Inventor: Kenji Konomi
  • Patent number: 11818885
    Abstract: According to an embodiment, a semiconductor memory device includes a first conductive layer and second conductive layers arranged at intervals in a first direction above the first conductive layer. A semiconductor layer extends in the first direction in the second conductive layers to be in contact with the first conductive layer. A charge storage layer is between the semiconductor layer and the second conductive layers. A metal layer extends in the first direction and a second direction above the first conductive layer, and separates the second conductive layers. The device further includes an insulating layer. The insulating layer includes a portion between the metal layer and the first conductive layer and a portion between the metal layer and the second conductive layers.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: November 14, 2023
    Assignee: Kioxia Corporation
    Inventor: Takamasa Ito
  • Patent number: 11818892
    Abstract: A semiconductor device includes: a stack structure including gate patterns and insulating patterns; a channel layer penetrating the stack structure; a memory layer penetrating the stack structure, the memory layer surrounding the channel layer; and a select transistor connected to the channel layer. The select transistor includes: a carbon layer Schottky-joined with the channel layer; a select gate spaced apart from the carbon layer; and a gate insulating layer between the select gate and the carbon layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: November 14, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang
  • Patent number: 11817428
    Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: November 14, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Masayoshi Tagami, Ryota Katsumata, Jun Iijima, Tetsuya Shimizu, Takamasa Usui, Genki Fujita
  • Patent number: 11818891
    Abstract: A memory device includes a staircase region and an array region, along a first lateral direction; a wall structure in the staircase region; and a first separation structure in the array region and arranged along the first lateral direction with the wall structure. The wall structure includes dielectric pairs of a first dielectric layer and a second dielectric layer stacked in the staircase region. The first separation structure is vertically through a stack structure in the array region. The stack structure includes pairs of the first dielectric layer and an electrode layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: November 14, 2023
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kai Han, Yali Guo, Zhipeng Wu, Lu Zhang, Hang Yin, Simin Liu, Bo Xu
  • Patent number: 11800718
    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a via above a substrate, a dielectric layer over the via, a first source/drain feature above the dielectric layer, a first channel feature above the first source/drain feature, a second source/drain feature above the first channel feature, and a gate line laterally spaced apart from the first source/drain feature, the first channel feature and the second source/drain feature. The gate line passes through the dielectric layer and is on the via.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chih Lai, Chung-Te Lin
  • Patent number: 11797746
    Abstract: A method (of forming a semiconductor device) including forming cell regions (in alternating first and second rows having first and second heights) including forming a majority of the cell regions in the first rows including: limiting a height of the majority of the cell regions to be single-row cell regions that span corresponding single one of the first rows but do not extend therebeyond; and forming a minority of the cell regions correspondingly in at least the first rows including reducing widths of the multi-row cell regions to be smaller than comparable single-row cell regions; and expanding heights of the minority of the cell regions to be multi-row cell regions, each of the multi-row cell regions spanning a corresponding single first row and at least a corresponding second row such that cell region densities of the second rows are at least about forty percent.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: October 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Hui-Ting Yang, Jiann-Tyng Tzeng, Lipen Yuan, Wei-An Lai
  • Patent number: 11791279
    Abstract: A semiconductor device according to an embodiment includes a stacked body having first films and second films that are alternately stacked, a light shielding film provided in a specific layer of the stacked body and having a higher optical absorptivity than that of the second films, and a channel film extending in the stacked body in the stacking direction. The channel film includes a first part located on an upper side than the light shielding film in the stacking direction and containing a monocrystalline semiconductor.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Tatsunori Isogai, Masaki Noguchi, Tatsufumi Hamada, Shinichi Sotome
  • Patent number: 11792981
    Abstract: A MOSFET device and method of making, the device including a floating gate layer formed within a trench in a substrate, a tunnel dielectric layer located on sidewalls and a bottom of the trench, a control gate dielectric layer located on a top surface of the floating gate layer, a control gate layer located on a top surface of the control gate dielectric layer and sidewall spacers located on sidewalls of the control gate dielectric layer and the control gate layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: October 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Chung Jen, Yu-Chu Lin, Y. C. Kuo, Wen-Chih Chiang, Keng-Ying Liao, Huai-Jen Tung
  • Patent number: 11785776
    Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: October 10, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
  • Patent number: 11784243
    Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 10, 2023
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD
    Inventors: Sagy Charel Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam G Geha
  • Patent number: 11776944
    Abstract: A discrete three-dimensional (3-D) processor comprises communicatively coupled first and second dice. The first die comprises 3-D memory (3D-M) arrays, whereas the second die comprises at least a non-memory circuit and at least an off-die peripheral-circuit component of the 3D-M arrays. The first die does not comprise said off-die peripheral-circuit component. The non-memory circuit on the second die is not part of a memory.
    Type: Grant
    Filed: November 27, 2022
    Date of Patent: October 3, 2023
    Assignees: HangZhou HaiCun Information Technology Co., Ltd.
    Inventor: Guobiao Zhang