CHIP PACKAGE STRUCTURE
A chip package includes a die, a pad-mounting surface on the die, a plurality of bonding pad arranged at the pad-mounting surface, at least one dielectric layer cover over the pad-mounting surface, and at least one conductive wire set in the dielectric layer. The formation of the conductive wire consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
1. Fields of the Invention
The preset invention relates to a chip package structure, especially to a die with a plurality of bonding pads. Each bonding pad includes a conductive wire extended outward and a solder point. The die is electrically connected and assembled with a substrate by each conductive wire and each solder point.
2. Descriptions of Related Art
Along with development of semiconductor manufacturing processes, there are various manufacturing processes and structures of the chip package, as shown in U.S. Pat. No. 6,239,488, U.S. Pat. No. 5,990,546, U.S. Pat. No. 6,143,991, U.S. Pat. No. 6,075,712, and U.S. Pat. No. 6,114,754. In early days, a TAB (Tape automated bonding) technique is developed and used. But outer lead portions extended from the pad-mounting surface of the plurality of bonding die pads causes the increased package size and this is not satisfied with the requirement of high density. In recent years, a CSP (chip scale package) technique is developed and used. A plurality of various manufacturing processes and structure have also been derived. Although CSP solves the problem of larger package size caused by TAB, it still has problems of complicated manufacturing processes, low yield rate of the products and increased manufacturing cost. Refer to claim 1, claim 6, FIG. 1 to FIG. 7 and FIG. 14 to FIG. 19 in U.S. Pat. No. 6,239,488, conductive bodies 3 are directly formed on a pad-mounting surface 10 and there is no dielectric layer between the conductive bodies 3 and the pad-mounting surface 10. This has negative effect on the insulation effect between the conductive bodies 3 and other bonding pads and the product yield rate is reduced. Moreover, according to the processes and structure revealed by this prior art, the step that produces the conductive body 3 can't be repeated so that the conductive body 3 is with only single-layer structure, not double-layer structure. Thus the space on the pad-mounting surface 10 for establishing the required electrical connection is also reduced.
However, according to the structure and manufacturing processes mentioned in U.S. Pat. No. 6,239,488, the step of forming the conductive body 3 is unable to be repeated so that the conductive body 3 only has a single-layer structure. Thus the use efficiency of the wiring space on the pad-mounting surface 10 of a die is further reduced. Moreover, this prior art also restricts the formation method of the conductive body 3 in the chip package structure and the technique revealed by the steps in the claim 1 intends to make greater difference than other prior techniques disclosed in U.S. Pat. No. 5,990,546, U.S. Pat. No. 6,143,991, U.S. Pat. No. 6,075,712, and U.S. Pat. No. 6,114,754. However, the not only the scope of the claim is limited, but the formation and the structure of the conductive body 3 are complicated that lead to increased manufacturing cost. Thus there is a need to improve the chip package structure and the related manufacturing processes.
SUMMARY OF THE INVENTIONTherefore it is a primary object of the present invention to provide a single-layer chip package structure that improves precision of a semiconductor chip package and use efficiency of a wiring space on a pad-mounting surface of a die so as to increase use efficiency of the wafer and yield rate of the packaging process.
It is another object of the present invention to provide a double-layer chip package structure that improves precision of a semiconductor chip package and use efficiency of a wiring space on a pad-mounting surface of a die so as to increase use efficiency of the wafer and yield rate of the packaging process.
In order to achieve above objects, a chip package structure of the present invention includes a die and a plurality of bonding pads arranged above the die. A conductive wire and a solder point is formed on the bonding pad so that the die is electrically connected with and assembled on a substrate by each conductive wire and respective solder point. The formation of the conductive wire includes the steps of: firstly coat a first dielectric layer on the pad-mounting surface of the die and produce a corresponding slot on each bonding pad by exposure and development of photoresist materials. Then coat a second dielectric layer again and form a wiring slot on each bonding pad and the slot thereof correspondingly by exposure and development of photoresist materials. Next fill each wiring slot with electrically conductive metal by various conventional ways so as to form a conductive wire respectively. The conventional ways include metal paste (such as silver paste) printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating, etc. Later coat a third dielectric layer and form a corresponding slot on one end of each conductive wire by exposure and development of photoresist materials. The slot is filled with electrically conductive metal so as to form a solder point exposed outside the outermost dielectric layer. Thus the bonding pad of the die is electrically extended to each solder point by each conductive wire and is electrically connected with each solder point preset on a substrate by the solder point so as to assembled and connect the die with the substrate.
In order to achieve above objects, a chip package structure of the present invention in which a die is electrically connected with and assembled on a substrate by each conductive wire and respective solder point. Similar to above steps, the steps of the formation of the conductive wire are repeated so as to further form an upper-layer conductive wire over the above conductive wire. The formation steps include: coat a third dielectric layer and form a corresponding slot on one end of each conductive wire (here is used as a lower-layer conductive wire) by exposure and development of photoresist materials. Then coat a fourth dielectric layer and form a wiring slot (used as an upper-layer wiring slot) on the slot disposed on one end of the lower-layer conductive wire correspondingly by exposure and development of photoresist materials. Then fill the upper-layer wiring slot with electrically conductive metal by various conventional ways so as to form a conductive wire respectively. The conventional ways include metal paste (such as silver paste) printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating, etc. Later coat a fifth dielectric layer and form a corresponding slot on one end of each conductive wire by exposure and development of photoresist materials. The slot is filled with electrically conductive metal so as to form a solder point exposed outside the outermost dielectric layer. Thus the bonding pad on the pad-mounting surface of the die is electrically extended to each solder point by each conductive wire and is electrically connected with each solder point preset on a substrate by the solder point so as to assembled and connect the die with the substrate.
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The manufacturing processes of the chip package structure of the present invention, especially formation steps of each conductive wire 30, can achieve a certain precision significantly. Thus the use of the wiring space on the pad-mounting surface of the die (chip) is improved effectively. Therefore, the use efficiency of the wafer is further increased and the yield rate of the packaging process is dramatically improved.
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The manufacturing processes of the chip package structure 1, 2 according to the present invention, especially the forming steps of each conductive wire 30 (30b, 30c), are with certain precision.
Moreover, according to the same forming processes, an upper and a lower layer (double-layer) structure of the conductive wire is formed so as to improve the use efficiency of the wiring space on the pad-mounting surface of the die. Therefore, the use efficiency of the wafer is further increased and the yield rate of the packaging process is dramatically improved.
Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, and representative devices shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.
Claims
1. A chip package that is assembled on a substrate and is electrically connected with a plurality of solder points arranged at the substrate comprising: a die, at least one dielectric layer and at least one conductive wire; wherein
- the die having a pad-mounting surface disposed with a plurality of bonding pads;
- the dielectric layer covered over the pad-mounting surface of the die;
- the conductive wire arranged in the dielectric layer and one end of each conductive wire is electrically connected with one bonding pad of the die while the other end of the conductive wire extends outward and exposes outside surface of the dielectric layer to form a solder point that is electrically connected with a preset solder point on a substrate for connecting and assembling the die on the substrate; the conductive wire is formed by:
- coating a first dielectric layer on the pad-mounting surface of the die;
- forming a slot on the first dielectric layer by exposure and development of photoresist materials while the slot corresponding to each bonding pad on the pad-mounting surface so that each bonding pad is exposed through each slot;
- coating a second dielectric layer on the first dielectric layer and each bonding pad;
- forming a wiring slot on the second dielectric layer by exposure and development of photoresist materials while the wiring slot connects with each bonding pad and the slot of the bonding pad; each wiring slot is mounted concavely in the second dielectric layer;
- filling electrically conductive metal into each wiring slot to form a respective conductive wire;
- coating a third dielectric layer on the second dielectric layer and each conductive wire;
- forming a slot on the third dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each conductive wire; and
- filling electrically conductive metal into each slot to form a respective solder point that is exposed outside the third dielectric layer to be electrically connected with each bonding pad of the die.
2. The device as claimed in claim 1, wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are coated by spin coating.
3. The device as claimed in claim 1, wherein before the step of coating a second dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad.
4. The device as claimed in claim 1, wherein the electrically conductive metal is filled into each wiring slot and into each slot by metal paste printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating.
5. The device as claimed in claim 1, wherein the solder point exposed outside the dielectric layer is a hemisphere, projecting out of the dielectric layer.
6. A chip package that is assembled on a substrate and is electrically connected with a plurality of solder points arranged at the substrate comprising: a die, at least one dielectric layer and at least one conductive wire; wherein:
- the die having a pad-mounting surface disposed with a plurality of bonding pads;
- the dielectric layer covered over the pad-mounting surface of the die;
- the conductive wire arranged in the dielectric layer and one end of each conductive wire is electrically connected with one bonding pad of the die while the other end of the conductive wire extends outward and exposes outside surface of the dielectric layer to form a solder point that is electrically connected with a preset solder point on a substrate for connecting and assembling the die on the substrate; the conductive wire is formed by:
- coating a first dielectric layer on the pad-mounting surface of the die;
- forming a slot on the first dielectric layer by exposure and development of photoresist materials while the slot corresponding to each bonding pad on the pad-mounting surface so that each bonding pad is exposed through the slot;
- coating a second dielectric layer on the first dielectric layer and each bonding pad;
- forming a wiring slot or a slot on the second dielectric layer by exposure and development of photoresist materials while the wiring slot or the slot connects with each bonding pad and the slot of the bonding pad; part of the bonding pad and the slot thereof forms a wiring slot and the rest part of the bonding pad and the slot thereof forms a slot while each wiring slot and each slot are mounted concavely in the second dielectric layer;
- filling electrically conductive metal into each wiring slot and each slot to form a lower-layer conductive wire respectively;
- coating a third dielectric layer on the second dielectric layer and each lower-layer conductive wire;
- forming a slot on the third dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each lower-layer conductive wire;
- coating a fourth dielectric layer on the third dielectric layer and each slot;
- forming a wiring slot or a slot on the fourth dielectric layer by exposure and development of photoresist materials and the wiring slot or the slot connected with one end of each lower-layer conductive wire; part of the lower-layer conductive wire forms a slot when the part of the lower-layer conductive wire is a wiring slot in the second dielectric layer while the rest part of the lower-layer conductive wire forms a slot wiring when the part of the lower-layer conductive wire is a slot in the second dielectric layer; wherein each wiring slot and each slot are mounted concavely in the fourth dielectric layer;
- filling electrically conductive metal into each wiring slot and each slot to form an upper-layer conductive wire respectively;
- coating a fifth dielectric layer on the fourth dielectric layer and each upper-layer conductive wire;
- forming a slot on the fifth dielectric layer by exposure and development of photoresist materials and the slot connected with one end of each upper-layer conductive wire; and
- filling electrically conductive metal into each slot on the fifth dielectric layer to form a respective solder point that is exposed outside the fifth dielectric layer to be electrically connected with each bonding pad of the die.
7. The device as claimed in claim 6, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, and the fifth dielectric layer are coated by spin coating but not limiting.
8. The device as claimed in claim 6, wherein before the step of coating a second dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad.
9. The device as claimed in claim 6, wherein before the step of coating a fifth dielectric layer, each bonding pad exposed through each slot is coated with an electrically conductive metal layer that is used as a protective layer for each bonding pad.
10. The device as claimed in claim 6, wherein the electrically conductive metal is filled into each wiring slot and into each slot by silver paste printing, sputter, chemical vapor deposition (CVD), sputtering and electroplating, or CVD and electroplating.
11. The device as claimed in claim 6, wherein the solder point exposed outside the dielectric layer is a hemisphere, projecting out of the dielectric layer.
Type: Application
Filed: Dec 1, 2009
Publication Date: Jun 3, 2010
Inventors: Tse-Ming CHU (Taipei City), Sung-Chuan MA (Hong Kong)
Application Number: 12/628,593
International Classification: H01L 23/498 (20060101); H01L 21/60 (20060101);