Additional Leads Joined To Metallizations On Insulating Substrate, E.g., Pins, Bumps, Wires, Flat Leads (epo) Patents (Class 257/E23.068)
  • Patent number: 10978418
    Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 13, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 10930539
    Abstract: An electrostatic chuck heater is such that a sheet heater formed by embedding a heater wire in a resin sheet is disposed between an electrostatic chuck and a support pedestal. The heater wires are provided one for each of many zones of the resin sheet, and are composed of copper wires routed unicursally from their first ends to their second ends so as to extend throughout the zones.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: February 23, 2021
    Assignee: NGK Insulators, Ltd.
    Inventors: Rishun Kin, Hiroshi Takebayashi, Natsuki Hirata
  • Patent number: 10622549
    Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 14, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Sundar Chetlur, Harianto Wong, Maxim Klebanov, William P. Taylor, Michael C. Doogue
  • Patent number: 9748115
    Abstract: An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12, a first resin layer 14 and a third resin layer 15 that are located above the semiconductor substrate, a second resin layer 16 that is formed such that at least portions of the second resin layer are located on the first resin layer and the third resin layer, a resin projection 17 that includes the first to third resin layers and is higher than the first resin layer, and a wiring layer 24 that is electrically connected to the electrode pad and lies above the resin projection.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: August 29, 2017
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Terunao Hanaoka
  • Patent number: 9560767
    Abstract: A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 31, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yonghoon Kim, Seung Hwan Kim, Heeseok Lee
  • Patent number: 9398691
    Abstract: A printed circuit board includes: a substrate; a land that is disposed on a surface of the substrate, and includes a central portion and a plurality of extended portions, the central portion having the same shape and the same size as a land of a surface mount device, and the extended portions being up-and-down symmetry and right-and-left symmetry with respect to a straight line which passes through the center of the central portion; gaps that are disposed on the surface of the substrate, each of the gaps being disposed on a periphery of the central portion and between the extended portions; and a resist that is disposed on the surface of the substrate, and has an opening portion formed at a position corresponding to the central portion and the gaps.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: July 19, 2016
    Assignee: FUJITSU COMPONENT LIMITED
    Inventor: Shinya Yamamoto
  • Patent number: 9030021
    Abstract: Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB body; a bottom metal layer at a bottom of the PCB body; and a top metal layer at a top of the PCB body, and the top metal layer includes: vias vertically connected to the PCB body; bump pads hexagonally aligned in a horizontal direction around the vias; and connection patterns connecting the vias to two or more of the bump pads. Accordingly, the number of bump pads in a unit area of the PCB may be increased.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 12, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jik-ho Song
  • Patent number: 9018769
    Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: April 28, 2015
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Craig Mitchell, Piyush Savalia
  • Patent number: 9006887
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Leonel Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Patent number: 9006892
    Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Kai-Ming Ching
  • Patent number: 9000584
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Patent number: 9000579
    Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Emmanuel Espiritu, Rachel Layda Abinan
  • Patent number: 8981575
    Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Pang-Chun Lin, Chun-Yuan Li, Chien-Ping Huang, Chun-Chi Ke
  • Patent number: 8975758
    Abstract: A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.
    Type: Grant
    Filed: December 26, 2011
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Seung Hyun Lee
  • Patent number: 8975760
    Abstract: A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: March 10, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Shori Fujiwara
  • Patent number: 8970033
    Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Yuh Chern Shieh, Tsung-Shu Lin, Han-Ping Pu, Jiun Yi Wu, Tin-Hao Kuo
  • Patent number: 8963313
    Abstract: Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: February 24, 2015
    Assignee: Raytheon Company
    Inventors: Sankerlingam Rajendran, Monte R. Sanchez, Susan M. Eshelman, Douglas R. Gentry, Thomas A. Hanft
  • Patent number: 8963326
    Abstract: A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Xusheng Bao, Ma Phoo Pwint Hlaing, Jian Zuo
  • Patent number: 8952529
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A first conductive layer having first and second segments is formed over a surface of the substrate with a first vent separating an end of the first segment and the second segment and a second vent separating an end of the second segment and the first segment. A second conductive layer is formed over the surface of the substrate to electrically connect the first segment and second segment. The thickness of the second conductive layer can be less than a thickness of the first conductive layer to form the first vent and second vent. The semiconductor die is mounted to the substrate with the bumps aligned to the first segment and second segment. Bump material from reflow of the bumps is channeled into the first vent and second vent.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: February 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JaeHyun Lee, SunJae Kim, JoongGi Kim
  • Patent number: 8952533
    Abstract: Polyimide-based redistribution layers (RDLs) can be employed to reduce thermo-mechanical stress that is exerted on conductive interconnections bonded to interposers in 2.5 D semiconductor packaging configurations. The polyimide-based RDL is located on an upper or lower face of an interposer. Additionally, height differentials between laterally adjacent semiconductor dies in 2.5 D semiconductor packages can be reduced or eliminated by using different diameter micro-bumps, different height copper pillars, or a multi-tiered interposer to lower taller semiconductor dies in relation to shorter semiconductor dies.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: February 10, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Anwar A. Mohammed, Weifeng Liu, Rui Niu
  • Patent number: 8941237
    Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: January 27, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yu Hasegawa, Mitsuaki Katagiri
  • Patent number: 8937386
    Abstract: The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: January 20, 2015
    Assignee: Aflash Technology Co., Ltd.
    Inventors: Tse-Ming Chu, Sung-Chuan Ma
  • Patent number: 8907481
    Abstract: A stack of a first and second semiconductor structures is formed. Each semiconductor structure includes: a semiconductor bulk, an overlying insulating layer with metal interconnection levels, and a first surface including a conductive area. The first surfaces of semiconductor structures face each other. A first interconnection pillar extends from the first surface of the first semiconductor structure. A housing opens into the first surface of the second semiconductor structure. The housing is configured to receive the first interconnection pillar. A second interconnection pillar protrudes from a second surface of the second semiconductor structure which is opposite the first surface. The second interconnection pillar is in electric contact with the first interconnection pillar.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 9, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Laurent-Luc Chapelon
  • Patent number: 8907469
    Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package providing electrical signal connections between the first integrated circuit package and the second integrated circuit package. At least one support structure is disposed between the first integrated circuit package and the second integrated circuit package to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package without providing electrical signal connections.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8884445
    Abstract: A semiconductor chip includes a substrate having one surface and an other surface which substantially faces away from the one surface; at least two alignment bumps formed on the one surface of the substrate and having different diameters; and at least two alignment grooves defined on the other surface of the substrate and having different diameters.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: November 11, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jin Hui Lee
  • Patent number: 8866294
    Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the first semiconductor die. A penetrable adhesive layer is formed over a temporary carrier. The adhesive layer can include a plurality of slots. The semiconductor die is mounted to the carrier by embedding the bumps into the penetrable adhesive layer. The semiconductor die and interconnect structure can be separated by a gap. An encapsulant is deposited over the first semiconductor die. The bumps embedded into the penetrable adhesive layer reduce shifting of the first semiconductor die while depositing the encapsulant. The carrier is removed. An interconnect structure is formed over the semiconductor die. The interconnect structure is electrically connected to the bumps. A thermally conductive bump is formed over the semiconductor die, and a heat sink is mounted to the interconnect structure and thermally connected to the thermally conductive bump.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Yaojian Lin, Jun Mo Koo
  • Patent number: 8860218
    Abstract: A semiconductor die includes a first contact stack including a first die pad having a first pad perimeter, a first via through a dielectric layer to the first die pad having a first via perimeter, and a first UBM pad contacting the first die pad through the first via having a first UBM pad perimeter. A second contact stack includes a second die pad having a second pad perimeter shorter than the first pad perimeter, a second via through the dielectric layer to the second die pad having a second via perimeter shorter than the first via perimeter, and a second UBM pad contacting the second die pad through the second via having a second UBM pad perimeter that is shorter than the first UBM pad perimeter.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: October 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Ramlah Binte Abdul Razak
  • Patent number: 8853853
    Abstract: The embodiments of bump and bump-on-trace (BOT) structures provide bumps with recess regions for reflowed solder to fill. The recess regions are placed in areas of the bumps where reflow solder is most likely to protrude. The recess regions reduce the risk of bump to trace shorting. As a result, yield can be improved.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Patent number: 8835300
    Abstract: The present invention relates to a method for inhibiting growth of intermetallic compounds, comprising the steps of: (i) preparing a substrate element including a substrate on which at least one layer of metal pad is deposited, wherein at least one thin layer of solder is deposited onto the layer of metal pad, and then carry out reflowing process; and (ii) further depositing a bump of solder with an appropriate thickness on the substrate element, characterized in that a thin intermetallic compound is formed by the reaction of the thin solder layer and the metal in the metal pad after appropriate heat treatment of the thin solder layer. In the present invention, the formation of a thin intermetallic compound is able to slow the growth of the intermetallic compound and to prevent the transformation of the intermetallic compounds.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 16, 2014
    Assignee: National Chiao Tung University
    Inventors: Chih Chen, King-Ning Tu, Hsiang-Yao Hsiao
  • Patent number: 8836116
    Abstract: The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsueh-An Yang
  • Patent number: 8836115
    Abstract: A stacked inverted flip chip package includes a substrate having a secondary electronic component opening and first traces. Primary flip chip bumps electrically and physically couple a primary electronic component structure to the substrate. Secondary flip chip bumps electrically and physically couple an inverted secondary electronic component to the primary electronic component structure between the primary electronic component structure and the substrate and within the secondary electronic component opening. By placing the secondary electronic component between the primary electronic component structure and the substrate, the height of the stacked inverted flip chip package is minimized.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: September 16, 2014
    Inventors: Roger D. St. Amand, August Joseph Miller, Jr., Alexander William Copia, KwangSeok Oh
  • Patent number: 8835301
    Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: September 16, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: JoonYoung Choi, YoungJoon Kim, SungWon Cho
  • Patent number: 8836117
    Abstract: An electronic device may include a bottom interconnect layer and an integrated circuit (IC) carried by the bottom interconnect layer. The electronic device may further include an encapsulation material on the bottom interconnect layer and laterally surrounding the IC. The electronic device may further include electrically conductive pillars on the bottom interconnect layer extending through the encapsulation material. At least one electrically conductive pillar and adjacent portions of encapsulation material may have a reduced height with respect to adjacent portions of the IC and the encapsulation material and may define at least one contact recess. The at least one contact recess may be spaced inwardly from a periphery of the encapsulation material.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 16, 2014
    Assignee: STMicroelectronics Asia Pacific Pte. Ltd.
    Inventors: Yonggang Jin, How Yuan Hwang
  • Patent number: 8829693
    Abstract: Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: September 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mostafa Naguib Abdulla, Steven Eskildsen
  • Patent number: 8816507
    Abstract: A device includes a device die and a plurality of metal posts at a surface of the device die and electrically coupled to the device die. The device further includes a plurality of through-assembly vias (TAVs), a dam member between the device die and the plurality of TAVs, and a polymer layer encompassing the device die, the plurality of metal posts, the plurality of TAVs, and the dam member.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chang Hu, Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 8809122
    Abstract: A method of manufacturing a flip chip package includes: providing a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is to be mounted, and a connection pad disposed outside the mounting region; forming a resin layer on the board; forming a trench by removing a part of the resin layer or forming an uneven portion at a portion of a surface of the resin layer; forming, on the trench or uneven portion, a dam member preventing leakage of an underfill between the mounting region and the connection pad; and mounting the electronic device on the mounting region.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ey Yong Kim, Young Hwan Shin, Soon Jin Cho, Jong Yong Kim, Jin Seok Lee
  • Patent number: 8803334
    Abstract: A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: August 12, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Yun-seok Choi, Tae-je Cho
  • Patent number: 8802557
    Abstract: A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.
    Type: Grant
    Filed: March 27, 2013
    Date of Patent: August 12, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Ruoh-Huey Uang, Yi-Ting Cheng
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8791007
    Abstract: Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 29, 2014
    Assignee: Spansion LLC
    Inventors: Gin Ghee Tan, Lai Beng Teoh, Royce Yeoh Kao Tziat, Sally Yin Lye Foong
  • Patent number: 8779300
    Abstract: A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 ?m, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: July 15, 2014
    Assignee: Unimicron Technology Corp.
    Inventor: Shih-Ping Hsu
  • Patent number: 8779576
    Abstract: In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wook Park, Nam-seog Kim, Seung-duk Baek
  • Patent number: 8766450
    Abstract: There is provided a lead pin for a package substrate including: a connection pin being inserted into a hole formed in an external substrate; a head part formed on one end of the connection pin; and a barrier part formed on one surface of the head part in order to block the path of a solder paste so that the solder paste is prevented from flowing so as to cover the upper portion of the head part when the head part is mounted on the package substrate.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 1, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ki Taek Lee, Hueng Jae Oh, Sung Won Jeong, Gi Sub Lee, Jin Won Choi
  • Patent number: 8766430
    Abstract: In accordance with an embodiment of the present invention, a semiconductor module includes a first semiconductor device having a first plurality of leads including a first gate/base lead, a first drain/collector lead, and a first source/emitter lead. The module further includes a second semiconductor device and a circuit board. The second semiconductor device has a second plurality of leads including a second gate/base lead, a second drain/collector lead, and a second source/emitter lead. The circuit board has a plurality of mounting holes, wherein each of the first plurality of leads and the second plurality of leads is mounted into a respective one of the plurality of mounting holes. At the plurality of mounting holes, a first distance from the first gate/base lead to the second gate/base lead is different from a second distance from the first source/emitter lead to the second source/emitter lead.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Davide Chiola, Erich Griebl, Fabio Brucchi
  • Patent number: 8759971
    Abstract: A semiconductor apparatus in a preferred embodiment includes: a substrate; a first chip provided on the substrate; a solder bump formed on the first chip; a solder dam arranged in substantially a rectangular and annular manner outside around the solder bump on the first chip by alternately connecting four sides and four quarter or less arcs; an electrode pad placed outside of the solder dam in the first chip; a second chip provided on the first chip in electric connection to the first chip via the solder bump; and an under-fill material filling a clearance between the first chip and the second chip inside of the solder dam. Here, a difference between an inner diameter and an outer diameter of the arc is 60 ?m or more whereas the center radius of the arc is greater than 207.5 ?m.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryuji Hosokawa, Tsutomu Kojima, Tatsuo Shiotsuki
  • Patent number: 8759957
    Abstract: A film for use in manufacturing a semiconductor device having at least one semiconductor element of the present invention is characterized by comprising: a base sheet having one surface; and a bonding layer provided on the one surface of the base sheet, the bonding layer being adapted to be bonded to the semiconductor element in the semiconductor device, the bonding layer being formed of a resin composition comprising a crosslinkable resin and a compound having flux activity. Further, it is preferred that in the film of the present invention, the semiconductor element is of a flip-chip type and has a functional surface, and the bonding layer is adapted to be bonded to the functional surface of the semiconductor element.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: June 24, 2014
    Assignee: Sumitomo Bakelite Company Limited
    Inventor: Takashi Hirano
  • Patent number: 8742577
    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 3, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-kun Jee, Sun-kyoung Seo, Sang-wook Park, Ji-hwan Hwang
  • Patent number: 8736048
    Abstract: A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: May 27, 2014
    Assignee: International Business Machines Corporation
    Inventor: Mark D. Schultz
  • Publication number: 20140131854
    Abstract: One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby electrically connect the first IC chip to the second chip.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: LSI Corporation
    Inventors: Donald E. Hawk, John W. Osenbach, James C. Parker
  • Patent number: 8723312
    Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 13, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Dominique Vicard, Sophie Verrun