Abstract: A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.

Abstract: A microspring includes a film stack having a base disposed on a build plane and a spring member extending from the base. The film stack includes a compressive layer, a substantially stress-free layer, and a tensile layer. The film stack is formed of one or more materials that become superconducting below 140 K. A stress gradient in the film stack causes the spring member to curl away from the build plane of the base.

Abstract: A semiconductor module, including: plurality of output elements provided to constitute an upper arm and a lower arm; a resin case provided surrounding an accommodation space for accommodating the output elements; an arm-to-arm wiring line for connecting the upper arm with the lower arm; an output terminal, which is connected to the arm-to-arm wiring line and is for outputting output currents from the output elements to a load being external to the semiconductor module; a sense terminal, which is connected to the arm-to-arm wiring line and is for detecting currents that flow in the output elements; and an inductor provided between a connection point for connecting the arm-to-arm wiring line with the output terminal, and the output terminal is provided. An inductance of the inductor is 1 ?H or more.

Abstract: An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.

Abstract: A substrate structure is provided, in which an insulating protection layer is formed on a substrate body having a plurality of electrical contact pads, and the insulating protection layer has a plurality of openings corresponding to the plurality of exposed electrical contact pads, and the insulating protection layer is formed with a hollow portion surrounding a partial edge of at least one of the electrical contact pads at at least one of the openings, so as to reduce the barrier of the insulating protection layer.

Abstract: An electronic device substrate with a substantially planar surface formed from an electrically non-conductive material is provided with one or more metalized pads on the substantially planner surface. Each of the one or more metalized pads is surrounded by and coplanar with the first electrically nonconductive material along an outer boundary of the metalized pad. The metalized pad is patterned such that portions of the metalized pad form metalized fingers that extend radially from the outer boundary of the metalized pad in an interdigitated arrangement with the first electrically nonconductive material. The metalized pad has a solderable surface.

Abstract: In one example, an electronic device includes a substrate, which has a dielectric structure includes a dielectric structure top side and a dielectric structure bottom side opposite to the dielectric structure top side, and a conductive structure comprising a protruded via that extends from the dielectric structure bottom side. An electronic component is coupled to the conductive structure at the dielectric structure top side, and a terminal is coupled to the protruded via such that the protruded via extends into the terminal. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP) or a package containing a semiconductor die, with a die embedded within a substrate that is surrounded by an elastomer. The package includes nonconductive layers on surfaces of the substrate and the elastomer as well as conductive layers and conductive vias that extend through these layers to form electrical connections in the package. The package includes surfaces of the conductive material, which may be referred to as contacts. These surfaces of the conductive material are exposed on both sides of the package and allow the package to be mounted within an electronic device and have other electronic components coupled to the package, or allow the package to be included in a stacked configuration of semiconductor dice or packages.

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Abstract: A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

Abstract: The present disclosure provides a semiconductor device package and a method of manufacturing the same. The semiconductor device package includes a substrate, an interconnection structure, a package body, and a first electronic component. The interconnection structure is disposed on the substrate. The package body is disposed on the substrate and partially covers the interconnection structure. The package body has a position limiting structure around the interconnection structure. The first electronic component is disposed on the interconnection structure and electrically connected to the interconnection structure.

Abstract: This disclosure is related to integrating optoelectronics microdevices into a system substrate for efficient and durable electrical bonding between two substrates at low temperature. 2D nanostructures and 3D scaffolds may create interlocking structures for improved bonding properties. Addition of nanoparticles into the structure creates high surface area for better conduction. Application of curing agents before or after alignment of micro devices and receiving substrates further assists with formation of strong bonds.

Abstract: A first substrate having a first face and a second face is prepared. The first face has a plurality of product regions defined thereon. An electrode pad forming side of each of a semiconductor chip stack and a semiconductor chip is attached to each corresponding product region of the plurality of product regions. The second face of the first substrate is thinned. A first inorganic insulating layer is formed on the second face. A first vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip stack. A second vertical interconnection penetrates the first inorganic insulating layer and the first substrate and is electrically connected to an electrode pad of the semiconductor chip. A first horizontal interconnection electrically connects a part of the first vertical interconnection to a part of the second vertical interconnection.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.

Abstract: A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

Abstract: A dielectric substrate has a first surface including a first terminal joint and a second terminal joint arranged along a first side surface. A first lead terminal is bonded to the first terminal joint with a bond. A second lead terminal is bonded to the second terminal joint with a bond. The first lead terminal includes a first base bonded to the first terminal joint and a first lead extending from the first base. The second lead terminal includes a second base bonded to the second terminal joint and a second lead extending from the second base. The first lead terminal includes the first base having a larger thickness than the first lead.

Abstract: In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Abstract: A laminated element manufacturing method includes a first forming step of forming a first modified region along a line to cut by irradiating a semiconductor substrate of a first wafer with a laser light along the line to cut, a first grinding step of grinding the semiconductor substrate of the first wafer, a bonding step of bonding a circuit layer of a second wafer to the semiconductor substrate of the first wafer, a second forming step of forming a second modified region along the line to cut by irradiating a semiconductor substrate of the second wafer with a laser light along the line to cut, and a second grinding step of grinding the semiconductor substrate of the second wafer.

Abstract: The present publication discloses a circuit-board structure, including a conductor layer on an insulating material layer, and a conductor pattern on top of the conductor foil. A component is attached to the conductor foil and the conductor pattern, the component embedded at least in part in adhesive which attaches the component to the insulating material layer. A recess is formed in the conductor foil and the insulating material layer, and contact openings are in the insulating material layer at locations of contact areas of the component. Conductor material of the conductor foil is not present outside the conductor pattern, and the conductor foil is located between the conductor pattern and the insulating material layer.

Abstract: A chip package includes a first substrate, a second substrate, a first conductive layer, and a metal layer. The first substrate has a bottom surface and an inclined sidewall adjoining the bottom surface, and an obtuse angle is between the bottom surface and the inclined sidewall. The second substrate is over the first substrate and has a portion that laterally extends beyond the inclined sidewall of the first substrate. The first conductive layer is between the first substrate and the second substrate. The metal layer is on said portion of the second substrate, on the bottom surface and the inclined sidewall of the first substrate, and electrically connected to an end of the first conductive layer.

Abstract: A flexible printed circuit board (FPCB), which is applied to various electronic display devices, may include a base, a first metal layer and a second metal layer on both surfaces of the base, a first plating layer on the first metal layer, a second plating layer on the second metal layer, and a first insulating pattern and a second insulating pattern respectively disposed on some region of the first plating layer and the second plating layer, wherein the first plating layer and the second plating layer may have different thicknesses.

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

Abstract: An antenna device includes a first substrate, a second substrate, an antenna layer, and a redistribution layer. The first substrate has a first surface, a second surface opposite to the first surface, and an inclined sidewall adjoining the first and second surfaces. The second substrate is below the first substrate. The first surface of the first substrate faces toward the second substrate. The antenna layer is located on the first surface of the first substrate. The redistribution layer extends from the second surface of the first substrate to the second substrate along the inclined sidewall of the first substrate, and the redistribution layer has a first section in contact with an end of the antenna layer.

Abstract: A method for fabricating a semiconductor device with a heterogeneous solder joint includes: providing a semiconductor die; providing a coupled element; and soldering the semiconductor die to the coupled element with a first solder joint. The first solder joint includes: a solder material including a first metal composition; and a coating including a second metal composition, different from the first metal composition, the coating at least partially covering the solder material. The second metal composition has a greater stiffness and/or a higher melting point than the first metal composition.

Abstract: A power semiconductor device includes a die carrier, a power semiconductor chip coupled to the die carrier by a first solder joint, a sleeve for a pin, the sleeve being coupled to the die carrier by a second solder joint, and a sealing mechanically attaching the sleeve to the die carrier, the sealing being arranged at a lower end of the sleeve, wherein the lower end faces the die carrier, and wherein the sealing does not cover the power semiconductor chip.

Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further incudes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.

Abstract: Various aspects of this disclosure provide a method of manufacturing an electronic device and an electronic device manufactured thereby. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing an electronic device, and an electronic device manufactured thereby, that utilizes ink to form an intermetallic bond between respective conductive interconnection structures of a semiconductor die and a substrate.

Abstract: A high speed signal transmitting and receiving detection device is provided. The high speed signal transmitting and receiving detection device includes a substrate unit and a plurality of probe units. The plurality of probe units pass through the substrate unit. The substrate unit includes a conducting space, a plurality of fillers and a plurality of barriers. Each of the fillers is arranged in the conducting space and between two of the probe units that are adjacent to each other. Each of the barriers is arranged in the conducting space and between the two of the probe units that are adjacent to each other. A capacitance effect between the two of the probe units that are adjacent to each other is formed through the filler and the barrier that correspond to the two of the probe units that are adjacent to each other.

Abstract: A semiconductor device includes wiring that is formed by a conductive body extending, via an insulating film, on a front surface of a semiconductor substrate, and an insulating layer that covers the front surface of the semiconductor substrate including the wiring. Gaps are provided extending from an upper surface of the wiring to a lower portion of the insulating film.

Abstract: A printed circuit board and an antenna module including the same are provided. The printed circuit board includes a core layer; a first build-up structure disposed on an upper side of the core layer, including first insulating layers and first bonding layers, alternately stacked, and further including first wiring layers disposed on upper surfaces of the first insulating layers, respectively, and embedded in the first bonding layers, respectively; and a second build-up structure disposed on a lower side of the core layer, including second insulating layers and second bonding layers, alternately stacked, and further including second wiring layers disposed on lower surfaces of the second insulating layers, respectively, and embedded in the second bonding layers, respectively. The printed circuit board has a through-portion penetrating through the core layer and the second build-up structure, and has a region in which the through-portion is disposed as a flexible region.

Abstract: A radio-frequency module includes a module substrate. The module substrate includes a first principal surface; a second principal surface on a side of the module substrate that is opposite to the first principal surface; a third principal surface that is recessed toward the first principal surface from the second principal surface in a plan view of the second principal surface; a recessed region in which the third principal surface is a bottom surface; and a protruding region located on an outer periphery of the recessed region, in a plan view of the second principal surface, wherein the protruding region has a via conductor disposed therein, the via conductor extending in a direction perpendicular to the second principal surface and having an end exposed on the second principal surface.

Abstract: Certain aspects of the present disclosure provide a glass ceramic antenna package having a large bandwidth (e.g., 19 GHz) for millimeter wave (mmWave) applications, for example. The antenna package generally includes an antenna element comprising a first substrate layer and a second substrate layer, wherein the first substrate layer comprises an antenna, wherein the second substrate layer comprises shielding elements and feed lines, and wherein the feed lines are electrically coupled to the antenna. The antenna package also includes a lead frame adjacent to one or more lateral surfaces of the antenna element.

Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

Abstract: An electrostatic chuck heater is such that a sheet heater formed by embedding a heater wire in a resin sheet is disposed between an electrostatic chuck and a support pedestal. The heater wires are provided one for each of many zones of the resin sheet, and are composed of copper wires routed unicursally from their first ends to their second ends so as to extend throughout the zones.

Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.

Abstract: An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12, a first resin layer 14 and a third resin layer 15 that are located above the semiconductor substrate, a second resin layer 16 that is formed such that at least portions of the second resin layer are located on the first resin layer and the third resin layer, a resin projection 17 that includes the first to third resin layers and is higher than the first resin layer, and a wiring layer 24 that is electrically connected to the electrode pad and lies above the resin projection.

Abstract: A wiring board includes a metal core including a first surface and a second surface facing each other and a first portion and a second portion disposed on the first and second surfaces, respectively. The first and second portions each include a plurality of insulating layers and a plurality of wiring layers stacked in an alternating manner. At least one capacitor is disposed in at least one interior region. The at least one capacitor includes first and second electrodes. The at least one interior region exposes a portion of the metal core and a portion of at least one of the first and second portions adjacent to the metal core and at least one first via electrically connects one of the wiring layers of the first portion with the first and second electrodes.

Abstract: A printed circuit board includes: a substrate; a land that is disposed on a surface of the substrate, and includes a central portion and a plurality of extended portions, the central portion having the same shape and the same size as a land of a surface mount device, and the extended portions being up-and-down symmetry and right-and-left symmetry with respect to a straight line which passes through the center of the central portion; gaps that are disposed on the surface of the substrate, each of the gaps being disposed on a periphery of the central portion and between the extended portions; and a resist that is disposed on the surface of the substrate, and has an opening portion formed at a position corresponding to the central portion and the gaps.

Abstract: Provided are a printed circuit board (PCB) having hexagonally aligned bump pads as a substrate of a semiconductor package, and a semiconductor package including the same. The PCB includes: a PCB body; a bottom metal layer at a bottom of the PCB body; and a top metal layer at a top of the PCB body, and the top metal layer includes: vias vertically connected to the PCB body; bump pads hexagonally aligned in a horizontal direction around the vias; and connection patterns connecting the vias to two or more of the bump pads. Accordingly, the number of bump pads in a unit area of the PCB may be increased.

Abstract: A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.

Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.

Abstract: A semiconductor package structure includes: a dielectric layer; a metal layer disposed on the dielectric layer and having a die pad and traces, the traces each including a trace body, a bond pad extending to the periphery of the die pad, and an opposite trace end; metal pillars penetrating the dielectric layer with one ends thereof connecting to the die pad and the trace ends while the other ends thereof protruding from the dielectric layer; a semiconductor chip mounted on the die pad and electrically connected to the bond pads through bonding wires; and an encapsulant covering the semiconductor chip, the bonding wires, the metal layer, and the dielectric layer. The invention is characterized by disposing traces with bond pads close to the die pad to shorten bonding wires and forming metal pillars protruding from the dielectric layer to avoid solder bridging encountered in prior techniques.

Abstract: A semiconductor package includes a first structural body having a first surface and a second surface which faces away from the first surface, and formed with first connection members on the first surface; a second structural body placed over the first structural body, and formed with second connection members on a surface thereof which faces the first surface of the first structural body; and an interposer interposed between the first structural body and the second structural body, and having a body which is formed with openings into which the first connection members and the second connection members are inserted and a conductive layer which is formed to fill the openings.

Abstract: A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

Abstract: A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump.