Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on the insulating layer and including a conductor pad, and a solder resist layer formed on the insulating layer such that the solder resist layer has an opening entirely exposing an upper surface and a side surface of the conductor pad. The conductor layer is formed such that the conductor pad has a pad body extending along a surface of the insulating layer, and a protective layer covering an upper surface and a side surface of the pad body and including material different from material of the pad body, and the pad body of the conductor pad has a notch part formed at a peripheral edge portion of the pad body such that the notch part separates a lower surface of the pad body and the surface of the insulating layer and is filled with the protective layer.

Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

Abstract: A light emitting diode (LED) device comprises: an interposer comprising: an interposer body, a plurality of pillars on a first surface of the interposer body, and two or more local fiducials on the first surface of the interposer body; an LED die comprising a die body and a first die surface comprising a plurality of light emitting diodes (LEDs), the LED die being mounted on the plurality of pillars; and a flux material located between each of the pillars and a second die surface of the die body, the second die surface of the die body being opposite the first die surface, there being no flux material on a fiducial surface of each of the local fiducials. Methods of manufacturing a light emitting diode (LED) devices comprise: printing a flux material onto the pillars of the interposer, attaching an LED die to the pillars, and washing away excess flux material.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and having a first portion and a second portion. The chip package structure includes a conductive bump over the second portion of the conductive pad. A third portion of the conductive pad is between the conductive bump and the conductive via structure from a top view of the conductive pad, the conductive bump, and the conductive via structure.

Abstract: An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.

Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

Abstract: An apparatus for forming a solder bump on a substrate including a supporter configured to support the substrate to be provided thereon, a housing surrounding the supporter, a cover defining a manufacturing space in combination with the housing and including an edge heating zone along a perimeter thereof, the manufacturing space surrounding the supporter, and an oxide remover supply nozzle configured to supply an oxide remover to the manufacturing space may be provided.

Abstract: A device for attaching conductive balls to a substrate includes a first plate, a second plate and a controller. The first plate includes first recesses. Each of the first recesses picks up a corresponding conductive ball to be attached to the semiconductor package. The second plate includes second recesses. Each of the second recesses picks up a corresponding conductive ball to be attached to the semiconductor package. The first plate and the second plate are separated from each other. The controller controls each of the first plate and the second plate to be separately moved up or down so that a lower surface of the first plate and a lower surface of the second plate are positioned differently in a first direction normal the lower surface of the first plate.

Abstract: A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.

Abstract: The present disclosure provides a fan-out wafer-level packaging structure and a method for packaging the same. The structure includes: two or more semiconductor chips with a bonding pad, the semiconductor chips are arranged in a fan-out wafer array, and each of the semiconductor chips has an initial position, respectively; a plastic packaging layer, covering surfaces of the semiconductor chips and between the semiconductor chips, each of the semiconductor chips has an offset position, respectively, and the offset position has an offset distance relative to the initial position; a redistribution layer formed on the semiconductor chips, to realize interconnection between the semiconductor chips, the redistribution layer includes at least one first redistribution layer, the first redistribution layer is formed on a surface of the semiconductor chips and is aligned and in contact with the bonding pad of the semiconductor chips; and a metal bump formed on the redistribution layer.

Abstract: A packaged semiconductor die with a bumpless die-package interface and methods of fabrication are described. For example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines, one of which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate. In another example, a semiconductor package includes a substrate having a land side with a lowermost layer of conductive vias. A semiconductor die is embedded in the substrate and has an uppermost layer of conductive lines with a layer of conductive vias disposed thereon. At least one of the conductive lines is coupled directly to a conductive via of the semiconductor die which is coupled directly to a conductive via of the lowermost layer of conductive vias of the substrate.

Abstract: The present disclosure provides a method that includes providing an integrated circuit (IC) substrate having various devices and an interconnection structure that couples the devices to an integrated circuit; forming a first passivation layer on the IC substrate; forming a redistribution layer on the first passivation layer, the redistribution layer being electrically connected to the interconnection structure; forming a second passivation layer on the redistribution layer and the first passivation layer; forming a polyimide layer on the second passivation layer; patterning the polyimide layer, resulting in a polyimide opening in the polyimide layer; and etching the second passivation layer through the polyimide opening using the polyimide layer as an etch mask.

Abstract: Rework and recovery processes generally include application of liquid metal etchant compositions to selectively remove one layer at a time of a solder layer and underball metallurgy multilayer stack including a titanium-based adhesion layer, a copper seed layer, a plated copper conductor layer, and a nickel-based barrier layer. The rework and recovery process can be applied to the dies, wafers, and/or substrate.

Abstract: A microelectronic device has a die with a die conductor at a connection surface. The microelectronic device includes a pillar electrically coupled to the die conductor, and a head electrically coupled to the pillar. The pillar has a die-side flared end at a die end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by more than a lesser of half a thickness of the die conductor and half a lateral width of the pillar midway between a die end and a head end. The pillar has a head-side flared end at a head end of the pillar; the pillar widens progressively along the die-side flared end, and extends outward by a distance that is greater than a lesser of half a thickness of the head and half the lateral width of the pillar. Methods of forming the microelectronic device are disclosed.

Abstract: A micro LED carrier board is provided. The micro LED carrier board includes a substrate structure having a first surface and a second surface and having a central region and a peripheral region on the outside of the central region. The micro LED carrier board includes a plurality of micro LED elements forming an array and on the second surface of the substrate structure. The micro LED carrier board includes a patterned structure formed on the first surface and the second surface. The patterned structure has a first pattern density in the central region and a second pattern density in the peripheral region, and the first pattern density is different from the second pattern density.

Abstract: A circuit substrate that includes a substrate having a major surface, a multilayer body on the major surface, and an insulating layer that covers the major surface. The multilayer body includes a first layer and a second layer that overlies the first layer. The first layer is made of a first metal as a main material thereof, and the second layer is made of a second metal as a main material thereof. The second metal has a higher solder wettability than the first metal. As viewed perpendicular to the major surface, the insulating layer is spaced from and surrounds the surface of the second layer so as to define a recess between the multilayer body and the insulating layer.

Abstract: A method for forming a semiconductor device structure and method for forming the same are provided. The method includes forming a conductive pad over the substrate, and forming a protection layer over the conductive pad. The method also includes forming a conductive structure accessibly arranged through the protection layer and electrically connected to the conductive pad, and the conductive structure has a curved top surface. A lowest point of the curved top surface of the conductive structure is higher than a topmost surface of the protection layer.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a conductive pad formed over a substrate, and a conductive structure formed over the conductive pad. The conductive structure has a curved top surface. The semiconductor device structure also includes a protection layer between the conductive pad and the conductive structure. A lowest point of the curved top surface of the conductive structure is higher than a topmost surface of the protection layer.

Abstract: An interposer comprises an insulating substrate having a first side and a second side; a first plurality of metal contacts on the first side; a second plurality of metal contacts on the second side; and a plurality of cuts through the insulating substrate. The plurality of cuts comprise a first cut between a first metal contact in the first plurality of metal contacts and a second metal contact in the first plurality of metal contacts, and between a first metal contact in the second plurality of metal contacts and a second metal contact in the second plurality of metal contacts.

Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a dielectric surface. A first protecting structure is on the dielectric surface. A conductive pad is on the dielectric surface and is leveled with the first protecting structure. A polymer layer is over the first protecting structure and the conductive pad. A conductive bump is electrically coupled to the conductive pad through an opening of the polymer layer. A method for manufacturing a semiconductor structure is also provided.

Abstract: An embedded component package structure including a dielectric structure and a component is provided. The component is embedded in the dielectric structure and is provided with a plurality of conductive pillars. The conductive pillars are exposed from an upper surface of the dielectric structure and have a first thickness and a second thickness, respectively, and the first thickness is not equal to the second thickness.

Abstract: A package structure including a redistribution structure, a die, at least one connecting module, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The connecting module is disposed on the redistribution structure. The connecting module has a protection layer and a plurality of conductive bars. The conductive bars are embedded in the protection layer. The protection layer includes a plurality of openings corresponding to the conductive bars. The first insulating encapsulant encapsulates the die and the connecting module. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the connecting module. The second insulating encapsulant encapsulates the chip stack.

Abstract: Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

Abstract: Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder bumps.

Abstract: A printed wiring board includes a conductor layer including first and second pads, a coating layer covering the conductor layer and having first opening exposing the first pad and second opening exposing the second pad, and metal bumps including a first bump on the first pad and a second bump on the second pad such that the first and second bumps protrude from the coating layer. The first and second openings are formed such that diameter of the second pad is smaller than diameter of the first pad. The first and second bumps are formed such that height of protruding portion of the first bump from the surface of the coating layer is substantially equal to height of protruding portion of the second bump from the surface of the coating layer and that the second bump covers an area of the coating layer on the surface surrounding the second opening.

Abstract: Some implementations are directed to a burn-in solder preform including: a barrier layer to prevent thermally conductive material from adhering to a semiconductor component during burn-in testing; and a thermally conductive cladding layer attached to a portion of the barrier layer such that at least one dimension of the barrier layer extends past the thermally conductive cladding layer, where the thermally conductive cladding layer is attached over the barrier layer through continuous attachment or spot attachment. In some implementations, a method includes: placing the aforementioned burn-in solder preform between a test fixture and a semiconductor component; attaching a portion of the barrier layer of the burn-in solder preform to a head of the text fixture; and after attaching a portion of the barrier layer of the burn-in solder preform to the head of the test fixture, performing burn-in testing of the semiconductor component.

Abstract: A semiconductor device type of field effect transistor (FET) primarily made of nitride semiconductor materials is disclosed. The FET includes a nitride semiconductor stack providing primary and auxiliary active regions and an inactive region surrounding the active regions; electrodes of a source, a drain, and a gate; an insulating film covering the electrodes and the semiconductor stack; and a field plate on the insulating film. A feature of the FET of the invention is that the field plate is electrically in contact with the auxiliary active region through the opening provided in the insulating film.

Abstract: A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Abstract: A method of making a semiconductor device can include providing a semiconductor die comprising a front surface comprising a gate pad and a source pad, the semiconductor die further comprising a back surface opposite the front surface, the back surface comprising a drain. A gate stud may be formed over and coupled to the gate pad. A source stud may be formed over and coupled to the source pad. An encapsulant may be formed over the semiconductor die. A through mold interconnect may extend between opposing first and second surfaces of the encapsulant. An RDL may be coupled to the gate stud, the source stud, and to the through mold interconnect. A land pad may be formed over the back surface of the semiconductor die and be coupled to the drain after singulating the semiconductor die from its native wafer and after forming the encapsulant over the semiconductor die.

Abstract: An integrated circuit (IC) chip can include a die with an interconnect conductively coupled to a leadframe, wherein the leadframe forms a portion of a given surface of the IC chip. The IC chip can also include an encapsulating material molded over the die and the leadframe. The encapsulating material can form another surface of the IC chip. The other surface of the IC chip opposes the given surface of the IC chip. The IC chip can further include a vertical wire extending through the encapsulating material in a direction that is substantially perpendicular to the given surface of the IC chip and the vertical wire protruding through the other surface of the IC chip to form a vertical connector for the IC chip. The vertical connector can be coupled to the interconnect on the die.

Abstract: A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.

Abstract: Disclosed is a semiconductor device and method of manufacturing a semiconductor device that includes planarizing surfaces of a semiconductor substrate and a carrier substrate and then placing the semiconductor substrate on the carrier substrate such that the planarized surfaces of each are adjoining and allowing the semiconductor substrate to bond to the carrier substrate using a Van der Waals force. The method also includes forming a metal filled trench around the semiconductor substrate and in contact with the carrier substrate, which can also be formed of metal. The metal filled trench and carrier substrate together form a metal cage-like structure around the semiconductor substrate that can serve as a heat sink, integrated heat spreader, and Electro-Magnetic Interference shield for the semiconductor substrate.

Abstract: A driving chip includes a body portion including a circuit. A first bump is electrically connected to the body portion. A second bump is disposed on the first bump. The second bump has a planar area less than a planar area of the first bump on a plane defined along a first direction parallel to an upper surface of the body portion. The first bump has a length of about 60 ?m or more in the first direction, a side surface of the second bump is aligned with a side surface of the first bump along a second direction orthogonal to the first direction.

Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

Abstract: A method for transferring a plurality of micro devices e is provided. The method includes picking up the micro devices from a carrier substrate by a transfer head, and iteratively performing a placing process. The placing process includes moving the transfer head to a position, at which an array of the micro devices is positioned over an array of receiving locations of a receiving substrate, and placing said array of the micro devices onto the array of the receiving locations of the receiving substrate.

Abstract: A transfer head is provided. The transfer head includes a body having a plurality of arrays of grip regions with each of the arrays comprising at least two columns of the grip regions. The grip regions in one of the columns are electrically connected in series. The columns in one of the arrays are controlled by a single voltage source, and the columns in two of the arrays are controlled by two voltage sources respectively.

Abstract: An integrated fan out package on package architecture is utilized along with de-wetting structures in order to reduce or eliminated delamination from through vias. In embodiments the de-wetting structures are titanium rings formed by applying a first seed layer and a second seed layer in order to help manufacture the vias. The first seed layer is then patterned into a ring structure which also exposes at least a portion of the first seed layer.

Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

Abstract: A chip inductor includes a substrate having a main surface, an insulating layer covering the main surface of the substrate, an external terminal formed on the insulating layer, and a coil conductor of a spiral-shape routed to a region outside the external terminal and a region facing the external terminal at the main surface of the substrate.

Abstract: A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is disposed on the substrate, wherein the conductive trace is elongated and carries a signal or a ground across at least a portion of the substrate. A die is mounted on the die attach surface of the substrate via a conductive pillar bump, the conductive pillar bump being rounded and elongated such that the conductive pillar bump extends along a length of the conductive trace and contacts the conductive trace at an end or at an intermediate portion thereof. The die further includes a metal pad electrically coupling to the conductive pillar bump, wherein the metal pad has a first edge and a second edge substantially vertical to the first edge, and wherein the first edge is not adjacent to the second edge.

Abstract: A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an under bump metallurgy (UBM) layer stacked over the electrode pad layer and the passivation layer, and a bump formed over the UBM layer. The width of an opening on which the passivation layer is not formed over the electrode pad layer is greater than the width of the bump. The flip chip can prevent a crack from being generated in the pad upon ultrasonic bonding.

Abstract: A semiconductor arrangement includes a semiconductor body with a first surface, an inner region and an edge region, the edge region surrounding the inner region, an attachment layer spaced apart from the first surface of the semiconductor body in a first direction, an intermediate layer arranged between the first surface of the semiconductor body and the attachment layer, and at least one first type sealing structure. The sealing structure includes a first barrier, a second barrier, and a third barrier. The first barrier is arranged in the intermediate layer and spaced apart from the attachment layer in the first direction. The second barrier is arranged in the intermediate layer, is spaced apart from the first surface in the first direction, and is spaced apart from the first barrier in a second direction. The third barrier extends from the first barrier to the second barrier in the second direction.

Abstract: A printed circuit board includes: an insulating layer; a plating seed layer disposed on the insulating layer; a circuit pattern layer disposed on the plating seed layer and formed of copper (Cu); and a surface treatment layer disposed on the circuit pattern layer and formed of gold (Au), wherein the circuit pattern layer includes a corner portion of an upper portion which has a curvature, and wherein the corner portion of the circuit pattern layer is a boundary surface between the top surface and a side surface of the circuit pattern layer, and the boundary surface has a concavely curved surface.

Abstract: An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug.

Abstract: A semiconductor manufacturing method includes a first process of etching an insulating film over a conductive layer of an object into a pattern of a mask, and exposing the conductive layer to a recessed portion formed in the insulating film, and a second process of forming an organic film in the recessed portion of the insulating film to which the conductive layer is exposed, the second process including, maintaining a chamber at a predetermined pressure, cooling a stage to ?20° C. or less, and placing the object on the stage, supplying a gas including a gas containing a low vapor pressure material to the chamber, and generating plasma from the gas including the gas containing the low vapor pressure material, and causing precursors generated from the low vapor pressure material and included in the plasma to be deposited in the recessed portion such that the organic film is formed.

Abstract: A semiconductor chip includes a semiconductor substrate including a bump region and a non-bump region, a bump on the bump region, and a passivation layer on the bump region and the non-bump region of the semiconductor substrate. No bump is on the non-bump region. A thickness of the passivation layer in the bump region is thicker than a thickness of the passivation layer in the non-bump region. The passivation layer includes a step between the bump region and the non-bump region.

Abstract: A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure.