Plural Conductive Layers Patents (Class 438/614)
  • Patent number: 10691868
    Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design (“CAD”) system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing (“CAM”) station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Utpal Bhattacharyya, Edward B. Acheson, Robert Roesler
  • Patent number: 10658267
    Abstract: A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more apertures each of which is tapered from a top surface to a bottom surface thereof. The carrier is positioned beneath the bottom of the decal and includes cavities in a top surface. The cavities are located in alignment with the apertures of the decal. The decal is positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities. The feature cavities are shaped to receive one or more metal elements and are configured for receiving molten solder cooled in the cavities. The decal is separable from the carrier to partially expose metal core solder contacts. The receiving elements receive the metal core solder contacts thereon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Jae-Woong Nah
  • Patent number: 10551432
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 10529650
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 10510723
    Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10461023
    Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
  • Patent number: 10354890
    Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yong Lin
  • Patent number: 10290604
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Patent number: 10229949
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10170442
    Abstract: A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Akio Furusawa, Hidetoshi Kitaura, Kazuki Sakai
  • Patent number: 10157873
    Abstract: A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 18, 2018
    Assignee: SK hynix Inc.
    Inventors: Jun-Hyun Cho, Young-Suk Ryu, Jae-Yong An, Il-Hwan Cho
  • Patent number: 10157872
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 18, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
  • Patent number: 10074595
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10074623
    Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho, Tzu-Yun Huang
  • Patent number: 10049997
    Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Il Choi, Hyoju Kim, Kwangjin Moon, Sujeong Park, Jubin Seo, Naein Lee, Ho-Jin Lee
  • Patent number: 10037957
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 31, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
  • Patent number: 9929117
    Abstract: An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal connection pads, a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads, and connection terminals disposed in the openings of the passivation layer and connected to the terminal connection pads. At least one of the openings of the passivation layer has a plurality of protrusion parts.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRO-MACHANICS CO., LTD.
    Inventors: Ji Hyun Lee, Sung Won Jeong, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook
  • Patent number: 9922922
    Abstract: A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over the redistribution conductors of the redistribution layer and in contact with the passivation layer. The passivation layer and the cap layer have one or more compatibilities that provide sufficient adhesion between those two layers to prevent metal migration from the conductors of the redistribution layer between the interfaces of the passivation and cap layers. In one embodiment, the passivation and cap layers are each formed from an inorganic oxide (e.g., SiO2) using a process (e.g., PECVD) that provides substantially-uniform step coverage by the cap layer in trench and via regions of underlying circuitry. The invention increases the reliability of the microchip, because it eliminates metal migration, and the electrical shorting caused therefrom, in the redistribution layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 20, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chi-Kuei Lee, Ying Chung, Ying-Chih Kuo, Wei-Feng Lin
  • Patent number: 9905524
    Abstract: A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chita Chuang, Yao-Chun Chuang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9865527
    Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yong Lin
  • Patent number: 9704781
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Patent number: 9685372
    Abstract: A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Hui-Jung Tsai, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 9607936
    Abstract: An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Jiun Yi Wu, Ru-Ying Huang, Chen-Shien Chen
  • Patent number: 9524945
    Abstract: An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 9491840
    Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chien Chang, Hsiang-Tai Lu, Dai-Jang Chen, Chih-Hsien Lin
  • Patent number: 9443807
    Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Thomas Ostermann
  • Patent number: 9431369
    Abstract: An antenna apparatus comprises a semiconductor die comprising a plurality of active circuits, a molding layer formed over the semiconductor die, wherein the semiconductor die and the molding layer form a fan-out package, a first dielectric layer formed on a first side of the semiconductor die over the molding compound layer, a first redistribution layer formed in the first dielectric layer and an antenna structure formed above the semiconductor die and coupled to the plurality of active circuits through the first redistribution layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: August 30, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lai Wei Chih, Monsen Liu, En-Hsiang Yeh, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9425092
    Abstract: A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to partially or fully fill the feature, depositing a copper fill to completely fill the feature if the feature is partially filled by the conductive layer, applying a copper overburden, thermally treating the workpiece, and removing the overburden to expose the substrate and the metalized feature.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 23, 2016
    Assignee: APPLIED Materials, Inc.
    Inventors: Ismail T. Emesh, Roey Shaviv, Mehul Naik
  • Patent number: 9385097
    Abstract: A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 9343363
    Abstract: Provided are methods for making a through-silicon via feature in a silicon substrate and related systems, such as by forming a noble metal structure on a silicon substrate support surface to generate silicon substrate contact regions that are in contact with or proximate to the noble metal structure; exposing at least a portion of the silicon substrate support surface and noble metal structure to an etchant to preferentially etch the silicon substrate contact regions compared to silicon substrate non-contact regions until the etch front reaches the silicon substrate bottom surface.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 17, 2016
    Assignee: Semprius, Inc.
    Inventors: Matthew Meitl, Christopher Bower
  • Patent number: 9299632
    Abstract: Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makio Okada, Takehiko Maeda
  • Patent number: 9295166
    Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: March 22, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 9287171
    Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Wen Wu, Cheng-Chung Lin, Chien Ling Hwang, Chung-Shi Liu
  • Patent number: 9281280
    Abstract: A bonding pad for thermocompression bonding of a carrier material to a further carrier material includes a base layer and a top layer. The base layer is made of metal, is deformable, and is connected to the carrier material. The metal is nickel-based. The top layer is metallic and is connected directly to the base layer. The top layer is arranged at least on a side of the base layer which faces away from the carrier material. The top layer has a smaller layer thickness than the base layer. In at least one embodiment, the top layer has a greater oxidation resistance than the base layer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: March 8, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Christoph Schelling, David Borowsky
  • Patent number: 9204551
    Abstract: Provided is a mounting structure capable of maintaining highly accurate connection reliability even when the temperature of the environment in which the mounting structure is used is high. Mounting structure (10) includes electronic component (11), metal (12), wiring substrate (13), and a preventing structure. Electronic component (11) includes first electrode (14). The melting point of metal (12) is 130° C. or less. Wiring substrate (13) includes second electrode (15) electrically connected to first electrode (14) via metal (12). The preventing structure prevents flowing-out of metal (12) in a melted state from a region where first electrode (14) and second electrode (15) are formed. Further, preventing structure (14) is formed in at least one member selected from electronic component (11) and wiring substrate (12).
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: December 1, 2015
    Assignee: Lenovo Innovations Limited (Hong Kong)
    Inventor: Masahiro Kubo
  • Patent number: 9202793
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming a protection layer on top of the contact pads and the substrate; exposing the contact pads from the protection layer; printing under bump metallization (UBM) layers over the exposed contact pads extended over the protection layer with conductive inks; and forming bumps on top of the under bump metallization layers. It also including: printing an adhesion layer using conductive ink, wherein the adhesion layer comprises interconnected adhesion layer pads; forming additional under bump metallization (UBM) layers and bumps on top of the adhesion layer pads utilizing an electro-deposition process; and removing connections among the interconnected adhesion layer pads.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: December 1, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Kyung Moon Kim, HeeJo Chi, JunMo Koo, Bartholomew Liao, Zigmund Ramirez Camacho
  • Patent number: 9190373
    Abstract: According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Soichi Yamashita, Masaya Shima
  • Patent number: 9177928
    Abstract: A semiconductor device fabrication method includes forming a barrier layer upon a dielectric layer, forming a pillar interconnect structure upon the barrier layer, forming solder upon the pillar interconnect structure, reflowing the solder to release solder voids, forming a perimeter material around at least a portion of an exposed sidewall of the pillar, and removing the barrier layer exterior to the pillar interconnect structure. Another fabrication method includes forming the barrier layer, forming the pillar interconnect structure, forming the solder upon the pillar interconnect structure, forming a perimeter material on exposed surfaces of the pillar interconnect structure, and removing the barrier layer on the surface of the dielectric layer exterior to the pillar interconnect structure.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: November 3, 2015
    Assignee: GlobalFoundries
    Inventors: Charles L. Arvin, Eric D. Perfecto, Wolfgang Sauter
  • Patent number: 9159683
    Abstract: Methods for etching copper in the fabrication of integrated circuits are disclosed. In one exemplary embodiment, a method for fabricating an integrated circuit includes providing an integrated circuit structure including a copper bump structure and a copper seed layer underlying and adjacent to the copper bump structure and etching the seed layer selective to the copper bump structure using a wet etching chemistry consisting of H3PO4 in a volume percentage of about 0.07 to about 0.36, H2O2 in a volume percentage of about 0.1 to about 0.7, and a remainder of H2O, and optionally NH4OH.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: October 13, 2015
    Assignees: GLOBALFOUNDRIES, INC., INTERMOLECULAR, INC.
    Inventors: Reiner Willeke, Tanya Atanasova, Anh Duong, Greg Nowling
  • Patent number: 9159674
    Abstract: A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: October 13, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mukta G. Farooq, Zhengwen Li, Zhijiong Luo, Huilong Zhu
  • Patent number: 9142498
    Abstract: An electrical interconnection can be provided using a bump stack including at least two solder bumps which are stacked on one another and at least one intermediate layer interposed between the at least stacked two solder bumps.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 22, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Boin Noh, Yonghwan Kwon, Sun-Hee Park
  • Patent number: 9131616
    Abstract: A metallized film-over-foam contact suitable for circuit grounding of surface mount technology devices generally includes a silicone foam resilient core member, a solderable electrically conductive layer, and an adhesive bonding the solderable electrically conductive layer to the resilient core member. The adhesive has no more than a maximum of 900 parts per million chlorine, no more than a maximum of 900 parts per million bromine, and no more than a maximum of 1,500 parts per million total halogens.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 8, 2015
    Assignee: Laird Technologies, Inc.
    Inventors: Weifan Wang, Yi-Shen Lin, Larry D. Creasy, Jr.
  • Patent number: 9105616
    Abstract: Disclosed herein are an external connection terminal part, a semiconductor package having the external connection terminal part, and a method for manufacturing the same. According to a preferred embodiment of the present invention, the external connection terminal part includes an insulating material and metal plating pattern formed on both surfaces of the insulating material.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 11, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Seob Hong, Eun Jung Jo, Kyu Hwan Oh, Kang Hyun Lee
  • Patent number: 9095081
    Abstract: Multiple injections of molten solder are employed to form double solder bumps having outer layers that melt at lower temperatures than the inner portions thereof. During a flip chip assembly process, the reflow temperature is above the melting temperature of the outer layers and below the melting temperature of the inner portions of the solder bumps. As the inner portions of the solder bumps do not collapse during reflow, a flip chip assembly can be made at relatively low temperatures and have a high stand-off height. A structure having double solder bumps facilitates flip chip assembly.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Paul A. Lauro, Jae-Woong Nah
  • Patent number: 9082762
    Abstract: A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: July 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Sung K. Kang, Paul A. Lauro, Minhua Lu, Da-Yuan Shih
  • Patent number: 9074294
    Abstract: Coated articles and methods for applying coatings are described. In some cases, the coating can exhibit desirable properties and characteristics such as durability, corrosion resistance, and high conductivity. The articles may be coated, for example, using an electrodeposition process.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: July 7, 2015
    Assignee: Xtalic Corporation
    Inventors: John Cahalen, Alan C. Lund, Christopher A. Schuh
  • Publication number: 20150145125
    Abstract: Disclosed is an under bump metallization structure including a plurality of metal or metal alloy layers formed on chip bond pads with improved reliability due to a sacrificial metal oxide and the methods of making the under bump metallization structures.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Richard Allen Faust, Joseph Nguyen
  • Patent number: 9040409
    Abstract: Embodiments of the present invention are directed to processes for making solar cells by simultaneously co-firing metal layers disposed both on a first and a second surface of a bifacial solar cell substrate. Embodiments of the invention may also provide a method forming a solar cell structure that utilize a reduced amount of a silver paste on a front surface of the solar cell substrate and a patterned aluminum metallization paste on a rear surface of the solar cell substrate to form a rear surface contact structure. Embodiments can be used to form passivated emitter and rear cells (PERC), passivated emitter rear locally diffused solar cells (PERL), passivated emitter, rear totally-diffused (PERT), “iPERC,” Crystalline Reduced-cost Aluminum Fire-Through (CRAFT), pCRAFT, nCRAFT or other high efficiency cell concepts.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 26, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prabhat Kumar, Michael P. Stewart, Kalyan Rapolu, Lin Zhang, Hari K. Ponnekanti
  • Patent number: 9040407
    Abstract: A method including depositing an alloying layer along a sidewall of an opening and in direct contact with a seed layer, the alloying layer includes a crystalline structure that cannot serve as a seed for plating a conductive material, exposing the opening to an electroplating solution including the conductive material, the conductive material is not present in the alloying layer, applying an electrical potential to a cathode causing the conductive material to deposit from the electroplating solution onto the cathode exposed at the bottom of the opening and causing the opening to fill with the conductive material, the cathode includes an exposed portion of the seed layer and excludes the alloying layer, and forming a first intermetallic compound along an intersection between the alloying layer and the conductive material, the first intermetallic compound is formed as a precipitate within a solid solution of the alloying layer and the conductive material.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Troy L. Graves-Abe
  • Patent number: 9040408
    Abstract: Semiconductor package devices, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 26, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Tiao Zhou, Joseph W. Serpiello, Md. Kaysar Rahim, Yong L. Xu, Karthik Thambidurai, Viren Khandekar