Plural Conductive Layers Patents (Class 438/614)
  • Patent number: 11343916
    Abstract: A component carrier has a stack including at least one electrically conductive layer structure and/or at least one electrically insulating layer structure. A component is embedded in the stack. The component includes a redistribution structure with at least one vertically protruding electrically conductive pad, and an electrically conductive material on at least part of said at least one pad. A method of manufacturing a component carrier is also disclosed.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: May 24, 2022
    Assignee: AT&S(China) Co. Ltd.
    Inventor: Mikael Tuominen
  • Patent number: 11335703
    Abstract: The present disclosure provides a display panel, a method for manufacturing the same, and a display device. The insulation layer is provided above the first conductive electrodes in the bonding area of the display panel, the insulation layer covers the first conductive electrodes, and the insulation layer is capable of being pierced by ACF particles. When the display panel is bound to an FPC by an ACF, second conductive electrodes on the FPC can be electrically coupled to the first conductive electrodes on the display panel through the ACF particles, thereby achieving the bonding connection between the display panel and the FPC, even if a conductive foreign object falls into the area where the first conductive electrodes are located, short circuit cannot be caused, thereby improving the product yield.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: May 17, 2022
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dexiong Song, Zhiyong Yang, Liwei Huang, Shihua Huang, Xue Jiang, Shibing Yuan, Fei Chen, Wei Li, Chao Fu, Na Zhang, Yu Du, Xuemei Deng
  • Patent number: 11335595
    Abstract: Provided is a semiconductor element including: a front-back conduction-type substrate including a front-side electrode and a back-side electrode; and an electroless plating layer formed on at least one of the electrodes of the front-back conduction-type substrate. The electroless plating layer includes: an electroless nickel-phosphorus plating layer; and an electroless gold plating layer formed on the electroless nickel-phosphorus plating layer, and has a plurality of recesses formed on a surface thereof to be joined with solder.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: May 17, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masatoshi Sunamoto, Ryuji Ueno
  • Patent number: 11335630
    Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: May 17, 2022
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
  • Patent number: 11270978
    Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 11251145
    Abstract: A semiconductor substrate has, on an Au electrode pad, an electrolessly-plated Ni film/an electrolessly-plated Pd film/an electrolessly-plated Au film or an electrolessly-plated Ni film/an electrolessly-plated Au film and a method of manufacturing the semiconductor substrate by the steps indicated in (1) to (6) below: (1) a degreasing step; (2) an etching step; (3) a pre-dipping step; (4) a Pd catalyst application step; (5) an electroless Ni plating step; (6) an electroless Pd plating step and electroless Au plating step or an electroless Au plating step.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: February 15, 2022
    Assignee: JX NIPPON MINING & METALS CORPORATION
    Inventors: Takuto Watanabe, Katsuyuki Tsuchida
  • Patent number: 11217548
    Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 11211352
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device structure including a bump structure overlying a bond pad. The bond pad is disposed over a semiconductor substrate. An etch stop layer overlies the bond pad. A buffer layer is disposed over the bond pad and separates the etch stop layer and the bond pad. The bump structure includes a base portion contacting an upper surface of the bond pad and an upper portion extending through the etch stop layer and the buffer layer. The base portion of the bump structure has a first width or diameter and the upper portion of the bump structure has a second width or diameter. The first width or diameter being greater than the second width or diameter.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Chern-Yow Hsu
  • Patent number: 11195785
    Abstract: An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yukyung Park, Seungkwan Ryu, Yunseok Choi
  • Patent number: 11177175
    Abstract: Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: William M. Hiatt, Kyle K. Kirby
  • Patent number: 11164830
    Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.
    Type: Grant
    Filed: October 7, 2018
    Date of Patent: November 2, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Dietrich Bonart, Ludger Borucki, Martina Debie, Bernhard Weidgans
  • Patent number: 11164845
    Abstract: A method for fabricating a resist structure is presented. The method includes preparing a substrate on which plural conductive pads are formed; and patterning a lower resist to form plural lower cavities. The lower resist is deposited above the substrate. Each of the plural lower cavities are located above a corresponding one of the plural conductive pads. Additionally, the method includes patterning an upper resist to form plural upper cavities. The upper resist is deposited on the lower resist. Each of the plural upper cavities are located on a corresponding one of the plural lower cavities and have a diameter larger than a diameter of the corresponding one of the plural lower cavities.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eiji Nakamura, Toyohiro Aoki, Takashi Hisada, Risa Miyazawa
  • Patent number: 11152323
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Yu Li, Hung-Jui Kuo, Li-Hsien Huang, Hsien-Wei Chen, Der-Chyang Yeh, Chung-Shi Liu, Shin-Puu Jeng
  • Patent number: 11145623
    Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Hsu, Yung-Chi Lin, Wen-Chih Chiou
  • Patent number: 11139260
    Abstract: A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11127705
    Abstract: A semiconductor structure includes a substrate; a conductive pad disposed over the substrate; a passivation disposed over the substrate and covering a portion of the conductive pad; a bump pad disposed over the conductive pad and the passivation; a conductive bump including a conductive pillar disposed over the bump pad and a soldering member disposed over the conductive pillar; and a dielectric member disposed over the passivation and surrounding the conductive pillar.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Tung-Jiun Wu
  • Patent number: 11114337
    Abstract: A method is provided for bonding and interconnecting two semiconductor chips arranged on semiconductor substrates. HSQ (Hydrogen Silsesquioxane) or an equivalent material is used as a bonding layer and after bonding and thinning one of the wafers (or first thinning and then bonding), the bond layer is locally irradiated by an e-beam through the thinned substrate, thereby locally transforming the bonding material into silicon oxide. Then a via opening is etched through the thinned substrate and an etch process selectively removes the oxide from an area delimited by the bonding material or vice versa. The filling of the via opening establishes an electrical connection between the bonded wafers, that is equivalent to a connection obtained by hybrid bonding, but that does not suffer from the disadvantages thereof.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 7, 2021
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Julien Jussot, Geert Van der Plas
  • Patent number: 11086220
    Abstract: Underlayer coating compositions are provided that comprise 1) a resin; and a solvent component comprising one or more solvents having a boiling of 200° C. or greater. Coating compositions are particularly useful with overcoated photoresist compositions imaged with EUV.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 10, 2021
    Assignee: Rohm and Haas Electronic Materials Korea Ltd.
    Inventors: Jung Kyu Jo, Jae Hwan Sim
  • Patent number: 10886244
    Abstract: The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and associated systems. A semiconductor die includes a semiconductor material having solid-state components and an interconnect extending at least partially through the semiconductor material. An under-bump metal (UBM) structure is formed over the semiconductor material and is electrically coupled to corresponding interconnects. A collar surrounds at least a portion of the side surface of the UBM structure, and a solder material is disposed over the top surface of the UBM structure.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giorgio Mariottini, Sameer Vadhavkar, Wayne Huang, Anilkumar Chandolu, Mark Bossier
  • Patent number: 10861711
    Abstract: A method of manufacturing a semiconductor structure includes forming a precursor structure including a plurality of conductive pads on a substrate, an etch stop layer between the conductive pads, and an UBM layer on the conductive pads and the etch stop layer. A plurality of mask structures are formed on the UBM layer, and a plurality of openings are formed between thereof. Each of the mask structures is located on one of the conductive pads, and the openings expose a first portion of the UBM layer. A supporting layer is formed in the openings. The mask structures are removed to form a plurality of cavities exposing a second portion of the UBM layer. A conductive material layer is formed in the cavities. The supporting layer is removed. The first portion of the UBM layer is removed to form a plurality of conductive bumps separated from each other.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: December 8, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 10854569
    Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die has a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang
  • Patent number: 10804312
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit 5 of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive 10 material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Patent number: 10691868
    Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include an electronic computer aided design (“CAD”) system configured to receive one or more design rules and to receive one or more manufacturing rules. The CAD system may be further configured to analyze design database objects from the electronic design with respect to the manufacturing rules. The CAD system may generate a manufacturing output file, based upon, at least in part, the analyzing. Embodiments may also include a signoff computer aided manufacturing (“CAM”) station configured to receive the manufacturing output file. The CAM station may be configured to attempt to validate the manufacturing output file.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: June 23, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Randall Scott Lawson, Utpal Bhattacharyya, Edward B. Acheson, Robert Roesler
  • Patent number: 10658267
    Abstract: A system of producing metal cored solder structures on a substrate includes: a decal, a carrier, and receiving elements. The decal includes one or more apertures each of which is tapered from a top surface to a bottom surface thereof. The carrier is positioned beneath the bottom of the decal and includes cavities in a top surface. The cavities are located in alignment with the apertures of the decal. The decal is positioned on the carrier having the decal bottom surface in contact with the carrier top surface to form feature cavities defined by the decal apertures and the carrier cavities. The feature cavities are shaped to receive one or more metal elements and are configured for receiving molten solder cooled in the cavities. The decal is separable from the carrier to partially expose metal core solder contacts. The receiving elements receive the metal core solder contacts thereon.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Peter A. Gruber, Jae-Woong Nah
  • Patent number: 10551432
    Abstract: A semiconductor device is manufactured at an improved efficiency. The method of the invention includes a step of carrying out an electrical test by bringing an external terminal electrically coupled to a semiconductor chip mounted on a semiconductor device into contact with a tip portion of a probe pin coupled to a test circuit and thereby electrically coupling the semiconductor chip to the test circuit. The probe pin has a tip portion comprised of a base material, a nickel film formed thereon, and a conductive film formed thereon and made of silver. The conductive film is thicker than the nickel film.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Toshitsugu Ishii, Naohiro Makihira, Hidekazu Iwasaki, Jun Matsuhashi
  • Patent number: 10529650
    Abstract: In an embodiment, a device includes: an integrated circuit die; a first dielectric layer over the integrated circuit die; a first metallization pattern extending through the first dielectric layer to electrically connect to the integrated circuit die; a second dielectric layer over the first metallization pattern; an under bump metallurgy extending through the second dielectric layer; a third dielectric layer over the second dielectric layer and portions of the under bump metallurgy; a conductive ring sealing an interface of the third dielectric layer and the under bump metallurgy; and a conductive connector extending through the center of the conductive ring, the conductive connector electrically connected to the under bump metallurgy.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, An-Jhih Su, Der-Chyang Yeh, Li-Hsien Huang, Ming Shih Yeh
  • Patent number: 10510723
    Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10461023
    Abstract: Semiconductor package s and methods of forming the same are disclosed. The semiconductor package includes a chip, a redistribution circuit structure and a UBM pattern. The redistribution circuit structure is disposed over and electrically connected to the chip and includes a topmost conductive pattern. The UBM pattern is disposed over and electrically connected to the topmost conductive pattern, wherein the UBM pattern includes a set of vias and a pad on the set of vias, wherein the vias are arranged in an array and electrically connected to the pad and the topmost conductive pattern.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mao-Yen Chang, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Tzung-Hui Lee, Teng-Yuan Lo, Hao-Chun Ting
  • Patent number: 10354890
    Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: July 16, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yong Lin
  • Patent number: 10290604
    Abstract: Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Lin-Chih Huang, Hung-An Teng, Hsin-Yu Chen, Tsang-Jiuh Wu, Cheng-Chieh Hsieh
  • Patent number: 10229949
    Abstract: A semiconductor device includes a lower device and an upper device disposed on the lower device. The lower device includes a lower substrate, a lower plug pad disposed on the lower substrate, and a lower interlayer dielectric layer on the lower plug pad. The upper device includes an upper substrate, an etch-delay structure in a lower portion of the upper substrate, an upper plug pad disposed on a bottom surface of the upper substrate, an upper interlayer dielectric layer on the upper plug pad, and a via plug configured to penetrate the upper substrate and contact the upper plug pad and the lower plug pad. The via plug includes a first portion in contact with the upper plug pad and the first etch-delay structure, and a second portion in contact with the lower plug pad.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 12, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-Jun Park, Chang-Rok Moon, Seung-Hun Shin, Seong-Ho Oh, Tae-Seok Oh, June-Taeg Lee
  • Patent number: 10170442
    Abstract: A mount structure includes two members that are bonded to each other with a bonding material layer having a first interface layer and a second interface layer at the interfaces with the two members. The bonding material layer contains a first intermetallic compound and a stress relaxation material. The first intermetallic compound has a spherical, a columnar, or an oval spherical shape, and the same crystalline structure as the first interface layer and the second interface layer, and partly closes the space between the first interface layer and the second interface layer. The stress relaxation material contains tin as a main component, and fills around the first intermetallic compound.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: January 1, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kiyohiro Hine, Akio Furusawa, Hidetoshi Kitaura, Kazuki Sakai
  • Patent number: 10157872
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 18, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
  • Patent number: 10157873
    Abstract: A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: December 18, 2018
    Assignee: SK hynix Inc.
    Inventors: Jun-Hyun Cho, Young-Suk Ryu, Jae-Yong An, Il-Hwan Cho
  • Patent number: 10074623
    Abstract: A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Hui Lee, Hung-Jui Kuo, Ming-Che Ho, Tzu-Yun Huang
  • Patent number: 10074595
    Abstract: An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ku-Feng Yang, Ming-Tsu Chung, Hong-Ye Shih, Jiung Wu, Chen-Yu Tsai, Hsin-Yu Chen, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10049997
    Abstract: A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper layer and a second copper layer sequentially stacked on the pad and a solder ball on the second copper layer. A first X-ray diffraction (XRD) peak intensity ratio of (111) plane to (200) plane of the first copper layer is greater than a second XRD peak intensity ratio of (111) plane to (200) plane of the second copper layer.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 14, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Il Choi, Hyoju Kim, Kwangjin Moon, Sujeong Park, Jubin Seo, Naein Lee, Ho-Jin Lee
  • Patent number: 10037957
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 31, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Greg Hames, Glenn Rinne, Devarajan Balaraman
  • Patent number: 9929117
    Abstract: An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal connection pads, a passivation layer disposed on one side of the redistribution layer and having openings exposing at least portions of the terminal connection pads, and connection terminals disposed in the openings of the passivation layer and connected to the terminal connection pads. At least one of the openings of the passivation layer has a plurality of protrusion parts.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRO-MACHANICS CO., LTD.
    Inventors: Ji Hyun Lee, Sung Won Jeong, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook
  • Patent number: 9922922
    Abstract: A microchip includes a passivation layer formed over underlying circuitry, a redistribution layer formed over the passivation layer, and a cap layer formed over the redistribution conductors of the redistribution layer and in contact with the passivation layer. The passivation layer and the cap layer have one or more compatibilities that provide sufficient adhesion between those two layers to prevent metal migration from the conductors of the redistribution layer between the interfaces of the passivation and cap layers. In one embodiment, the passivation and cap layers are each formed from an inorganic oxide (e.g., SiO2) using a process (e.g., PECVD) that provides substantially-uniform step coverage by the cap layer in trench and via regions of underlying circuitry. The invention increases the reliability of the microchip, because it eliminates metal migration, and the electrical shorting caused therefrom, in the redistribution layer.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: March 20, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chi-Kuei Lee, Ying Chung, Ying-Chih Kuo, Wei-Feng Lin
  • Patent number: 9905524
    Abstract: A bump structure in a semiconductor device or a packing assembly includes an under-bump metallization (UBM) layer formed on a conductive pad of a semiconductor substrate. The UBM layer has a width greater than a width of the conductive pad.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: February 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chita Chuang, Yao-Chun Chuang, Tsung-Shu Lin, Chen-Cheng Kuo, Chen-Shien Chen
  • Patent number: 9865527
    Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: January 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Yong Lin
  • Patent number: 9704781
    Abstract: The present technology is directed to manufacturing semiconductor dies with under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects or other types of interconnects. In one embodiment, a method for forming under-bump metal (UBM) structures on a semiconductor die comprises constructing a UBM pillar by plating a first material onto first areas of a seed structure and depositing a second material over the first material. The first material has first electrical potential and the second material has a second electrical potential greater than the first electrical potential. The method further comprises reducing the difference in the electrical potential between the first material and the second material, and then removing second areas of the seed structure between the UBM pillars thereby forming UBM structures on the semiconductor die.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: July 11, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Brandon P. Wirz, Jaspreet S. Gandhi, Christopher J. Gambee, Satish Yeldandi
  • Patent number: 9685372
    Abstract: A method of forming an integrated circuit device includes forming a conductive element over a substrate, wherein the conductive element is over an under bump metallurgy (UBM) layer, and the UBM layer comprises a first UBM layer and a second UBM layer over the first UBM layer. The method further includes etching the second UBM layer to expose a portion of the first UBM layer beyond a periphery of the conductive element. The method further includes forming a protection layer over sidewalls of the conductive element, over sidewalls of the second UBM layer and over a top surface of the first UBM layer. The method further includes etching the first UBM layer to remove a portion of the first UBM layer. The method further includes forming a cap layer over a top surface of the conductive element.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 20, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Hui-Jung Tsai, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 9607936
    Abstract: An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Wen Hsiao, Jiun Yi Wu, Ru-Ying Huang, Chen-Shien Chen
  • Patent number: 9524945
    Abstract: An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Yi-Wen Wu, Chung-Shi Liu
  • Patent number: 9491840
    Abstract: In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Chien Chang, Hsiang-Tai Lu, Dai-Jang Chen, Chih-Hsien Lin
  • Patent number: 9443807
    Abstract: A device includes a semiconductor chip. An outline of a frontside of the semiconductor chip includes at least one of a polygonal line including two line segments joined together at an inner angle of greater than 90° and an arc-shaped line.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Thomas Ostermann
  • Patent number: RE48421
    Abstract: Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: February 2, 2021
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIV.
    Inventors: Seung Boo Jung, Jong Woong Kim
  • Patent number: RE48422
    Abstract: Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: February 2, 2021
    Assignee: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIV.
    Inventors: Seung Boo Jung, Jong Woong Kim