Method of Forming Via Recess in Underlying Conductive Line
A method of fabricating a semiconductor device includes forming a via in a dielectric layer that opens to a conductive line underlying the dielectric layer, and forming a via recess in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line. The via recess may have a same size or smaller cross-section area than that of the via, for example. Such via structure may be part of a dual damascene structure in an intermetal dielectric structure, for example.
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This application is a divisional of U.S. patent application Ser. No. 11/652,210, entitled Method of Forming Via Recess in Underlying Conductive Line, filed Jan. 11, 2007, which is a divisional of U.S. patent application Ser. No. 10/823,159, now U.S. Pat. No. 7,180,193, entitled Via Recess in Underlying Conductive Line, filed on Apr. 13, 2004, which applications are incorporated herein by reference.
TECHNICAL FIELDThe present invention generally relates to fabricating semiconductor devices. In one aspect it relates more particularly to a method and structure for providing a via recess in an underlying conductive line.
BACKGROUNDIn the case shown in
The problems and needs outlined above may be addressed by embodiments of the present invention. In accordance with one aspect of the present invention, a semiconductor device is provided, which includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The conductive line is underlying the dielectric layer. The via is formed in the dielectric layer and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of at least about 100 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line.
In accordance with another aspect of the present invention, a semiconductor device is provided, which includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The dielectric layer includes an insulating material layer and a capped layer. The capped layer has a dielectric constant less than about 4.0. The conductive line underlies the dielectric layer. The via is formed in the insulating material layer, through the capped layer, and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of in a range from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line.
In accordance with yet another aspect of the present invention, a semiconductor device is provided, which includes a dielectric layer, a conductive line, a via, and a via recess in the conductive line. The dielectric layer includes an insulating material layer and a capped layer. The capped layer comprises silicon and carbon. The conductive line comprising copper underlies the dielectric layer. The via is formed in the insulating material layer, through the capped layer, and extends into the conductive line to form the via recess in the conductive line. The via recess formed in the conductive line has a depth of in a range from about 100 angstroms to about 600 angstroms. Via-fill material fills the via recess and at least partially fills the via, such that the via-fill material is electrically connected to the conductive line.
In accordance with still another aspect of the present invention, a method of fabricating a semiconductor device is provided. This method includes the following steps described in this paragraph. The order of the steps may be sequential and/or may overlap. A via is formed in a dielectric layer and opens to a conductive line underlying the dielectric layer. A via recess is formed in the conductive line at the via. The via recess in the conductive line has a depth ranging from about 100 angstroms to about 600 angstroms.
The foregoing has outlined rather broadly features of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.
The following is a brief description of the drawings, which illustrate exemplary embodiments of the present invention and in which:
Referring now to the drawings, wherein like reference numbers are used herein to designate like or similar elements throughout the various views, illustrative embodiments of the present invention are shown and described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations of the present invention based on the following illustrative embodiments of the present invention.
The capped layer 26 of
A via 30 is formed in the dielectric layer 24 and extends into the underlying conductive line 22 to form a via recess 40 in the conductive line 22. As measured from the top of the conductive line 22 at the via 30, the via recess 40 in the conductive line 22 preferably has a depth D of at least about 100 angstroms to provide more areas for subsequent metallic contact, to reduce via resistance, and to enhance physical adhesion between conductive line 22 and subsequent conductor 34. Lower via resistance will achieve higher performance circuits and better adhesion will result in a reliable metallization system. Especially when the size of via 30 is less than about 90 nanometers, the via recess may be necessary to achieve a high performance and reliable circuit. In a preferred embodiment, the via recess 40 has a depth DVR in a range from about 150 angstroms to about 300 angstroms, for example.
Via-fill material 42 fills the via recess 40 and the via 30 in
Only a portion 20 of the semiconductor device is shown in
There are numerous methods that may be used to fabricate a semiconductor device incorporating the first embodiment of the present invention and to arrive at the via structure shown in
An embodiment of the present invention may have an advantage of providing a lower via resistance through forming via recess 40 to provide more contacting areas between conductive line 22 and barrier layer 32, as compared to a prior art via structure (see e.g.,
Although embodiments of the present invention and at least some of its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods, and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
Claims
1. A method of fabricating a semiconductor device comprising:
- forming a via in a dielectric layer to a conductive line underlying the dielectric layer;
- forming a barrier layer along sidewalls of the via;
- forming a via recess through the barrier layer and into the conductive line at the via, the via recess in the conductive line having a depth ranging from about 100 angstroms to about 600 angstroms.
2. The method of claim 1, wherein the conductive line comprises a material selected from a group consisting of metal alloy, copper, aluminum, copper alloy, poly-crystalline silicon, metal silicide, compounds thereof, composites thereof, and combinations thereof.
3. The method of claim 1, wherein the barrier layer comprises a material selected from a group consisting of tantalum, tantalum nitride, tungsten, compounds thereof, composites thereof, and combinations thereof.
4. The method of claim 1, further comprising filling the via recess and at least partially filling the via with a via-fill material.
5. The method of claim 4, wherein the via-fill material comprises a conducting material and the barrier layer is located between at least part of the conducting material and at least part of the dielectric layer.
6. The method of claim 5, wherein the conducting material comprises material selected from a group consisting of metal alloy, copper, copper alloy, aluminum, aluminum alloy, tungsten, poly-crystalline silicon, compounds thereof, composites thereof, and combinations thereof.
7. The method of claim 1, wherein the dielectric layer comprises:
- a capped layer; and
- a layer of insulating material overlying the capped layer.
8. The method of claim 7, wherein the capped layer is a material comprising silicon-carbon having a thickness less than about 600 angstroms.
9. The method of claim 8, wherein the capped layer has at least 30% carbon.
10. The method of claim 1, wherein the size of the via is less than about 90 nanometers.
11. The method of claim 1, wherein the forming of the via recess includes a pre-metal cleaning process performed after the forming of the via.
12. The method of claim 11, wherein the pre-metal cleaning is a process selected from the group consisting of an argon sputter, an ammonia-based reactive process, a hydrogen-based reactive process, and combinations thereof.
13. The method of claim 1, wherein the depth of the via recess formed in the conductive line is between about 150 angstroms and about 300 angstroms.
14. The method of claim 1, wherein the depth of the via recess formed in the conductive line is between about 300 angstroms and about 600 angstroms.
15. A method of fabricating a semiconductor device comprising:
- forming a dielectric layer comprising an insulating material layer and a capped layer, wherein the capped layer has a dielectric constant less than about 4;
- forming a via in the dielectric layer, thereby exposing a conductive line underlying the dielectric layer;
- forming a barrier layer along sidewalls of the via and over the conductive line;
- removing at least a portion of the barrier layer to expose at least a portion of the conductive line;
- forming a via recess in the conductive line along a bottom of the via, the via recess in the conductive line having a depth ranging from about 100 angstroms to about 600 angstroms; and
- filling the via recess and at least partially filling the via with a via-fill material, such that the via-fill material is electrically connected to the conductive line.
16. The method of claim 15, wherein the capped layer is a material comprising silicon-carbon having a thickness less than about 600 angstroms, wherein the capped layer has at least 30% carbon.
17. The method of claim 15, wherein the forming of the via recess includes a pre-metal cleaning process performed after the forming of the via, wherein the pre-metal cleaning is a process selected from the group consisting of an argon sputter, an ammonia-based reactive process, a hydrogen-based reactive process, and combinations thereof.
18. A method of fabricating a semiconductor device comprising:
- forming a dielectric layer comprising an insulating material layer and a capped layer, wherein the capped layer is located between the insulating material layer and a conductive line underlying the dielectric layer, wherein the capped layer has a dielectric constant less than about 4, wherein the capped layer comprises silicon carbon, and wherein the capped layer comprises at least 30% carbon;
- forming a via in the dielectric layer, thereby exposing at least a portion of the conductive line;
- forming a barrier layer along sidewalls of the via;
- forming a via recess in the conductive line along a bottom of the via, the via recess extending through the barrier layer and having a depth in the conductive line ranging from about 100 angstroms to about 600 angstroms; and
- filling the via recess and at least partially filling the via with a via-fill material, such that the via-fill material is electrically connected to the conductive line, wherein the via-fill material comprises a conducting material in physical contact with the conductive line.
19. The method of claim 18, wherein the forming of the via recess includes a pre-metal cleaning process performed after the forming of the via.
20. The method of claim 19, wherein the pre-metal cleaning is a process selected from the group consisting of an argon sputter, an ammonia-based reactive process, a hydrogen-based reactive process, and combinations thereof.
Type: Application
Filed: Mar 1, 2010
Publication Date: Jun 24, 2010
Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. (Hsin-Chu)
Inventors: Chung-Shi Liu (Hsin-Chu), Chen-Hua Yu (Hsin-Chu), Horng-Huei Tseng (Hsin-Chu)
Application Number: 12/715,175
International Classification: H01L 21/768 (20060101);