Filling Of Holes, Grooves, Vias Or Trenches With Conductive Material (epo) Patents (Class 257/E21.585)
  • Patent number: 10981372
    Abstract: A three-dimensional inkjet printer and method for printing an aperture mask on a multi-spectral filter array. A custom tray is used by the printer allowing for printing on a prefabricated filter array. Photopolymer resin is deposited on the prefabricated filter array to form the aperture mask of dark mirror coating. An ultraviolet lamp illuminates the deposited photopolymer resin on the surface of the prefabricated multi-spectral optical filter array to cure the resin, thereby forming the mask. The prefabricated multi-spectral optical filter array includes an optical coating on at least one side, the aperture mask being formed on the optical coating, without the use of heat, chemical etching, or deformation of the optical coating.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 20, 2021
    Assignee: Materion Corporation
    Inventor: Kevin R. Downing
  • Patent number: 10920322
    Abstract: The present invention relates to a method for directly depositing palladium onto a non-activated surface of a gallium nitride semiconductor, the use of an acidic palladium plating bath (as defined below) for directly depositing metallic palladium or a palladium alloy onto a non-activated surface of a doped or non-doped gallium nitride semiconductor, and a palladium or palladium alloy coated, doped or non-doped gallium nitride semiconductor.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: February 16, 2021
    Assignee: Atotech Deutschland GmbH
    Inventor: Andreas Walter
  • Patent number: 10796956
    Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: October 6, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Patent number: 10672613
    Abstract: A method of forming a semiconductor structure includes forming a metal gate stack over a shallow trench isolation (STI) material in a semiconductor substrate, forming an interlayer dielectric over the STI material, recessing the interlayer dielectric to a height lower than a top surface of the metal gate stack, forming a helmet structure over the recessed interlayer dielectric, and after forming the helmet structure, etching the metal gate stack until reaching the STI material.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Uei Jang, Chien-Hua Tseng, Chung-Shu Wu, Ya-Yi Tsai, Ryan Chia-Jen Chen, An-Chyi Wei
  • Patent number: 10559497
    Abstract: Methods for filling a substrate feature with a seamless tungsten fill are described. The methods include depositing a tungsten film, oxidizing the tungsten film to a tungsten oxide pillar, reducing the tungsten oxide film to a seamless tungsten gapfill and optionally depositing additional tungsten on the tungsten gapfill.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 11, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wu, Yihong Chen, Shishi Jiang, Ziqing Duan, Abhijit Basu Mallick, Srinivas Gandikota
  • Patent number: 10546812
    Abstract: A liner-free or partial liner-free contact/via structure that is embedded within a dielectric capping layer and positioned between an electrically conductive structure and an overlying contact structure is provided.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 10510666
    Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Su-Jen Sung
  • Patent number: 10465287
    Abstract: A semiconductor device includes a substrate, a dielectric layer, a first tungsten layer, an interface layer and a second tungsten layer. The dielectric layer is disposed on the substrate and has a first opening and a second opening larger than the first opening. The first tungsten layer is filled in the first opening and is disposed in the second opening. The second tungsten layer is disposed on the first tungsten layer in the second opening, wherein the second tungsten layer has a grain size gradually increased from a bottom surface to a top surface. The interface layer is disposed between the first tungsten layer and the second tungsten layer, wherein the interface layer comprises a nitrogen containing layer. The present invention further includes a method of forming a semiconductor device.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 5, 2019
    Assignees: UNITED MICROELECTRONCIS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Pin-Hong Chen, Tsun-Min Cheng, Yi-Wei Chen
  • Patent number: 10468596
    Abstract: First stacked rail structures including a first conductive rail, a selector rail, and a sacrificial material rail and separated by first trenches are formed over a substrate. First dielectric isolation structures are formed in the first trenches. Second trenches are formed, which divides the first stacked rail structures above the first conductive rails. Second dielectric isolation structures in the second trenches. Pillar structures are formed, which include a respective vertical stack of a selector element and a sacrificial material pillar. The sacrificial material pillars are replaced with phase change memory material pillars by a damascene method that deposits and planarizes a phase change memory material. Second conductive rails are formed over the phase change memory material pillars. Sidewalls of the phase change memory material pillars are not subjected to etch damage, thereby enhancing electrical characteristics of the phase change memory material pillars.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: November 5, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Senaka Kanakamedala, Yao-Sheng Lee
  • Patent number: 10446469
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 10418236
    Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The dielectric composite film in one embodiment includes Al, Si, and O and has a thickness of between about 10-100 ?. The dielectric composite film can reside between two layers of inter-layer dielectric, and may be in contact with metal layers. An apparatus for depositing such dielectric composite films includes a process chamber, a conduit for delivering an aluminum containing precursor to the process chamber, a second conduit for delivering a silicon-containing precursor to the process chamber and a controller having program instructions for depositing the dielectric composite film from these precursors, e.g., by reacting the precursors adsorbed to the substrate with an oxygen-containing species.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: September 17, 2019
    Assignee: Lam Research Corporation
    Inventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
  • Patent number: 10403729
    Abstract: A semiconductor device has a high electric connection reliability and includes a base substrate having a connection target layer, a lower contact plug formed over the base substrate and electrically connected to the connection target layer, and an upper contact plug formed over the lower contact plug, wherein the lower contact plug includes a lower plug layer having a gap portion extending inward from a top portion of the lower plug layer, a gap cover layer filling the gap portion, and an upper cover layer covering a top surface of the lower plug layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Eui-bok Lee
  • Patent number: 10319695
    Abstract: A semiconductor device includes a semiconductor substrate. A pad region is disposed on the semiconductor substrate. A micro bump is disposed on the pad region. The micro bump has a first portion on the pad region and a second portion on the first portion. The first portion and the second portion have different widths. The first portion has a first width and the second portion has a second width. The first width is larger or smaller than the second width. The micro bump includes nickel and gold. The semiconductor device also includes a passivation layer overlying a portion of the pad region.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu Wu, Ching-Hui Chen, Mirng-Ji Lii, Kai-Di Wu, Chien-Hung Kuo, Chao-Yi Wang, Hon-Lin Huang, Zi-Zhong Wang, Chun-Mao Chiu
  • Patent number: 10297504
    Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Keith Tabakman, Ruilong Xie
  • Patent number: 10199342
    Abstract: A device and methods of forming the device are disclosed. A substrate with a circuits component and a dielectric layer with interconnects is provided. A pad level dielectric layer is formed over the dielectric layer. A primary passivation layer is formed over the pad level dielectric layer with pad interconnects. The substrate is subjected to an alloying process. During the alloying process, the primary passivation layer prevents or reduces formation of hillocks on surfaces of the pad interconnects to improve surface smoothness of the pad interconnects. Pad openings are formed in the pad level dielectric layer to expose top surfaces of the pad interconnects. A cap dielectric layer is formed on the substrate and lines the primary passivation layer as well as the exposed top surfaces of the pad interconnects. A final passivation layer is formed on the substrate and covers the cap dielectric layer. The final passivation layer is patterned to form final passivation openings corresponding to the pad openings.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xiaohua Zhan, Xinfu Liu, Yoke Leng Lim, Siow Lee Chwa
  • Patent number: 10189239
    Abstract: A three-dimensional inkjet printer and method for printing an aperture mask on a multi-spectral filter array. A custom tray is used by the printer allowing for printing on a prefabricated filter array. Photopolymer resin is deposited on the prefabricated filter array to form the aperture mask of dark mirror coating. An ultraviolet lamp illuminates the deposited photopolymer resin on the surface of the prefabricated multi-spectral optical filter array to cure the resin, thereby forming the mask. The prefabricated multi-spectral optical filter array includes an optical coating on at least one side, the aperture mask being formed on the optical coating, without the use of heat, chemical etching, or deformation of the optical coating.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: January 29, 2019
    Assignee: MATERION CORPORATION
    Inventor: Kevin R. Downing
  • Patent number: 10186463
    Abstract: An integrated electronic circuit has probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacturing including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. The process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: January 22, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10157866
    Abstract: A method includes depositing a dielectric layer over a substrate, patterning the dielectric layer to form a first opening and a second opening, wherein a width of the second opening is greater than a width of the first opening, forming a first metal layer over the dielectric layer, wherein a planar surface of the first metal layer in the second opening is lower than a top surface of the dielectric layer, forming a second metal layer in a conformal manner over the first metal layer, wherein a material of the first metal layer is different from a material of the second metal layer and applying a polishing process to the first metal layer and the second metal layer until the dielectric layer is exposed.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao Yun Lo, Lin-Chih Huang, Tasi-Jung Wu, Hsin-Yu Chen, Yung-Chi Lin, Ku-Feng Yang, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 10109525
    Abstract: A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 23, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Jiunn-Hsiung Liao, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10062647
    Abstract: Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 28, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anthony K. Stamper, Baozhen Li
  • Patent number: 10049927
    Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 14, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Bencherki Mebarki, Sean Kang, Keith Tatseun Wong, He Ren, Mehul B. Naik, Ellie Y. Yieh, Srinivas D. Nemani
  • Patent number: 10049869
    Abstract: Dielectric composite films characterized by a dielectric constant (k) of less than about 7 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers. The composite films in one embodiment include at least two elements selected from the group consisting of Al, Si, and Ge, and at least one element selected from the group consisting of O, N, and C. In one embodiment the composite film includes Al, Si and O. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) and, sequentially, with a silicon-containing compound. Adsorbed compounds are then treated with an oxygen-containing plasma (e.g., plasma formed in a CO2-containing gas) to form a film that contains Al, Si, and O.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 14, 2018
    Assignee: Lam Research Corporation
    Inventors: Kapu Sirish Reddy, Nagraj Shankar, Shankar Swaminathan, Meliha Gozde Rainville, Frank L. Pasquale
  • Patent number: 10026616
    Abstract: There is provided a method of reducing stress in a metal film that is highly stressed, the method including: processing the metal film by supplying a metal chloride gas containing a metal of the metal film and a reduction gas for reducing the metal chloride gas onto the metal film; and forming a process film on the metal film to reduce stress in the metal film.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: July 17, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kenji Suzuki, Takanobu Hotta, Koji Maekawa, Yasushi Aiba
  • Patent number: 9941196
    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin Lee, Tae-Je Cho, Dong-Hyeon Jang, Ho-Geon Song, Se-Young Jeong, Un-Byoung Kang, Min-Seung Yoon
  • Patent number: 9922872
    Abstract: Processing methods comprising exposing a substrate to a nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal-containing compound and a second reactive gas to form a metal-containing film on the substrate.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 20, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: David Knapp, Jeffrey W. Anthis, Xinyu Fu, Srinivas Gandikota
  • Patent number: 9870980
    Abstract: The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: January 16, 2018
    Assignee: MEDIATEK INC.
    Inventors: Ming-Tzong Yang, Yu-Hua Huang, Wei-Che Huang
  • Patent number: 9704803
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. In various embodiments, the method for forming a semiconductor structure includes following steps. A structure on a semiconductor substrate is received, which the structure includes at least two conductive lines and a shorting bridge, and the conductive lines electrically connected to each other through the shorting bridge. The shorting bridge is insulated to make the conductive lines electrically isolated to each other.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hung-Chih Yu, Chien-Mao Chen
  • Patent number: 9634013
    Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9633942
    Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Erik R. Hosler, Deniz E. Civay
  • Patent number: 9627498
    Abstract: A method is described for forming a circuit that comprises forming a layer of semiconductor material on the substrate and an interlayer conductor contacting the layer. The layer can be a thin film layer. An opening is etched in an interlayer insulator over a layer of semiconductor material, to expose a landing area on the layer of semiconductor material. The semiconductor material exposed by the opening is thickened by adding some of the semiconductor material within the opening. The process for adding the semiconductor material can include a blanket deposition, or a selective growth only within the landing area. A reaction precursor, such as a silicide precursor is deposited on the landing area in the opening. A reaction of the precursor with the semiconductor material in the opening is induced. An interlayer conductor is formed within the opening.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: April 18, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Jia-Rong Chiou, Yu-Wei Jiang, Teng-Hao Yeh
  • Patent number: 9536745
    Abstract: A tungsten film forming method for forming a tungsten film on a surface of a target substrate by an ALD (atomic layer deposition) method comprises adding a reduction gas to allow an ALD reaction to mainly occur when a tungsten chloride gas is supplied. In the ALD method, the tungsten chloride gas as a tungsten source gas and the reduction gas for reducing the tungsten chloride gas are alternately supplied into a chamber which accommodates the target substrate and is maintained under a depressurized atmosphere, with a purge process for purging an inside of the chamber performed between the supply of the tungsten chloride gas and the supply of the reduction gas.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 3, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kensaku Narushima, Takanobu Hotta, Tomohisa Maruyama, Yasushi Aiba
  • Patent number: 9450062
    Abstract: A semiconductor device includes a field effect transistor structure having source zones of a first conductivity type and body zones of a second conductivity type which is the opposite of the first conductivity type, the source zones adjoining a first surface of a semiconductor die comprising the source and the body zones. The semiconductor device further includes a dielectric layer adjoining the first surface and polysilicon plugs extending through openings in the dielectric layer and electrically connected to the source and the body zones. The polysilicon plugs have silicide crystallites in portions distant to the semiconductor die.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Ralf Siemieniec, Oliver Blank
  • Patent number: 9343357
    Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: May 17, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jeffrey Junhao Xu, John Jianhong Zhu, Choh Fei Yeap
  • Patent number: 9303788
    Abstract: Provided is a load lock device which includes: a container with an opening formed therein and configured to be selectively maintained at an atmospheric environment and a vacuum atmosphere; a holding unit arranged within the container and configured to hold objects to be processed; an elevation mechanism configured to vertically move the holding unit; and a pressure regulating mechanism configured to vacuum-evacuate the container through the opening of the container. The elevation mechanism includes at least two vertically-extended elevation shaft members connected to the holding unit; and a drive unit configured to vertically move the elevation shaft members. The elevation shaft members are arranged opposite each other with the opening interposed therebetween.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: April 5, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masamichi Hara, Tetsuya Miyashita
  • Patent number: 9275962
    Abstract: An integrated electronic circuit having probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacture including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. In an embodiment, the process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: March 1, 2016
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 9245661
    Abstract: A conductive film, a method for producing the same and an array substrate comprising the same are provided, so that copper atoms can be efficiently prevented from diffusing into an adjacent semiconductor layer or interlaminated insulation film. The conductive film comprises a base film made of copper or copper alloy, in which hydrogen and/or carbon atoms are distributed.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: January 26, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhang, Zhengliang Li, Zhen Liu, Luke Ding, Zhanfeng Cao, Guanbao Hui
  • Patent number: 9041087
    Abstract: Semiconductor device structures are provided. An exemplary semiconductor device structure includes a substrate of a semiconductor material and a gate structure overlying the substrate. The semiconductor substrate further includes a doped region formed in the substrate proximate the gate structure and a first dielectric material overlying the doped region. The semiconductor substrate also includes a conductive contact formed in the first dielectric material, the conductive contact being electrically connected to the doped region, and a dielectric cap overlying the conductive contact.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Lei Yuan, Jin Cho, Jongwook Kye
  • Patent number: 9018102
    Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: April 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohammed Radwan, Matthias Zinke
  • Patent number: 9012326
    Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: April 21, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nam-Gun Kim, Yoonjae Kim, Sungil Cho
  • Patent number: 8999827
    Abstract: A method of manufacturing a semiconductor device, includes: forming a first and second interconnect trenches adjacent to each other in an interlayer insulating film; providing a first interconnect and a space thereon within the first interconnect trench, and a second interconnect and a space thereon within the second interconnect trench; forming a first trench larger in width from the first interconnect trench and a second trench larger in width from the second interconnect trench, by conducting isotropic-etching; and forming a first insulating film within the first trench and a second insulating film within the second trench by filling an insulating material in the first trench and the second trench.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: April 7, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Toshiyuki Hirota
  • Patent number: 8999846
    Abstract: An integrated circuit structure includes a plurality of insulator layers (connected to each other) that form a laminated structure. Further included are via openings within each of the insulator layers, and conductive via material within the via openings. The conductive via material within corresponding via openings of adjacent insulator layers are electrically connected to form continuous electrical via paths through the insulator layers between the top surface and the bottom surface of the laminated structure. Within each of the continuous electrical via paths, the via openings are positioned relative to each other to form a diagonal structural path of the conductive via material through the laminated structure. The corresponding via openings of the adjacent insulator layers partially overlap each other. The diagonal structural paths are non-perpendicular to the top surface and the bottom surface.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Luke D. LaCroix, Mark C. H. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 9000579
    Abstract: An integrated circuit package system includes a substrate having an opening provided therein, forming a conductor in the opening having a closed end at the bottom, attaching an integrated circuit die over the substrate, and connecting a die interconnect to the integrated circuit die and the closed end of the conductor.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: April 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Dario S. Filoteo, Jr., Emmanuel Espiritu, Rachel Layda Abinan
  • Patent number: 8993439
    Abstract: A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Jun Kim, Kil-Ho Lee, Ki-Joon Kim, Myoung-Su Son
  • Patent number: 8987851
    Abstract: The invention provides a radio-frequency (RF) device package and a method for fabricating the same. An exemplary embodiment of a radio-frequency (RF) device package includes a base, wherein a radio-frequency (RF) device chip is mounted on the base. The RF device chip includes a semiconductor substrate having a front side and a back side. A radio-frequency (RF) component is disposed on the front side of the semiconductor substrate. An interconnect structure is disposed on the RF component, wherein the interconnect structure is electrically connected to the RF component, and a thickness of the semiconductor substrate is less than that of the interconnect structure. A through hole is formed through the semiconductor substrate from the back side of the semiconductor substrate, and is connected to the interconnect structure. A TSV structure is disposed in the through hole.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: March 24, 2015
    Assignee: MediaTek Inc.
    Inventors: Ming-Tzong Yang, Cheng-Chou Hung, Tung-Hsing Lee, Wei-Che Huang, Yu-Hua Huang
  • Patent number: 8987914
    Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Yen-Hao Shih, Yi-Hsuan Hsiao, Chih-Ping Chen
  • Patent number: 8980716
    Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 17, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Patent number: 8962455
    Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Choi, Jin-Ho Noh, Yoon-Ho Son, Dae-Hyuk Chung, In-Seak Hwang, Tae-Joon Park, Tae-Ho Hwang
  • Patent number: 8962485
    Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohamed Salama, Tuhin Guha Neogi, Scott Beasor
  • Patent number: 8962473
    Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Shiang Kuo, Ken-Yu Chang, Ya-Lien Lee, Hung-Wen Su
  • Patent number: 8951908
    Abstract: A method for manufacturing semiconductor device includes preparing a structure including a substrate, an insulating layer on the substrate and having a recess, a barrier film on the insulating layer, and a copper film on the barrier such that the copper film is filling the recess with the barrier between the insulating layer and copper film, removing the copper film down to interface with the barrier such that copper wiring is formed in the recess, etching the wiring such that surface of the wiring is recessed from surface of the insulating layer, and removing the barrier from the surface of the insulating layer such that the surface of the insulating layer is exposed. The etching includes positioning the structure removed down to the barrier in organic compound atmosphere having vacuum state, and irradiating oxygen gas cluster ion beam on the surface of the wiring to anisotropically etch the wiring.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 10, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Kenichi Hara, Takashi Hayakawa, Mariko Ozawa