With Formation Of Opening (i.e., Viahole) In Insulative Layer Patents (Class 438/637)
  • Patent number: 10784153
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 10741435
    Abstract: Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 11, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Yihong Chen, Kelvin Chan, Abhijit Basu Mallick, Srinivas Gandikota, Pramit Manna
  • Patent number: 10734278
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Patent number: 10692812
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi Prakash Srivastava, Hui Zang, Jiehui Shu
  • Patent number: 10658234
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Sung-Li Wang, Pei-Wen Wu, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi-On Chui
  • Patent number: 10658180
    Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Yongan Xu, Oleg Gluschenkov
  • Patent number: 10651283
    Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10644037
    Abstract: The present disclosure relates to a via-hole connection structure and a method of manufacturing the same and an array substrate and a method of manufacturing the same. In an embodiment, a method of manufacturing a via-hole connection structure, includes the following steps of: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a first conductive pattern on which a first photoresist pattern is provided; forming a first insulation layer covering the first conductive layer and the first photoresist pattern; patterning the first insulation layer to form a first via-hole from which at least a portion of the first photoresist pattern is exposed; removing the at least a portion of the first photoresist pattern exposed from the first via-hole; and forming a second conductive pattern, wherein the second conductive pattern is electrically connected to the first conductive pattern through the first via-hole.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELETRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xun Mou, Yawen Zhu
  • Patent number: 10636698
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
  • Patent number: 10600678
    Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Elliot N. Tan, Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10580692
    Abstract: A system and method of fabricating a semiconductor device include forming a series of gates, and forming a gate spacer on each side of each gate of the series of gates. The method includes forming a source region on a side of each of the gates and forming a drain region on an opposite side of each of the gates. The source region or the drain region between two adjacent ones of the gates is shared and only the source region or the drain region on one side of a first gate and the source region or the drain region on one side of a last gate in the series of gates are unshared source or drain regions. A self-aligned contact (SAC) is formed on the unshared source or drain regions. An air spacer is formed between the SACs and the first gate and the last gate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Ruilong Xie, Julien Frougier, Kangguo Cheng
  • Patent number: 10558121
    Abstract: In a method for producing a wired circuit board includes a step (1), in which the insulating layer having an inclination face is provided; a step (2), in which a metal thin film is provided on the surface of the insulating layer including the inclination face; a step (3), in which a photoresist is provided on the surface of the metal thin film; a step (4), in which a photomask is disposed so that a first light exposure portion and a second light exposure portion in the photoresist are exposed to light, and the photoresist is exposed to light; a step (5), in which the first light exposure portion and the second light exposure portion are removed; and a step (6), in which the first wire and the second wire are provided on the surface of the metal thin film.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 11, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 10553534
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Chun-Hsien Lin
  • Patent number: 10520817
    Abstract: In a method for producing a wired circuit board includes a step (1), in which the insulating layer having an inclination face is provided; a step (2), in which a metal thin film is provided on the surface of the insulating layer including the inclination face; a step (3), in which a photoresist is provided on the surface of the metal thin film; a step (4), in which a photomask is disposed so that a first light exposure portion and a second light exposure portion in the photoresist are exposed to light, and the photoresist is exposed to light; a step (5), in which the first light exposure portion and the second light exposure portion are removed; and a step (6), in which the first wire and the second wire are provided on the surface of the metal thin film.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 10522398
    Abstract: A metal interconnect structure can be fabricated within an integrated circuit (IC). A recess can be created in an IC dielectric layer and a surface modulation liner can be formed by depositing two different metallic elements onto the surfaces of the recess. One metallic element can have a standard electrode potential greater than a standard electrode potential of an interconnect metal, and the other metallic element can have a standard electrode potential less than the standard electrode potential of the interconnect metal. A metal interconnect structure can be formed by filling the remainder of the recess with interconnect metal, which is physically separated from the dielectric layer by the surface modulation liner. The surface topography of the metal interconnect structure can be modulated with a polishing process, by removing a top portion of the interconnect metal and a top portion of the surface modulation liner.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Conal Murray, Chih-Chao Yang
  • Patent number: 10522394
    Abstract: A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Runzi Chang, Min She
  • Patent number: 10510587
    Abstract: A method for manufacturing a semiconductor device includes forming a structure protruding from a substrate, forming a dielectric layer covering the structure, forming a dummy layer covering the dielectric layer, and performing a planarization process to completely remove the dummy layer. A material of the dummy layer has a slower removal rate to the planarization process than a material of the dielectric layer.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Chieh Huang, Chin-Wei Liang, Feng-Jia Shiu, Hsia-Wei Chen, Jieh-Jang Chen, Ching-Sen Kuo
  • Patent number: 10504845
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first insulating layer is formed over a first surface of the encapsulant and an active surface of the semiconductor die. A second insulating layer is formed over a second surface of the encapsulant opposite the first surface. A conductive layer is formed over the first insulating layer. The conductive layer includes a line-pitch or line-spacing of less than 5 ?m. The active surface of the semiconductor die is recessed within the encapsulant. A third insulating layer is formed over the semiconductor die including a surface of the third insulating layer coplanar with a surface of the encapsulant. The second insulating layer is formed prior to forming the conductive layer. A trench is formed in the first insulating layer. The conductive layer is formed within the trench.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: December 10, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventor: Yaojian Lin
  • Patent number: 10446443
    Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Himani Suhag Kamineni, Vimal Kumar Kamineni, Daniel Smith, Maxwell Lippitt
  • Patent number: 10433435
    Abstract: A semiconductor device may include the following elements: a first substrate; a second substrate; a dielectric layer, which may be positioned between the first substrate and the second substrate and may have a hole; a first conductive member, which may be positioned in the dielectric layer; a second conductive member, which may be positioned in the dielectric layer, may be spaced from the first conductive member, and may be positioned closer to the second substrate than the first conductive member; and a third conductive member, which may contact both the first conductive member and the second conductive member through the hole.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: October 1, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION
    Inventors: Herb He Huang, Clifford Ian Drowley, Hai Ting Li
  • Patent number: 10431546
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 1, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hideomi Kumano
  • Patent number: 10388860
    Abstract: A method for manufacturing magnetic random access memory. The method allows very high density magnetic memory elements to be formed on a magnetic memory chip. A magnetic memory element material is deposited and a diamond like carbon (DLC) hard mask is formed over the magnetic memory element material. An ion or atom bombardment process such as ion milling is performed to remove portions of the magnetic memory element material that are not protected by the hard mask to form a plurality of magnetic memory element pillars. Because the diamond like carbon hard mask is resistant to the material removal processes such as ion milling, it can be made very thin (10-20 nm), which reduces shadowing while still allowing a process such as ion milling to be used to define the magnetic data element pillars. This advantageously allows the pillars to be formed with well defined, vertical sidewalls, and avoiding shorting.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 20, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Girish Jagtiani, Yuan-Tung Chin, Thomas D. Boone, Mustafa Pinarbasi
  • Patent number: 10381362
    Abstract: A three-dimensional memory device includes field effect transistors located on a substrate, lower metal interconnect structures embedded in first dielectric layers and located over the substrate, a source line located over the first dielectric layers, a stepped dielectric material portion located over the first dielectric layers and including stepped surfaces, an alternating stack of insulating layers and electrically conductive layers located over the source line and contacting the stepped surfaces of the stepped dielectric material portion, and memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel. A lateral extent of the stepped dielectric material portion decreases stepwise with a vertical distance from the substrate, and lateral extents of the electrically conductive layers increase with a vertical distance from the source line.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Keisuke Izumi, Tomohiro Kubo
  • Patent number: 10354114
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Patent number: 10347583
    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Guillaume Bouche
  • Patent number: 10319626
    Abstract: Methods of fabricating an interconnect structure. A first sacrificial layer is deposited over a dielectric layer, and a block mask is formed that covers an area on the first sacrificial layer. A second sacrificial layer is deposited over the block mask and the first sacrificial layer. After the block mask is formed, the second sacrificial layer is patterned to form a mandrel that is arranged in part on a portion of the block mask.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Minghao Tang, Rui Chen, Yuping Ren
  • Patent number: 10312270
    Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 4, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhilian Xiao, Haisheng Zhao, Hongxi Xiao, Xiaoguang Pei, Chong Liu
  • Patent number: 10290535
    Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Te Ho, Shih-Yu Chang, Da-Wei Lin, Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 10269716
    Abstract: Techniques and mechanisms for interconnecting circuitry disposed on a transparent substrate. In an embodiment, a multilayer circuit is bonded to the transparent substrate, the multilayer circuit including conductive traces that are variously offset at different respective levels from a side of the transparent substrate. Circuit components, such as packaged or unpackaged integrated circuit devices, are coupled each to respective input and/or output (IO) contacts of the multilayer circuit, where the conductive traces and the IO contacts interconnect the circuit components with each other. In another embodiment, the multilayer circuit is a flexible circuit that is bent to interconnect circuit components which are disposed on opposite respective sides of the transparent substrate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vijay Kasturi, Ana M. Yepes, Chung-Hao Chen, Bradley A. Jackson
  • Patent number: 10269630
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Patent number: 10229885
    Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Steffen Jordan
  • Patent number: 10217748
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Kazuaki Takesako
  • Patent number: 10141319
    Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Wei Yeh, Tsung-Hsun Wu, Chih-Ming Su, Zhi-Xian Chou
  • Patent number: 10134754
    Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 20, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Min-Feng Hung, Jia-Rong Chiou
  • Patent number: 10121697
    Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Joe Lindgren
  • Patent number: 10115701
    Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 30, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xing Zhao, Duk Ju Na, Siew Joo Tan, Pandi C. Marimuthu
  • Patent number: 10115758
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Patent number: 10115630
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 10109486
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10090352
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 2, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 10062701
    Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10032643
    Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
  • Patent number: 10014397
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, David L. Harame, Renata Camillo-Castillo
  • Patent number: 10002790
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a hard mask layer over the material layer. The hard mask layer contains metal. The method also includes forming an opening in the hard mask layer using a plasma etching process, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The method further includes etching the material layer through the opening in the hard mask layer to form a feature opening in the material layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yungtzu Chen, Yu-Shu Chen, Yu-Cheng Liu
  • Patent number: 9997457
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 9994737
    Abstract: Provided are slurry compounds for polishing an SOH organic layer and methods of fabricating a semiconductor device using the same. The slurry compound may include a polishing particle, an oxidizing agent including at least one selected from the group consisting of a nitrate, a sulfate, a chlorate, a perchlorate, a chlorine, and a peroxide, and a polishing accelerator.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyun Kim, Yun-Jeong Kim, SeungHo Park
  • Patent number: 9985047
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a multi-layered stack; forming a vertical hole in the stack; forming a plurality of material layers over a bottom and a sidewall of the vertical hole, wherein the plurality of material layers includes a first material layer and a second material layer, wherein the second material layer is provided under the first material layer; patterning the first material layer located over the bottom of the vertical hole to form a first opening, wherein the first opening exposes the second material layer; and patterning the second material layer exposed by the first opening using a difference in an etch rate between the first material layer and the second material layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 29, 2018
    Assignee: SK Hynix Inc.
    Inventor: Seung Cheol Lee
  • Patent number: 9978594
    Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Lin, Ching-Yu Chang, Kuei-Shun Chen, Chin-Hsiang Lin
  • Patent number: 9950920
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Patent number: 9953915
    Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang