With Formation Of Opening (i.e., Viahole) In Insulative Layer Patents (Class 438/637)
  • Patent number: 10388860
    Abstract: A method for manufacturing magnetic random access memory. The method allows very high density magnetic memory elements to be formed on a magnetic memory chip. A magnetic memory element material is deposited and a diamond like carbon (DLC) hard mask is formed over the magnetic memory element material. An ion or atom bombardment process such as ion milling is performed to remove portions of the magnetic memory element material that are not protected by the hard mask to form a plurality of magnetic memory element pillars. Because the diamond like carbon hard mask is resistant to the material removal processes such as ion milling, it can be made very thin (10-20 nm), which reduces shadowing while still allowing a process such as ion milling to be used to define the magnetic data element pillars. This advantageously allows the pillars to be formed with well defined, vertical sidewalls, and avoiding shorting.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: August 20, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Elizabeth A. Dobisz, Girish Jagtiani, Yuan-Tung Chin, Thomas D. Boone, Mustafa Pinarbasi
  • Patent number: 10381362
    Abstract: A three-dimensional memory device includes field effect transistors located on a substrate, lower metal interconnect structures embedded in first dielectric layers and located over the substrate, a source line located over the first dielectric layers, a stepped dielectric material portion located over the first dielectric layers and including stepped surfaces, an alternating stack of insulating layers and electrically conductive layers located over the source line and contacting the stepped surfaces of the stepped dielectric material portion, and memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel. A lateral extent of the stepped dielectric material portion decreases stepwise with a vertical distance from the substrate, and lateral extents of the electrically conductive layers increase with a vertical distance from the source line.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: August 13, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Keisuke Izumi, Tomohiro Kubo
  • Patent number: 10354114
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Patent number: 10347583
    Abstract: Structures including metallization layers and metal lines, and methods of forming thereof. A patterning stack, a masking layer, and a spacer patterning layer are formed over a dielectric layer, and an opening is formed in the spacer patterning layer. First and second spacers are formed on a portion of the masking layer at sidewalls of an opening in the spacer patterning layer. The first spacer and the second spacer overlie and traverse first portions of the dummy line. After removing the spacer patterning layer and masking layer, second portions of the dummy line are removed to form a feature in the patterning stack that includes a first gap beneath the first spacer and a second gap beneath the second spacer. A metal line is formed in the dielectric layer using the feature, and includes cuts at the first gap and the second gap in the feature.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Guillaume Bouche
  • Patent number: 10319626
    Abstract: Methods of fabricating an interconnect structure. A first sacrificial layer is deposited over a dielectric layer, and a block mask is formed that covers an area on the first sacrificial layer. A second sacrificial layer is deposited over the block mask and the first sacrificial layer. After the block mask is formed, the second sacrificial layer is patterned to form a mandrel that is arranged in part on a portion of the block mask.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: June 11, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Minghao Tang, Rui Chen, Yuping Ren
  • Patent number: 10312270
    Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: June 4, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhilian Xiao, Haisheng Zhao, Hongxi Xiao, Xiaoguang Pei, Chong Liu
  • Patent number: 10290535
    Abstract: Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Te Ho, Shih-Yu Chang, Da-Wei Lin, Chien-Chih Chiu, Ming-Chung Liang
  • Patent number: 10269630
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Hung Lin, You-Hua Chou, Sheng-Hsuan Lin, Chih-Wei Chang
  • Patent number: 10269716
    Abstract: Techniques and mechanisms for interconnecting circuitry disposed on a transparent substrate. In an embodiment, a multilayer circuit is bonded to the transparent substrate, the multilayer circuit including conductive traces that are variously offset at different respective levels from a side of the transparent substrate. Circuit components, such as packaged or unpackaged integrated circuit devices, are coupled each to respective input and/or output (IO) contacts of the multilayer circuit, where the conductive traces and the IO contacts interconnect the circuit components with each other. In another embodiment, the multilayer circuit is a flexible circuit that is bent to interconnect circuit components which are disposed on opposite respective sides of the transparent substrate.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: April 23, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vijay Kasturi, Ana M. Yepes, Chung-Hao Chen, Bradley A. Jackson
  • Patent number: 10229885
    Abstract: The method comprises providing a plurality of electronic devices, embedding the electronic devices in an encapsulation layer, forming vias into the encapsulation layer, the vias extending from a main face of the encapsulation layer to the electronic devices, and depositing a metallic layer onto the encapsulation layer including the vias by galvanic plating, the method further comprising providing a current distribution layer for effecting a distributed growth of the metallic material during the galvanic plating.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: March 12, 2019
    Assignee: Infineon Technologies AG
    Inventors: Martin Gruber, Steffen Jordan
  • Patent number: 10217748
    Abstract: A dynamic random access memory (DRAM) includes a substrate, a bit line, a capacitor contact, a dielectric structure, a capacitor, and a landing pad. The bit line is located on the substrate. The capacitor contact is aside the bit line. The capacitor contact protrudes from a space between adjacent bit lines, such that upper sidewalls of the capacitor contact are exposed by the bit line. The dielectric structure is located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contacts. The capacitor is located above the capacitor contact. The landing pad is located between the capacitor contact and the capacitor. The landing pad at least covers one portion of the upper surface of the capacitor contact. A contact area between landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 26, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Kazuaki Takesako
  • Patent number: 10141319
    Abstract: A layout pattern of a static random access memory includes a pull-up device, a first pull-down device, a second pull-up device, a second pull-down device, a first pass gate device, a second pass gate device, a third pass gate device and a fourth pass gate device disposed on a substrate. A plurality of fin structures is disposed on the substrate, the fin structures including at least one first fin structure and at least one second fin structure. A step-shaped structure is disposed on the substrate, including a first part, a second part and a bridge part. A first extending contact feature crosses over the at least one first fin structure and the at least one second fin structure.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Wei Yeh, Tsung-Hsun Wu, Chih-Ming Su, Zhi-Xian Chou
  • Patent number: 10134754
    Abstract: A method for forming a semiconductor structure includes the following steps. First, a preliminary structure is provided. The preliminary structure has an array region. The preliminary structure includes a plurality of first stacks in the array region. Then, a first dielectric layer is formed on the first stacks. A first hard mask layer is formed on the first dielectric layer. An insulating material is formed on the first hard mask layer. Then, a planarization process stopped on the first hard mask layer is conducted. Thereafter, the first hard mask layer is removed. A second hard mask layer is formed on the first dielectric layer. A second dielectric layer is formed on the second hard mask layer. A plurality of contacts are formed through the second dielectric layer, the second hard mask layer and the first dielectric layer to the preliminary structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 20, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Min-Feng Hung, Jia-Rong Chiou
  • Patent number: 10121697
    Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Joe Lindgren
  • Patent number: 10115758
    Abstract: A semiconductor device and a method for fabricating the same are provided. In the method for fabricating the semiconductor device, at first, a semiconductor substrate is provided. Then, a trench is formed in the semiconductor substrate. Thereafter, a dielectric layer is formed to cover the semiconductor substrate, in which the dielectric layer has a trench portion located in the trench of the semiconductor substrate. Then, a reflective material layer is formed on the trench portion of the dielectric layer. Thereafter, the reflective material layer is etched to form an isolation structure, in which the isolation structure includes a top portion located on the semiconductor substrate and a bottom portion located in a trench formed by the trench portion of the dielectric layer.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 30, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Yi Chen, Chih-Fei Lee, Fu-Cheng Chang, Ching-Hung Kao, Chia-Pin Cheng
  • Patent number: 10115630
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower etch stop layer (ESL); a middle low-k (LK) dielectric layer over the lower ESL; a supporting layer over the middle LK dielectric layer; an upper LK dielectric layer over the supporting layer; an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature is through the supporting layer; a gap along an interface of the upper conductive feature and the upper LK dielectric layer; and an upper ESL over the upper LK dielectric layer, the upper conductive feature, and the gap.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shiou Chen, Chih-Yuan Ting
  • Patent number: 10115701
    Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: October 30, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Xing Zhao, Duk Ju Na, Siew Joo Tan, Pandi C. Marimuthu
  • Patent number: 10109486
    Abstract: The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10090352
    Abstract: A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 2, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideomi Kumano
  • Patent number: 10062701
    Abstract: The present invention provides a SRAM unit cell which includes a semiconductor substrate, six transistors, a first well, two first doped regions and two second doped regions. The transistors are disposed on the semiconductor substrate, and include a first gate line and a second gate line. The first well is disposed in the semiconductor substrate, and the first well has a first conductive type, wherein the first gate line and the second gate line extend onto the first well. The first doped regions are disposed in the first well at two sides of the first gate line, and the second doped regions are disposed in the first well at two sides of the second gate line.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10032643
    Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
  • Patent number: 10014397
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: July 3, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, David L. Harame, Renata Camillo-Castillo
  • Patent number: 10002790
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a material layer over a semiconductor substrate and forming a hard mask layer over the material layer. The hard mask layer contains metal. The method also includes forming an opening in the hard mask layer using a plasma etching process, and a gas mixture used in the plasma etching process includes a nitrogen-containing gas, a halogen-containing gas, and a carbon-containing gas. The method further includes etching the material layer through the opening in the hard mask layer to form a feature opening in the material layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yungtzu Chen, Yu-Shu Chen, Yu-Cheng Liu
  • Patent number: 9997457
    Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Christopher J. Jezewski, Tejaswi K. Indukuri, Ramanan V. Chebiam, Colin T. Carver
  • Patent number: 9994737
    Abstract: Provided are slurry compounds for polishing an SOH organic layer and methods of fabricating a semiconductor device using the same. The slurry compound may include a polishing particle, an oxidizing agent including at least one selected from the group consisting of a nitrate, a sulfate, a chlorate, a perchlorate, a chlorine, and a peroxide, and a polishing accelerator.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangkyun Kim, Yun-Jeong Kim, SeungHo Park
  • Patent number: 9985047
    Abstract: Disclosed is a method of manufacturing a semiconductor device, including: forming a multi-layered stack; forming a vertical hole in the stack; forming a plurality of material layers over a bottom and a sidewall of the vertical hole, wherein the plurality of material layers includes a first material layer and a second material layer, wherein the second material layer is provided under the first material layer; patterning the first material layer located over the bottom of the vertical hole to form a first opening, wherein the first opening exposes the second material layer; and patterning the second material layer exposed by the first opening using a difference in an etch rate between the first material layer and the second material layer.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 29, 2018
    Assignee: SK Hynix Inc.
    Inventor: Seung Cheol Lee
  • Patent number: 9978594
    Abstract: Formation methods of a semiconductor device structure are provided. The method includes forming an under layer over a substrate, forming a middle layer over the under layer, and forming a patterned upper layer over the middle layer. The patterned upper layer has a first opening exposing a portion of the middle layer. The method also includes etching the portion of the middle layer exposed by the first opening to form a second opening exposing a portion of the under layer, and etching the portion of the under layer exposed by the second opening of the middle layer. The method further includes forming pores in the middle layer before or during the etching of the portion of the under layer.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Yen Lin, Ching-Yu Chang, Kuei-Shun Chen, Chin-Hsiang Lin
  • Patent number: 9953915
    Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang
  • Patent number: 9950920
    Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: April 24, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yuan-Sheng Lin, Weng-Yi Chen, Kuan-Yu Wang, Chih-Wei Liu
  • Patent number: 9922884
    Abstract: A first aspect of the invention provides for a method including: forming an interfacial layer in a first opening in a pFET region and a second opening in an nFET region, each opening being in a dielectric layer in the pFET region and the nFET region; forming a high-k layer over the interfacial layer in each of the first and second openings; forming a wetting layer over the high-k layer in each of the first and second openings; forming a first metal layer in each of the first and second openings, the first metal layer including tungsten; and forming a first gate electrode layer over the first metal layer to substantially fill each of the first and second openings, thereby forming a first replacement gate stack over the pFET region and a second replacement gate stack over the nFET region.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan
  • Patent number: 9911822
    Abstract: A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 6, 2018
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Damian Sojka
  • Patent number: 9894770
    Abstract: Disclosed is an embedded electronic component which can improve reliability of connection with external wiring and efficiency of an embedding process by including: a contact pad provided on at least one surface of a body portion and made of a conductive material; a first insulating layer for covering the at least one surface of the body portion; a first pad in contact with a surface of the contact pad and made of a conductive material; a rearrangement portion provided on a surface of the first insulating layer to be in contact with the first pad; a second pad provided on the surface of the first insulating layer to be in contact with the rearrangement portion; and a second insulating layer having an opening to expose a portion of the second pad while covering the first insulating layer, the first pad, the rearrangement portion, and the second pad.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: February 13, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Doo Hwan Lee
  • Patent number: 9887161
    Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 6, 2018
    Assignee: INTEL CORPORATION
    Inventors: Christopher J. Jezewski, David J. Michalak, Kanwal Jit Singh, Alan M. Myers
  • Patent number: 9880686
    Abstract: A touch screen panel includes first electrode patterns disposed in a first direction, first connection patterns electrically connecting the first electrode patterns, second electrode patterns disposed in a second direction intersecting the first direction and insulated from the first electrode patterns, insulating patterns disposed on the first connection patterns, and second connection patterns disposed on the insulating patterns and electrically connecting the second electrode patterns, in which at least one of the first electrode patterns, the first connection patterns, the second electrode patterns, and the second connection patterns include a first polymer layer including a conductive material infiltrated therein, and the insulating patterns comprise a second polymer layer comprising a dielectric material infiltrated therein.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: January 30, 2018
    Assignees: Samsung Display Co., Ltd., IUCF-HYU
    Inventors: Seung Hun Kim, Cheol Jang, Sang Hwan Cho, Chung Sock Choi, Myung Mo Sung
  • Patent number: 9818845
    Abstract: A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Kin-On Sin, Chun-Wai Ng, Hitoshi Sumida, Yoshiaki Toyada, Akihiko Ohi, Hiroyuki Tanaka, Takeyoshi Nishimura
  • Patent number: 9754885
    Abstract: A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top potion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9754883
    Abstract: A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top portion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9748105
    Abstract: Implementations described herein generally relate to methods for forming tungsten materials on substrates using vapor deposition processes. The method comprises positioning a substrate having a feature formed therein in a substrate processing chamber, depositing a first film of a bulk tungsten layer by introducing a continuous flow of a hydrogen containing gas and a tungsten halide compound to the processing chamber to deposit the first tungsten film over the feature, etching the first film of the bulk tungsten layer using a plasma treatment to remove a portion of the first film by exposing the first film to a continuous flow of the tungsten halide compound and an activated treatment gas and depositing a second film of the bulk tungsten layer by introducing a continuous flow of the hydrogen containing gas and the tungsten halide compound to the processing chamber to deposit the second tungsten film over the first tungsten film.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 29, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kai Wu, Sang Ho Yu
  • Patent number: 9721873
    Abstract: A semiconductor device with a through via penetrating a semiconductor substrate, in which shorting between a wiring and a semiconductor element is prevented to improve the reliability of the semiconductor device. A liner insulating film as a low-k film, which has a function to insulate the semiconductor substrate and a through-silicon via from each other and is thick enough to reduce capacitance between the semiconductor substrate and the through-silicon via, is used as an interlayer insulating film for a first wiring layer over a contact layer. This prevents a decrease in the thickness of an interlayer insulating film in the contact layer.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Masazumi Matsuura
  • Patent number: 9698048
    Abstract: A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yung-Sung Yen
  • Patent number: 9691643
    Abstract: An etching apparatus includes a controller configured to control a high frequency power supply to supply a high frequency power to a mounting table for etching a polymer layer formed on a base layer placed on the mounting table, using plasma generated from a predetermined gas supplied from a gas supply source by the high frequency power, the polymer layer having a periodic pattern of a first polymer and a second polymer formed by self-assembling the first polymer and the second polymer of a block copolymer that is capable of being self-assembled, the high frequency power being set for etching the polymer layer using the generated plasma such that the second polymer is removed and a pattern of the first polymer is formed for subsequently etching the base layer using the pattern of the first polymer as a mask.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: June 27, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Eiichi Nishimura, Tadashi Kotsugi, Fumiko Yamashita
  • Patent number: 9679807
    Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Mark V. Raymond, Praneet Adusumilli, Chengyu Niu
  • Patent number: 9647169
    Abstract: Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: May 9, 2017
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Keith Kwong Hon Wong, Jun Yuan
  • Patent number: 9640431
    Abstract: Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: May 2, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee
  • Patent number: 9637823
    Abstract: Plasma atomic layer deposition (ALD) is optimized through modulation of the gas residence time during an excited species phase, wherein activated reactant is supplied such as from a plasma. Reduced residence time increases the quality of the deposited layer, such as reducing wet etch rates, increasing index of refraction and/or reducing impurities in the layer. For example, dielectric layers, particularly silicon nitride films, formed from such optimized plasma ALD processes have low levels of impurities remaining from the silicon precursor.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 2, 2017
    Assignee: ASM IP HOLDING B.V.
    Inventors: Harm C. M. Knoops, Koen de Peuter, Wilhelmus M. M. Kessels
  • Patent number: 9607889
    Abstract: Method and apparatus for direct writing of passive structures having a tolerance of 5% or less in one or more physical, electrical, chemical, or optical properties. The present apparatus is capable of extended deposition times. The apparatus may be configured for unassisted operation and uses sensors and feedback loops to detect physical characteristics of the system to identify and maintain optimum process parameters.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 28, 2017
    Assignee: Optomec, Inc.
    Inventors: Michael J. Renn, Bruce H. King
  • Patent number: 9589884
    Abstract: An integrated circuit device may include the following elements: a first semiconductor substrate; a first transistor set positioned in the first semiconductor substrate; a first dielectric layer covering a gate electrode of the first transistor set; a first interconnect member positioned in the first dielectric layer and electrically connected to the first transistor set; a second semiconductor substrate; a second transistor set positioned in the second semiconductor substrate and structurally different from the first transistor set; a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second semiconductor substrate, and covering a gate electrode of the second transistor set; and a second interconnect member positioned in the second dielectric layer, electrically connected to a terminal of the second transistor set, and electrically connected to the first interconnect member.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 7, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Herb He Huang, Clifford Ian Drowley
  • Patent number: 9583579
    Abstract: A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer P. Pendharkar, Jarvis Benjamin Jacobs
  • Patent number: 9570397
    Abstract: A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 14, 2017
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Su Chen Fan, Vimal Kamineni, Andre P. Labonte, Ruilong Xie
  • Patent number: 9564354
    Abstract: The present invention discloses a via-hole etching method related to semiconductor manufacturing field, and the method overcomes the defects of an uncontrollable end point of a via-hole and an unfavorable profile-angle in a conventional via-hole etching method. The via-hole etching method includes: forming a structure for via-hole etching, includes: a low-temperature poly-silicon layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer, which are sequentially formed on a substrate; forming a mask layer comprising a via-hole masking pattern on the structure for via-hole etching; by using a first etching process, etching the structure for via-hole etching to a first thickness of the gate insulating layer; by using a second etching process, etching the structure for via-hole etching to etch away the remaining thickness of the gate insulating layer, and uncovering the low-temperature poly-silicon layer; removing the mask layer to form a via-hole structure.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: February 7, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Byung Chun Lee, Donghua Jiang, Yongyi Fu, Wuyang Zhao, Chundong Li