With Formation Of Opening (i.e., Viahole) In Insulative Layer Patents (Class 438/637)
  • Patent number: 11502033
    Abstract: Disclosed is a semiconductor device comprising a substrate, a first dielectric layer and a second dielectric layer that are sequentially stacked on the substrate, a contact that penetrates the first dielectric layer and extends toward the substrate, and a conductive line that is provided in the second dielectric layer and electrically connected to the contact, The conductive line extends in a first direction. The contact comprises a lower segment in the first dielectric layer and an upper segment in the second dielectric layer. A width in a second direction of the conductive line decreases with decreasing distance from the substrate. The second direction intersects the first direction. A sidewall of the upper segment of the contact is in contact with the conductive line.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kiho Yang
  • Patent number: 11437299
    Abstract: A semiconductor apparatus comprising a first substrate that has a first surface and a second surface and is provided with a through hole extending through from the first surface to the second surface and an insulating layer and a conductive member that are provided in the through hole is provided. The through hole includes a first opening formed in the first substrate and a second opening provided between the first opening and the second surface. The first opening and the second opening each have a tapered shape whose opening width decreases from the first surface to the second surface, and a first taper angle formed by a side surface of the first opening and a plane parallel to the second surface is smaller than a second taper angle formed by a side surface of the second opening and a plane parallel to the second surface.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: September 6, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Tatsuya Saito
  • Patent number: 11398428
    Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 26, 2022
    Assignee: Intel Corporation
    Inventors: Eungnak Han, Tayseer Mahdi, Rami Hourani, Gurpreet Singh, Florian Gstrein
  • Patent number: 11393715
    Abstract: Provided is a method for manufacturing a 14 nm-node BEOL 32 nm-width metal. A semiconductor structure for manufacturing BEOL wire is provided, wherein the semiconductor structure at least comprises a carbon coating and intermediate layer on it; forming a photoresist layer on the intermediate layer and exposing the photoresist layer according to a layout; developing the exposed photoresist layer by using a developing solution, and causing the developed photoresist to react with the intermediate layer in a contact region of the developed photoresist to form a peg groove; and etching by using the groove in the semiconductor structure to form a 14 nm-node BEOL 32 nm-width metal. This application can reducing the longitudinal shrink of the metal wire, achieving the improvement of the lateral and longitudinal shrink uniformity, reducing defects caused by misalignment of the through hole and the metal wire, and increasing the effective usable area of a chip.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: July 19, 2022
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventors: Yongji Mao, Ronghong Ye, Liyao Liu, Yu Zhang, Zhanyuan Hu
  • Patent number: 11394104
    Abstract: The present disclosure relates to a printed circuit board. The printed circuit board includes: a first substrate portion having a rigid region and a flexible region; and a second substrate portion disposed on the first substrate portion. The first substrate portion and the second substrate portion are disposed to be shifted such that portions of each of the first substrate portion and the second substrate portion overlap each other.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Tae Hong Min
  • Patent number: 11387168
    Abstract: A semiconductor device includes a first conductive layer, an organic layer and a silicon layer. The first conductive layer includes a first surface. The organic layer is disposed over the first surface of the first conductive layer. The silicon layer is disposed over the organic layer and extended onto and in contact with the first surface of the first conductive layer.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
  • Patent number: 11367590
    Abstract: A plasma processing method includes: placing a substrate on a substrate support provided in a chamber of a capacitively coupled plasma processing apparatus where the substrate includes a silicon-containing film and a mask provided on the silicon-containing film and having an opening having a longitudinal direction; and supplying an inert gas into the chamber; and selectively performing one of supplying a first radio-frequency power to an upper electrode of the plasma processing apparatus to generate plasma from the inert gas and supplying a second radio-frequency power to a lower electrode of the plasma processing apparatus included in the substrate support, and applying a negative bias voltage to the upper electrode to cause positive ions from the plasma to collide with the upper electrode and release a silicon-containing material from the upper electrode, thereby depositing the silicon-containing material on the substrate.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: June 21, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kosuke Ogasawara, Kentaro Yamaguchi, Takanori Banse
  • Patent number: 11345591
    Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 31, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Chun Yeh, Lien-Yao Tsai, Shao-Chi Yu
  • Patent number: 11309217
    Abstract: A method of making a semiconductor device that includes forming a dielectric stack over a substrate and patterning a contact region in the dielectric stack, the contact region having side portions and a bottom portion that exposes the substrate. The method also includes forming a dielectric barrier layer in the contact region to cover the side portions and forming a conductive blocking layer to cover the dielectric barrier layer, the dielectric stack, and the bottom portion of the contact region. The method can include forming a conductive layer over the conductive blocking layer and forming a conductive barrier layer over the conductive layer. The method can further include forming a silicide region in the substrate beneath the conductive layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ya-Huei Li, Li-Wei Chu, Yu-Hsiang Liao, Hung-Yi Huang, Chih-Wei Chang, Ching-Hwanq Su
  • Patent number: 11289427
    Abstract: A faceted integrated-circuit die includes a concave facet with an increased interconnect breakout area available to an adjacent device such as a rectangular IC die that is nested within the form factor of the concave facet. The concave facet form factor includes a ledge facet and a main-die facet. Multiple nested faceted IC dice are disclosed for increasing interconnect breakout areas and package miniaturization. A faceted silicon interposer has a concave facet that also provides an increased interconnect breakout area and package miniaturization.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Jenny Shio Yin Ong, Seok Ling Lim
  • Patent number: 11276636
    Abstract: Chamfer-less via interconnects and techniques for fabrication thereof with a protective dielectric arch are provided. In one aspect, a method of forming an interconnect includes: forming metal lines in a first dielectric; depositing an etch stop liner onto the first dielectric; depositing a second dielectric on the etch stop liner; patterning vias and a trench in the second dielectric, wherein the vias are present over at least one of the metal lines, and wherein the patterning forms patterned portions of the second dielectric/etch stop liner over at least another one of the metal lines; forming a protective dielectric arch over the at least another one of the metal lines; and filling the vias/trench with a metal(s) to form the interconnect which, due to the protective dielectric arch, is in a non-contact position with the at least another one of the metal lines. An interconnect structure is also provided.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Koichi Motoyama, Gangadhara Raja Muthinti, Cornelius Brown Peethala, Benjamin D. Briggs, Michael Rizzolo
  • Patent number: 11264344
    Abstract: A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: March 1, 2022
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: John Moore, Joseph F. Brooks
  • Patent number: 11264326
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes an active region including a channel region and a source/drain region and extending along a first direction, and a source/drain contact structure over the source/drain region. The source/drain contact structure includes a base portion extending lengthwise along a second direction perpendicular to the first direction, and a via portion over the base portion. The via portion tapers away from the base portion.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Kuan-Lun Cheng, Chih-Hao Wang, Cheng-Chi Chuang, Chia-Hao Chang
  • Patent number: 11257923
    Abstract: A method includes removing a dummy gate structure to form a gate trench over a semiconductor layer, forming a high-k gate dielectric layer over an interfacial layer exposed in the gate trench, depositing a metal-containing precursor over the high-k gate dielectric layer to form a metal-containing layer, and subsequently depositing an aluminum-containing precursor over the metal-containing layer, where depositing the aluminum-containing precursor forms an aluminum oxide layer at an interface between the high-k gate dielectric layer and the interfacial layer and where the metal-containing precursor includes a metal different from aluminum. The method further includes, subsequent to depositing the aluminum-containing precursor, removing a portion of the metal-containing layer, depositing a work-function metal layer over a remaining portion of the metal-containing layer, and forming a bulk conductive layer over the work-function metal layer, resulting in a metal gate structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh Wen Tsau, Ziwei Fang, Huang-Lin Chao, Kuo-Liang Sung
  • Patent number: 11251118
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 11232951
    Abstract: In an embodiment is provided a method of forming a blind via in a substrate comprising a mask layer, a conductive layer, and a dielectric layer that includes conveying the substrate to a scanning chamber; determining one or more properties of the blind via, the one or more properties comprising a top diameter, a bottom diameter, a volume, or a taper angle of about 80° or more; focusing a laser beam at the substrate to remove at least a portion of the mask layer; adjusting the laser process parameters based on the one or more properties; and focusing the laser beam, under the adjusted laser process parameters, to remove at least a portion of the dielectric layer within the volume to form the blind via. In some embodiments, the mask layer can be pre-etched. In another embodiment is provided an apparatus for forming a blind via in a substrate.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: January 25, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei-Sheng Lei, Kurtis Leschkies, Roman Gouk, Steven Verhaverbeke, Visweswaren Sivaramakrishnan
  • Patent number: 11217476
    Abstract: A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate and a via hole in the dielectric layer. The via hole has an oval cross section. The semiconductor device structure further includes a trench in the dielectric layer, and the via hole extends from a bottom portion of the trench. The trench has a trench width wider than a hole width of the via hole. In addition, the semiconductor device structure includes one or more conductive materials filling the via hole and the trench and electrically connected to the conductive feature.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen Peng, Jyu-Horng Shieh
  • Patent number: 11217534
    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: January 4, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Ji Yong Park, Kyu Oh Lee
  • Patent number: 11211470
    Abstract: An improved dummy gate and a method of forming the same are disclosed. In an embodiment, the method includes depositing a first material in a trench, the trench being disposed between a first fin and a second fin; etching the first material to expose an upper portion of sidewalls of the trench; and depositing a second material on the first material without the second material being deposited on the exposed upper portion of the sidewalls of the trench.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Ku Chen, Chii-Horng Li, Cheng-Po Chau, Pei-Ren Jeng, Yee-Chia Yeo, Chia-Ao Chang
  • Patent number: 11205586
    Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: December 21, 2021
    Assignee: Intel Corporation
    Inventors: Kevin Lin, Christopher J. Jezewski
  • Patent number: 11201232
    Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a source/drain structure formed adjacent to the gate structure in the substrate and a contact formed over the source/drain structure. The semiconductor structure further includes a metal-containing layer formed over the contact and a dielectric layer covering the gate structure and the metal-containing layer. The semiconductor structure further includes a first conductive structure formed through dielectric layer and the metal-containing layer and landing on the contact. In addition, a bottom surface of the metal-containing layer is higher than a top surface of the gate structure.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mrunal A. Khaderbad, Sung-Li Wang, Yasutoshi Okuno
  • Patent number: 11145585
    Abstract: A wiring board includes a semiconductor chip mounting surface, an external connection surface provided on an opposite side from the semiconductor chip mounting surface, and pads provided on the semiconductor chip mounting surface. Each pad includes a columnar section, and a tapered section, continuously formed on a first end of the columnar section, and having a cross sectional area that decreases toward a direction away from the columnar section. The tapered section of each pad projects from the semiconductor chip mounting surface.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: October 12, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Daisuke Sakurai
  • Patent number: 11121084
    Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ching-Jung Yang, Jie Chen, Ming-Fa Chen
  • Patent number: 11094580
    Abstract: Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kenneth Chun Kuen Cheng, Koichi Motoyama, Chih-Chao Yang
  • Patent number: 11087994
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 11078337
    Abstract: The present invention is broadly concerned with novel directed self-assembly compositions, processes utilizing those compositions, and the resulting structures that are formed. The composition comprises a block copolymer of polystyrene and a polymethylmethacrylate block with polylactic acid side chains (“PS-b-P(MMA-LA)”). The block copolymer is capable of crosslinking and micro-phase separating into lines and spaces measuring about 10-nm or smaller with sub-20 nm L0 capability. Additionally, PS-b-P(MMA-LA) can be thermally annealed without a top-coat for simpler processing than the prior art. The polylactic acid side chains also increase the etch rate of the poly(methylmethacrylate) block when exposed to oxygen plasma, as well as lower the Tg.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: August 3, 2021
    Assignee: Brewer Science, Inc.
    Inventors: Daniel Sweat, Kui Xu
  • Patent number: 11081387
    Abstract: A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: August 3, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Runzi Chang, Min She
  • Patent number: 11056342
    Abstract: A method of fabricating a semiconductor device includes forming a protective layer on a portion of the semiconductor body that is not to be silicided. The protective layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. At least a portion of the silicon nitride layer of the protective layer is removed. A silicided portion of the semiconductor body is laterally spaced from the protective layer. The siliciding is performed by an ion sputtering in a plasma environment on both the silicided portion of the semiconductor body and the portion of the semiconductor body that is not to be silicided.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 6, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Denis Monnier, Olivier Gonnard
  • Patent number: 11056404
    Abstract: An evaluation system that may include an imager; and a processing circuit. The imager may be configured to obtain an electron image of a hole that is formed by an etch process, the hole exposes at least one layer of a one or more sets of layers, each set of layers comprises layers that differ from each other by their electron yield and belong to an intermediate product. The processing circuit may be configured to evaluate, based on the electron image, whether the hole ended at a target layer of the intermediate product. The intermediate product is manufactured by one or more manufacturing stages of a manufacturing process of a three dimensional NAND memory unit. The hole may exhibit a high aspect ratio, and has a width of a nanometric scale.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: July 6, 2021
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Roman Kris, Grigory Klebanov, Dhananjay Singh Rathore, Einat Frishman, Sharon Duvdevani-Bar, Assaf Shamir, Elad Sommer, Jannelle Anna Geva, Daniel Alan Rogers, Ido Friedler, Avi Aviad Ben Simhon
  • Patent number: 11049788
    Abstract: An integrated circuit chip device configured provide thermal control by directing heat transfer away from a heat sensitive component. The structure directs the heat transfer away from the heat sensitive component so that the heat sensitive component can be maintained at reduced operating temperatures for improved performance.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Maria Esther Pace
  • Patent number: 11031246
    Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Yongan Xu, Oleg Gluschenkov
  • Patent number: 10867922
    Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10840134
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-yi Ruan
  • Patent number: 10829366
    Abstract: Disclosed is a method of forming an interconnect in a substrate having a first surface and a second surface. The method includes forming an insulating structure abutting the first surface and defining a closed loop around a via in the substrate and forming an insulating region abutting the second surface such that the insulating region contacts the insulating structure and separates the via from a bulk region of the substrate. Forming the insulating structure includes etching the substrate beginning from the first surface to form a trench, filling the trench to form a seam portion, and converting a first portion of the substrate to a first solid portion to form the closed loop.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: November 10, 2020
    Assignee: Kionix, Inc.
    Inventors: Scott G. Adams, Charles W. Blackmer
  • Patent number: 10825508
    Abstract: A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 3, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Pei-Hsiu Tseng, I-Shuan Wei, Jia-You Lin, Shou-Zen Chang, Chi-Wei Lin, Hung-Hsun Lin
  • Patent number: 10784153
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: September 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 10741435
    Abstract: Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause growth of the film from the at least one feature. Methods of forming self-aligned vias are also described.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: August 11, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Susmit Singha Roy, Yihong Chen, Kelvin Chan, Abhijit Basu Mallick, Srinivas Gandikota, Pramit Manna
  • Patent number: 10734278
    Abstract: A process is provided in which low-k layers are protected from etch damage by the use of a selectively formed protection layer which forms on the low-k layer. In one embodiment, the low-k layers may be low-k dielectric layers utilized in BEOL process steps. In one embodiment, the selectively formed protection layer may be formed by a selective deposition process which selectively forms layers on the low-k dielectric but not over the conductor layer. The selectively formed protection layer may then be utilized to protect the low-k layer from a plasma etch that is utilized to recess the conductor. In this manner, a conductor (for example metal) may be recessed in a low-k dielectric layer via a plasma etch process.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Aizawa, Karthikeyan Pillai, Nicholas Joy, Kandabara Tapily
  • Patent number: 10692812
    Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ravi Prakash Srivastava, Hui Zang, Jiehui Shu
  • Patent number: 10658234
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer to expose a conductive element. The method also includes forming a conductive layer over the conductive element and modifying an upper portion of the conductive layer using a plasma operation to form a modified region. The method further includes forming a conductive plug over the modified region.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min-Hsiu Hung, Sung-Li Wang, Pei-Wen Wu, Yida Li, Chih-Wei Chang, Huang-Yi Huang, Cheng-Tung Lin, Jyh-Cherng Sheu, Yee-Chia Yeo, Chi-On Chui
  • Patent number: 10658180
    Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Yongan Xu, Oleg Gluschenkov
  • Patent number: 10651283
    Abstract: A method includes forming a trench over a substrate, wherein the trench is surrounded by gate spacers and an inter-layer dielectric layer, depositing a dielectric layer on a bottom and along sidewalls of the trench, depositing a metal layer over the dielectric layer, depositing a protection layer over the metal layer, wherein the protection layer has an uneven thickness, applying an etch-back process to the protection layer and the metal layer, wherein as a result of applying the etch-back process, a portion of the metal layer has been removed and at least a portion of the protection layer remains at the bottom of the trench and removing the protection layer from the trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 10644037
    Abstract: The present disclosure relates to a via-hole connection structure and a method of manufacturing the same and an array substrate and a method of manufacturing the same. In an embodiment, a method of manufacturing a via-hole connection structure, includes the following steps of: forming a first conductive layer on a substrate, and patterning the first conductive layer to form a first conductive pattern on which a first photoresist pattern is provided; forming a first insulation layer covering the first conductive layer and the first photoresist pattern; patterning the first insulation layer to form a first via-hole from which at least a portion of the first photoresist pattern is exposed; removing the at least a portion of the first photoresist pattern exposed from the first via-hole; and forming a second conductive pattern, wherein the second conductive pattern is electrically connected to the first conductive pattern through the first via-hole.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELETRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Su, Xiaofei Yang, Xu Liu, Xun Mou, Yawen Zhu
  • Patent number: 10636698
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank W. Mont, Errol Todd Ryan
  • Patent number: 10600678
    Abstract: Self-aligned isotropic etch processes for via and plug patterning for back end of line (BEOL) interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes removing a sacrificial or permanent placeholder material of a subset of a plurality of holes or trenches through openings in a patterning layer. The method also includes removing the patterning layer and filling the subset of the plurality of holes or trenches with a permanent material.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Elliot N. Tan, Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10580692
    Abstract: A system and method of fabricating a semiconductor device include forming a series of gates, and forming a gate spacer on each side of each gate of the series of gates. The method includes forming a source region on a side of each of the gates and forming a drain region on an opposite side of each of the gates. The source region or the drain region between two adjacent ones of the gates is shared and only the source region or the drain region on one side of a first gate and the source region or the drain region on one side of a last gate in the series of gates are unshared source or drain regions. A self-aligned contact (SAC) is formed on the unshared source or drain regions. An air spacer is formed between the SACs and the first gate and the last gate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: March 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Ruilong Xie, Julien Frougier, Kangguo Cheng
  • Patent number: 10558121
    Abstract: In a method for producing a wired circuit board includes a step (1), in which the insulating layer having an inclination face is provided; a step (2), in which a metal thin film is provided on the surface of the insulating layer including the inclination face; a step (3), in which a photoresist is provided on the surface of the metal thin film; a step (4), in which a photomask is disposed so that a first light exposure portion and a second light exposure portion in the photoresist are exposed to light, and the photoresist is exposed to light; a step (5), in which the first light exposure portion and the second light exposure portion are removed; and a step (6), in which the first wire and the second wire are provided on the surface of the metal thin film.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 11, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 10553534
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a first dielectric layer on a substrate, in which a first conductor is embedded within the first dielectric layer. Next, a second dielectric layer is formed on the first dielectric layer, part of the second dielectric layer is removed to form a contact hole, and a lateral etching process is conducted to expand the contact hole to form a funnel-shaped opening. Next, a metal layer is formed in the funnel-shaped opening, and the metal layer is planarized to form a second conductor.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: February 4, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Te Wei, Chun-Hsien Lin
  • Patent number: 10520817
    Abstract: In a method for producing a wired circuit board includes a step (1), in which the insulating layer having an inclination face is provided; a step (2), in which a metal thin film is provided on the surface of the insulating layer including the inclination face; a step (3), in which a photoresist is provided on the surface of the metal thin film; a step (4), in which a photomask is disposed so that a first light exposure portion and a second light exposure portion in the photoresist are exposed to light, and the photoresist is exposed to light; a step (5), in which the first light exposure portion and the second light exposure portion are removed; and a step (6), in which the first wire and the second wire are provided on the surface of the metal thin film.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: NITTO DENKO CORPORATION
    Inventors: Yuu Sugimoto, Hiroyuki Tanabe, Yoshito Fujimura
  • Patent number: 10522394
    Abstract: A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 31, 2019
    Assignee: Marvell World Trade Ltd.
    Inventors: Runzi Chang, Min She