Abstract: A semiconductor system includes a controller configured to apply a command address, a first chip selection signal, and a second chip selection signal, and a semiconductor device including a first rank and a second rank configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal.

Abstract: Systems, methods, circuits, and apparatuses for managing integrated circuits in memory devices are provided. In one aspect, a system includes a semiconductor device configured to store data, and a controller communicatively coupled to the semiconductor device. The controller is configured to send, to the semiconductor device, an instruction requesting transmission of the data; in response to determining that a predetermined time duration has elapsed after sending the instruction, initiate transmission of a read enable signal to the semiconductor device; receive, from the semiconductor device, a data strobe signal; and, in response to determining that the data strobe signal has a frequency matching a frequency of the read enable signal, read the data from the semiconductor device.

Abstract: A semiconductor system includes a controller configured to transmit a command address and a plurality of read strobe signals, and a semiconductor device including a first rank and a second rank that are configured to receive the command address and the plurality of read strobe signals and to perform a write operation and a read operation based on the command address. In the semiconductor device, the first rank is configured to calibrate a termination resistance value of the first rank to a target resistance value when a write operation for the first rank is performed. In the semiconductor device, the first rank is configured to calibrate the termination resistance value of the first rank to a dynamic resistance value based on the plurality of read strobe signals when a write operation for the second rank is performed.

Abstract: A method, system and computer program product for increasing automation of license plate reading accuracy, can involve searching by a correlation search process, ALPR (Automatic License Plate Recognition) results against an ALPR database of previous ALPR results, when an ALPR read by an ALPR search engine occurs with respect to a license plate, and constructing a confidence level for a correlation to a known previous license plate read based on a number of parameters and a number of times that the parameters match, when a match is found in the ALPR database for a parameter contained in the ALPR database as a result of the correlation search process.

Abstract: A method of operating a host device includes transmitting a read command that requests information related to an eye open monitor (EOM) operation performed in a memory device to the memory device, and receiving a response signal including the information related to the EOM operation performed in the memory device from the memory device.

Abstract: A method and apparatus for testing a command are provided. The method includes that: when the test platform exists a target command to be sent to a memory, a duration of a deselect command is determined according to a minimum time interval between a target command and each of historical commands and the time when the each of the historical commands is sent and the present time; the target command is sent to the memory after the deselect command.

Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.

Abstract: A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

Abstract: The present technology includes a data strobe clock output circuit. The data strobe clock output circuit includes a first output circuit configured to generate a rising clock and a falling clock in response to a clock and a first enable signal and output a first data strobe clock in response to the rising clock, the falling clock, and mode signals, and a second output circuit configured to generate a rising inverted clock and a falling inverted clock by inverting the rising clock and the falling clock generated by the first output circuit, and output a second data strobe clock in response to the rising inverted clock, the falling inverted clock, a second enable signal, and the mode signals.

Abstract: A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a write training setting configured to adjust a write timing of data being sent by the memory controller to the one or more memory devices during write operations of the memory system.

Abstract: According to one embodiment, a transceiver includes a sampler, a pipeline, and a transmission circuit. The sampler takes a data signal received from a host at a timing based on a data strobe signal received from the host. The pipeline transfers the data signal taken by the sampler using at least a clock signal, different from the data strobe signal, as a drive signal. The transmission circuit acquires and transmits a data signal having passed through the pipeline.

Abstract: The embodiments provide an integrated circuit structure and a memory, and relates to the field of semiconductor memory technologies. The integrated circuit structure includes: a pad region, including a plurality of signal pads arranged along a target direction; and a circuit region arranged on one side of the pad region. The circuit region includes a plurality of input/output circuit modules arranged along the target direction and correspondingly connected to the signal pads. Each of the input/output circuit modules is configured to implement a sampling operation of an input signal and write a sampling result into a storage array, and read data stored in the storage array. A size of the circuit region along the target direction is smaller than that of the pad region along the target direction. According to the present disclosure, the performance of a write operation can be improved for the memory.

Abstract: A stacked semiconductor device includes a base die including an input buffer and a parallel circuit; and a plurality of core dies stacked over the base die, the core dies coupled to the base die through a plurality of through-electrodes, wherein the input buffer receives write data in a first order and a write inversion signal, the parallel circuit sorts consecutive bits of the write data to be positioned adjacent to each other so that the write data becomes first parallel data and to transfer the first parallel data to respective first to n-th internal input/output lines, and each of the core dies includes an input control circuit to re-sort the first parallel data transferred via the respective first to n-th internal I/O lines into the write data and a write inversion circuit to selectively invert the re-sorted write data according to the write inversion signal.

Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may execute a read operation by setting a command delay time for determining whether to merge and process read commands, for each of a plurality of time periods, and may set a target command delay time, from among the command delay times set for each of the plurality of time periods, to be used for determining whether to merge and process a subsequent read command with one or more prior read commands based on the execution result of the read operation for each of the plurality of time periods.

Abstract: A system-on-chip (SoC) includes a system memory, a memory controller, and a memory management system coupled therebetween. The memory management system is configured to receive, from the memory controller, a first control signal that is indicative of a memory operation associated with the system memory, and output and provide a second control signal to the system memory to control an execution of the memory operation. The second control signal is outputted such that when the memory operation corresponds to a first read operation, the first read operation is executed with the system memory, and when the memory operation corresponds to a first write operation, a second read operation is executed with the system memory followed by the first write operation. Thus, the memory management system prevents memory corruption of the system memory when an asynchronous reset event is detected in the SoC.

Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.

Abstract: A memory controller, a method for read control of a memory, and an associated storage system are provided. The memory controller includes a data latch circuit, a mask generating circuit, a clock control logic electrically coupled to the mask generating circuit, and a demultiplexer electrically coupled to the data latch circuit and the clock control logic. The data latch circuit latches a series of data within a data signal from the memory according to a data strobe signal from the memory. The mask generating circuit generates a mask signal according to the data strobe signal. The clock control logic generates a receiving clock signal according to the mask signal. The demultiplexer determines valid data within the series of data with aid of the receiving clock signal.

Abstract: A semiconductor device comprises an input circuit that includes a first comparator configured to output a first output signal and a second output signal having a phase opposite to that of the first output signal, based on a comparison result of a first input signal and a second input signal which is a complementary signal of the first input signal. A duty ratio of the first output signal and a duty ratio of the second output signal are different from a duty ratio of the first input signal and a duty ratio of the second input signal, respectively.

Abstract: An integrated circuit device includes a read strobe signal transmitter including a main output drive circuit and a victim output drive circuit having an output terminal electrically coupled to an output terminal of the main output drive circuit. The read strobe signal transmitter is configured to: (i) generate a periodic active read strobe signal during a read time interval, in response to a pair of periodic drive signals, which are 180° out-of-phase relative to each other during the read time interval, and (ii) generate a disabled read strobe signal at a fixed logic level during a non-read time interval, in response to an active victim control signal. The main output drive circuit is responsive to the pair of periodic drive signals during the read time interval, and the victim output drive circuit is responsive to the active victim control signal during the non-read time interval.

Abstract: Provided are techniques for using a memory subsystem for a workload job. A section of a memory subsystem is allocated to a workload job, where the memory subsystem is comprised of a plurality of heterogeneous memory devices. In response to a track being modified for the workload job in a cache, it is determined that modified tracks have reached a threshold portion of the cache. In response to determining that the track exists in the section of the memory subsystem, data in the track in the section of the memory subsystem is overwritten with data in the track in the cache. in response to determining that the track does not exist in the section of the memory subsystem, the data in the track in the cache is copied to the track in the section of the memory subsystem, and the track is demoted from the cache.

Abstract: Methods, systems, and devices for input/output line sharing for memory subarrays are described. I/O lines may be shared across subarrays, which may correspond to separate memory tiles. The sharing of I/O lines may allow an I/O line to carry data from one subarray in response to access commands associated with one address range, and to carry data from another subarray in response to access commands associated with another address range. In some cases, sense amplifiers and other components may also be shared across subarrays, including across subarrays in different banks. The sharing of I/O lines may, in some cases, support activating only a subset of subarrays in a bank when accessing data stored in the bank, which may provide power savings.

Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Abstract: A system and a method. The system may include a computing device configured for monitoring delay across clock domains using a constant phase shift. The computing device may be further configured to: use a counter value, a known clock period of a primary clock domain, and a known clock period of a secondary clock domain to calculate a current offset between a last rising edge of a primary clock and a current rising edge of a secondary clock; monitor a calibration signal to verify alignment such that a zero state occurs when expected; and adjust a counter to maintain the alignment.

Abstract: An apparatus may include at least one output circuit configured to generate a desired output driver impedance (ODI) during a first operational mode. The least one output circuit may further be configured to independently generate a desired on-die termination (ODT) impedance during a second operational mode. Memory systems, memory devices, electronic systems, and related methods of operation are also described.

Abstract: A storage device includes a non-volatile memory including a buffer of a first size and a controller. The controller is configured to transmit a control command to the non-volatile memory, and then repeat a process including a first process of changing a phase value of a timing signal indicating timing to read or write data from or to the non-volatile memory and a second process of reading or writing data having a second size smaller than the first size from or to the non-volatile memory in synchronization with the timing signal of the changed phase value, a certain plurality of times without transmitting any other control command to the non-volatile memory during repetition of the process.

Abstract: A semiconductor memory device includes: a plurality of banks each including a plurality of cell mats and a plurality of sense amplifiers shared by adjacent cell mats; and a bank control circuit suitable for activating a normal word line of a particular cell mat of a bank selected according to a refresh command including bank information, and activating a target word line of a cell mat that does not share a sense amplifier with the particular cell mat according to a target refresh command after a preset delay time.

Abstract: A circuit configured to dynamically adjust data transfer speeds for a non-volatile memory die interface. The circuit includes an initialization circuit, a control circuit, a switch circuit, and a read-write circuit. The initialization circuit is configured to load multi-level cell settings that configure a memory interface for transfer of data for storage cells configured to store more than one bit per storage cell. The control circuit is configured to receive a read command that references single-level storage cells of a memory die. The switch circuit is configured to switch settings for the memory interface from the multi-level cell settings to single level cell settings, in response to receiving the read command. The read-write circuit is configured to read data for the read command from the memory die using the single level cell settings.

Abstract: Methods, systems, and apparatuses related to memory operation with on-die termination (ODT) are provided. A memory device may be configured to provide ODT at a first portion (e.g., rank) during multiple communications at a second portion (e.g., rank). For example, a memory device may receive a first command instructing a first portion to perform a first communication and instructing a second portion to enter an ODT mode. The device may perform, with the first portion, the first communication with a host while the second portion is in the ODT mode. The device may receive a second command instructing the first portion to perform a second communication, and the device may perform, with the first portion, the second communication while the second portion remains in the ODT mode. The second portion may persist in the ODT mode for an indicated number of communications, or until instructed to exit the ODT mode.

Abstract: A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

Abstract: Various embodiments described herein provide for a data transfer mechanism for a memory device, such as a Double Data Rate (DDR) memory device, which can improve critical timing within the memory device without a latency impact. In addition, various embodiments described herein provide for a switching sequence for a memory device, which can improve switching time for the memory device.

Abstract: A memory system includes a memory and a controller for providing the memory with a data strobe signal; and data synchronized with an internal data strobe signal, wherein the controller includes a signal generator for generating the data strobe signal, an inverter for selectively outputting one between a non-inverted data strobe signal having the same phase as the data strobe signal and an inverted data strobe signal having an inverted phase to the phase of the data strobe signal based on an inversion signal, a delayer for delaying the inverted data strobe signal or the non-inverted data strobe signal based on a delay signal and outputting the internal data strobe signal, and a trainer for performing a verification operation on the synchronized data and generating the inversion signal and the delay signal based on the verification operation result.

Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.

Abstract: A clock alignment system includes a first clock generator generating a first clock signal in a first clock domain and a second clock generator generating a second clock signal in a second clock domain slower than the first clock domain. A coarse delay-locked loop (DLL) generates third clock signals having corresponding phase offsets from the first clock signal, and a fine DLL generates a fourth clock signal by adjusting the phase of a selected one of the third clock signals. The second clock generator generates the second clock signal from the fourth clock signal. A phase detector compares phases of the first and second clock signals. A control circuit aligns the first and second clock signals by using the compared phases to select the third clock signal output by the coarse DLL, and control the phase adjustment by the fine DLL of this third clock signal.

Abstract: A memory device includes a data write circuitry. The data write circuitry is configured to capture a first write command received via an external input/output (I/O) interface. The data write circuitry is further configured to generate a first internal write start (InternalWrStart) in a data strobe (DQS) domain after capture of the first write command. The data write circuitry is additionally configured to write a first one or more data bits into at least one memory bank based on the first InternalWrStart, wherein the first InternalWrStart is generated internally in the memory device.

Abstract: In an embodiment, a differential strobe input squelch circuit includes a squelch sub-circuit that is configured to perform operations including receiving a true strobe signal, a complement strobe signal, and a strobe difference signal that is representative of a difference between the true strobe signal and the complement strobe signal; determining, based on the true strobe signal and the complement strobe signal, whether the strobe difference signal is defined or undefined; and outputting a modified strobe difference signal that is equal to the strobe difference signal when the squelch sub-circuit determines that the strobe difference signal is defined and that is instead equal to a constant strobe-level voltage when the squelch sub-circuit determines that the strobe difference signal is undefined.

Abstract: A semiconductor device includes a pre-shift circuit and a shift circuit. The pre-shift circuit shifts an internal write signal by a pre-shift period to generate a pre-write signal. The shift circuit shifts the pre-write signal by a shift period to generate a shift write signal for generating a column selection signal. The column selection signal is activated to select a column path through which data are inputted or outputted. The pre-shift period is set as a period corresponding to a multiple of “L” times a cycle of a clock signal, wherein “L” is a natural number which is equal to or greater than two.

Abstract: Apparatuses and methods for detecting refresh starvation at a memory. An example apparatus, may include a plurality of memory cells, and a control circuit configured to monitor refresh request commands and to perform an action that prevents unauthorized access to data stored at the plurality of memory cells in response to detection that timing of the refresh request commands has failed to meet a refresh timing limit.

Abstract: A method for performing enhanced pattern scanning includes the steps of: providing a three-dimensional memory structure including multiple physical memory elements; compiling multiple programmable finite state machines, each of the programmable finite state machines representing at least one deterministic finite automation data structure, the data structure being distributed over at least a subset of the physical memory elements; configuring a subset of the programmable finite state machines to operate in parallel on a same input data stream, while each of the subset of programmable finite state machines processes a different pattern subset; and providing a local result processor, the local result processor transferring at least a part of a match state from the deterministic finite automation data structures to corresponding registers within the local result processor, the part of the match state being manipulated being based on instructions embedded within the deterministic finite automation data structures.

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

Abstract: A semiconductor device includes a strobe signal generation circuit. The strobe signal generation circuit generates a strobe signal which is toggled in synchronization with a multiplication clock signal during enablement periods of a toggling drive signal and a down drive signal. A postamble period is set according to the toggling drive signal and the down drive signal.

Abstract: A semiconductor device includes a control circuit configured to receive a clock and generate first to fourth internal clocks which have different phases, and generate first to fourth masking clocks from a latency signal in synchronization with the first internal clock and the second internal clock depending on a mode signal; and a signal mixing circuit configured to output the first to fourth internal clocks as first to fourth strobe signals during enable periods of the first to fourth masking clocks.

Abstract: A system includes a data transmission unit, a termination resistor and a data reception unit. The data transmission unit may drive a data transmission line based on data, and drive the data transmission line to a voltage level corresponding to a termination voltage during a specified operation period. The termination resistor may be coupled between the data transmission line and a termination node. The data reception unit may receive a signal transmitted through the data transmission line.

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

Abstract: An integrated circuit includes: a delay circuit suitable for delaying one or more input signals; a toggle sensing circuit suitable for sensing whether or not the one or more input signals toggle; and a replica delay circuit suitable for delaying one or more clock signals in a section where no toggle of the one or more input signals is sensed by the toggle sensing circuit.

Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

Abstract: A semiconductor memory chip includes an upper data pad region, a lower data pad region, and an additional pad region. Upper data pads, upper data strobe signal pair pads, and an upper data mask signal pad are arranged in the upper data pad region. Lower data pads, lower data strobe signal pair pads, and a lower data mask signal pad are arranged in the lower data pad region adjacent to and below the upper data pad region. An inverted termination data strobe signal pad used for a second semiconductor memory package and internally connected to the upper data mask signal pad, which is used for a first semiconductor memory package, is arranged in the additional pad region adjacent to and above the upper data pad region.

Abstract: A semiconductor device having a first inverter electrically connected to a first node. A second inverter is electrically connected to a second node. A third clocked inverter is electrically connected to an output node of the first inverter. A fourth clocked inverter is electrically connected to an output node of the second inverter. A third inverter is electrically connected to an output node of a first clocked inverter and an output node of a second clocked inverter. A fourth inverter is electrically connected to an output node of the third clocked inverter and an output node of the fourth clocked inverter. A comparison circuit is electrically connected to an output node of the third inverter and an output node of the fourth inverter.

Abstract: A semiconductor device may be provided. The semiconductor device may include a power-down signal generation circuit and a refresh signal generation circuit. The power-down signal generation circuit may be configured to generate a power-down signal which is enabled during a power-down operation period based on a multi-operation signal that is generated by decoding commands. The refresh signal generation circuit may be configured to generate a refresh signal which is enabled during a refresh operation period based on the multi-operation signal and an operation selection signal.

Abstract: The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.