Plural Blocks Or Banks Patents (Class 365/230.03)
  • Patent number: 11189341
    Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chiting Cheng
  • Patent number: 11171798
    Abstract: A network device configured to perform scalable, in-network computations is described. The network device is configured to process pull requests and/or push requests from a plurality of endpoints connected to the network. A collective communication primitive from a particular endpoint can be received at a network device. The collective communication primitive is associated with a multicast region of a shared global address space and is mapped to a plurality of participating endpoints. The network device is configured to perform an in-network computation based on information received from the participating endpoints before forwarding a response to the collective communication primitive back to one or more of the participating endpoints. The endpoints can inject pull requests (e.g., load commands) and/or push requests (e.g., store commands) into the network. A multicast capability enables tasks, such as a reduction operation, to be offloaded to hardware in the network device.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 9, 2021
    Assignee: NVIDIA Corporation
    Inventors: Benjamin Klenk, Nan Jiang, Larry Robert Dennison, Gregory M. Thorson
  • Patent number: 11164907
    Abstract: A method may include forming two vertical transport field effect transistors stacked one atop the other and separated by a resistive random access memory structure. The two vertical transport field effect transistors may include a source, a channel, and a drain, wherein a contact layer of the resistive random access memory structure functions as the drain of the two vertical transport field effect transistors. Forming the two vertical transport field effect transistors may further include forming a first source and a second source. The first source is a bottom source and the second source is a top source. The method may include forming a gate conductor layer surrounding the channel. The resistive random access memory structures may include faceted epitaxy defined by pointed tips. The pointed tips of the faceted epitaxy may extend vertically toward each other. The faceted epitaxy may be between the two vertical transport field effect transistors.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Takashi Ando
  • Patent number: 11133043
    Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: September 28, 2021
    Assignee: Arm Limited
    Inventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan
  • Patent number: 11133042
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to enable a start signal and an oscillation signal based on the reset signal. The oscillation signal starts to oscillate in response to the reset signal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim, Dae Suk Kim
  • Patent number: 11127455
    Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Bar-Ilan University
    Inventors: Adam Teman, Amir Shalom, Robert Giterman, Alexander Fish
  • Patent number: 11120850
    Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Glen E. Hush
  • Patent number: 11119671
    Abstract: A method facilitating a memory system operable in advance during power-up is introduced, including the following. A power-up verification circuit is provided, internally coupled to a memory control circuit of the memory system. During a period of the power-up in which a power voltage signal is ramping but not yet reaching a power voltage threshold, a power-up verification state machine of the power-up verification circuit is activated responsive to a power-on reset signal and the power voltage signal. The activated power-up verification state machine communicates with circuit units of the memory system to enable execution of corresponding detections on the circuit units in accordance with a sequence of states of the power-up verification state machine. After completion of the sequence of states, a verification completion signal is sent to enable the memory control circuit to be powered by the power voltage signal and operable to control the memory system.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: September 14, 2021
    Assignee: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC.
    Inventor: Teng-Chuan Cheng
  • Patent number: 11100969
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to enable a start signal and an oscillation signal based on the reset signal. The oscillation signal starts to oscillate in response to the reset signal.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Hun Kwon, Jae Il Kim, Dae Suk Kim
  • Patent number: 11100985
    Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Nagashima, Hirofumi Inoue
  • Patent number: 11094357
    Abstract: A memory device includes a memory array with memory blocks each having a plurality of memory cells, and one or more current monitors configured to measure current during post-deployment operation of the memory device; and a controller configured to identify a bad block within the memory blocks based on the measured current, and disable the bad block for preventing access thereof during subsequent operations of the memory device.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Aaron S. Yip, Theodore T. Pekny
  • Patent number: 11086534
    Abstract: An embodiment of an apparatus includes a plurality of processing circuits, a plurality of memory circuits, and a memory controller circuit coupled to each memory circuit via a respective communication channel. A particular processing circuit may generate a data stream that includes a plurality of data blocks. The memory controller circuit may receive the plurality of data blocks from the particular processing circuit. The memory controller circuit may distribute the plurality of data blocks among the plurality of memory circuits based on respective utilizations of the plurality of communication channels.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 10, 2021
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Thejasvi Magudilu Vijayarai
  • Patent number: 11080219
    Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Eric J. Stave
  • Patent number: 11074910
    Abstract: An electronic device includes a microphone obtaining an audio signal, a memory in which a speaker model is stored, and at least one processor. The at least one processor is configured to obtain a voice signal from the audio signal, to compare the voice signal with the speaker model to verify a user, and, if a verification result indicates that the user corresponds to a pre-enrolled speaker, to perform an operation corresponding to the obtained voice signal.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: July 27, 2021
    Inventors: Young Woo Lee, Ho Seon Shin, Sang Hoon Lee
  • Patent number: 11074947
    Abstract: A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: July 27, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Yuichiro Ajima, Toshiyuki Shimizu
  • Patent number: 11056155
    Abstract: A memory device can include a plurality of banks, each bank including a memory cell array of nonvolatile (NV) memory cells; a plurality of charge pumps, including a first charge pump and second charge pump; and a switch circuit. The switch circuit can be configured to, in a first mode, connect the first charge pump to first circuits of the banks and isolate the second charge pump from the first circuits, and in a second mode, isolate the first charge pump from the first circuits and connect the second charge pump to the first circuits.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Adesto Technologies Corporation
    Inventors: Stephen Trinh, Duong Vinh Hao, Nguyen Khac Hieu, Hendrik Hartono, John Dinh, Shane Charles Hollmer
  • Patent number: 11056183
    Abstract: Various implementations described herein are directed to an integrated circuit having multiple bitcell arrays and multiple input ports including a single write input port for the multiple bitcell arrays and multiple read input ports for the multiple bitcell arrays. The integrated circuit may include multiple read output ports for the multiple bitcell arrays. The single write input port is used for writing data to the multiple bitcell arrays, and the multiple read input ports are used separately for reading data from the multiple bitcell arrays for output to the multiple read output ports.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: July 6, 2021
    Assignee: Arm Limited
    Inventors: Yew Keong Chong, Andy Wangkun Chen, Sriram Thyagarajan
  • Patent number: 11043271
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: June 22, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Arun Kumar Shukla, Sharad Gupta, Silky Mohanty, Athira Kanchiyil, Arunkumar Mani, Noor Mohamed
  • Patent number: 11029852
    Abstract: The present application describes embodiments of an interface for coupling flash memory and dynamic random access memory (DRAM) in a processing system. Some embodiments include a dedicated interface between a flash memory and DRAM. The dedicated interface is to provide access to the flash memory in response to instructions received over a DRAM interface between the DRAM and a processing device. Some embodiments of a method include accessing a flash memory via a dedicated interface between the flash memory and a dynamic random access memory (DRAM) in response to an instruction received over a DRAM interface between the DRAM and a processing device.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: June 8, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: James Bauman
  • Patent number: 11031049
    Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Joe M. Jeddeloh, Brent Keeth
  • Patent number: 11017844
    Abstract: A semiconductor memory device includes a cache latch group including a plurality of even latch stages and a plurality of odd latch stages arranged alternately with each other; and a sense amplifier group coupled to the cache latch group through a plurality of first bit out lines respectively corresponding to the plurality of even latch stages and through a plurality of second bit out lines respectively corresponding to the plurality of odd latch stages.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Wan Seob Lee
  • Patent number: 11009864
    Abstract: Systems, methods, and devices for monitoring operation of industrial equipment are disclosed. In one embodiment, a monitoring system is provided that includes a passive backplane and one more functional circuits that can couple to the backplane. Each of the functional circuits that are coupled to the backplane can have access to all data that is delivered to the backplane. Therefore, resources (e.g., computing power, or other functionality) from each functional circuits can be shared by all active functional circuits that are coupled to the backplane. Because resources from each of the functional circuits can be shared, and because the functional circuits can be detachably coupled to the backplane, performance of the monitoring systems can be tailored to specific applications. For example, processing power can be increased by coupling additional processing circuits to the backplane.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: May 18, 2021
    Assignee: BENTLY NEVADA, LLC
    Inventors: Steven Thomas Clemens, Dustin Hess
  • Patent number: 11011226
    Abstract: Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: May 18, 2021
    Assignee: Unity Semiconductor Corporation
    Inventors: Christophe Chevallier, Chang Hua Siau
  • Patent number: 11010225
    Abstract: An electronic control unit includes a computer that outputs a monitoring signal and an external monitoring circuit that monitors a state of the computer based on the monitoring signal. The computer includes a monitoring signal output section that generates and outputs the monitoring signal to the external monitoring circuit by performing a software process; a self-diagnostic section that self-diagnoses the computer and detects an abnormality by identifying a cause of the abnormality; and a break signal output section that outputs a break signal to interrupt an input of the monitoring signal to the external monitoring circuit by performing a hardware process when an abnormality in the monitoring signal output section is detected.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 18, 2021
    Assignee: DENSO CORPORATION
    Inventors: Daichi Marui, Mitsuru Aoki
  • Patent number: 11004521
    Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 11, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Yasuhiro Suematsu, Masaru Koyanagi, Kensuke Yamamoto, Ryo Fukuda
  • Patent number: 11003387
    Abstract: An arrangement for providing a combined data and control signal for a multi die flash, comprising, a memory arrangement, the memory arrangement comprising at least two dies, a controller configured to send and receive signals to the memory arrangement and a common line connected to the memory arrangement and the controller and configured to transmit the signals from the controller to the at least two dies, wherein the arrangement is configured to provide a combined data and combined control signals to the multi-die flash.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 11, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yoav Markus, Alexander Bazarsky
  • Patent number: 10984866
    Abstract: A non-volatile memory device includes a plurality of memory blocks grouped into pages, page buffer regions corresponding to the pages of the plurality of memory blocks; and a peripheral circuit region for supporting operations of the pages of the plurality of memory blocks. The peripheral circuit region comprises a plurality of pool capacitors. At least one of the memory blocks is a dummy block. The dummy block is configured to form a supplementary pool capacitor for suppressing power noise.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: April 20, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Jin Yong Oh
  • Patent number: 10971212
    Abstract: A memory chip including a memory bank, an address decoder circuit and a control circuit is provided. The memory bank includes a first sub-bank coupled to a first word line and a first access line and a second sub-bank coupled to a second word line and the first access line. The first sub-bank outputs data to the first access line via a first path. The second sub-bank outputs data to the first access line via a second path. The address decoder circuit decodes an external address to generate a row address and a column address. The control circuit controls the first path and the second path according to the row address and the column address. In response to the row address indicating the first word line and the column address indicating the first access line, the control circuit turns on the first path and turns off the second path.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: April 6, 2021
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chien-Ti Hou, Wu-Chuan Cheng
  • Patent number: 10964385
    Abstract: Methods, systems, and devices for restoring memory cell threshold voltages are described. A memory device may perform a write operation on a memory cell during which a logic state is stored at the memory cell. Upon detecting satisfaction of a condition, the memory device may perform a read refresh operation on the memory cell during which the threshold voltage of the memory cell may be modified. In some cases, the duration of the read refresh operation may be longer than the duration of a read operation performed by the memory device on the memory cell or on a different memory cell.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Lingming Yang, Nevil Gajera, Karthik Sarpatwari
  • Patent number: 10943624
    Abstract: Apparatuses and methods can be related to countering noise at a memory array. Countering noise can include enable switches to connect third digit lines of the first array adjacent to the respective first digit lines to fourth digit lines of the second array adjacent to the reference digit lines such that the reference digit lines experience a same amount of digit line coupling noise as the first digit lines experience.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Scott J. Derner
  • Patent number: 10943643
    Abstract: First and second memory cell arrays each having memory cells arranged in the X and Y directions lie side by side in the Y direction with space between them. A relay buffer is provided between first and second row decoders for buffering a control signal to be supplied to the second row decoder. An inter-array block between the first and second memory cell arrays is constituted by at least either a tap cell or a dummy memory cell. The relay buffer and the inter-array block are the same in position and size in the Y direction.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: March 9, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Masataka Sato, Hideo Akiyoshi, Masanobu Hirose, Yoshinobu Yamagami
  • Patent number: 10922169
    Abstract: A memory device includes a non-destructive memory array that includes memory cells arranged in rows and columns. The array includes a plurality of word lines, first bit lines and second bit lines, a NOR gate per column Each word line activates memory cells in a row and thereby establishes an activated row. First bit lines and second bit lines connect memory cells in columns, each first bit line provides the result of a Boolean AND operation between data stored in the first activated row and data stored in the second activated row. Each second bit line provides the result of a Boolean NOR operation between data stored in the first activated row and data stored in the second activated row. Each per-column NOR gate is connected to the first and second bit lines of each column and compares data stored in the first activated row with data stored in the second activated row.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 16, 2021
    Assignee: GSI Technology Inc.
    Inventor: Avidan Akerib
  • Patent number: 10902902
    Abstract: A memory system may include a memory system may include a memory device including a table suitable for managing rows for an additional refresh operation; and a memory controller comprising: a replica table corresponding to the table of the memory; an error history storage circuit suitable for storing an error history of the memory device; and a determination circuit suitable for determining whether to perform an active operation of a target row to be evicted from the replica table without the additional refresh operation, using the error history, when the target row is present.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Mun-Gyu Son
  • Patent number: 10902894
    Abstract: A semiconductor device includes a column control circuit and a core circuit. The column control circuit generates a read column signal and a write column signal from a read bank address signal and a write bank address signal in response to a read latch pulse and a write latch pulse, which are generated during a masked write operation. The core circuit is configured to include a plurality of banks. Any one of the plurality of banks is activated by the read column signal and the write column signal to perform an internal read operation and a write operation.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Woongrae Kim
  • Patent number: 10871970
    Abstract: Technologies are disclosed herein that allow for utilization of memory channel storage (“MCS”) devices in a computing system. The MCS device may be detected during a boot phase of the computing system, and the address data for the MCS device may be detected through repeated manipulation of a logical offset. The address data may then be stored for later use in memory allocation.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 22, 2020
    Assignee: AMERICAN MEGATRENDS INTERNATIONAL, LLC
    Inventors: Senthamizhsey Subramanian, Bejean David Mosher
  • Patent number: 10872894
    Abstract: In some embodiments, memory circuitry comprises a pair of immediately-adjacent memory arrays having space laterally there-between. The memory arrays individually comprise memory cells individually having upper and lower elevationally-extending transistors and a capacitor elevationally there-between. The memory arrays comprise individual rows that (a) have an upper access line above and directly electrically coupled to a lower access line, and (b) are directly electrically coupled to one another across the space. The lower access line in one of the rows extends across the space from one of the memory arrays to the other of the memory arrays. Another of the rows comprises a conductive interconnect extending across a portion of the space. The conductive interconnect includes a horizontally-extending portion within the space that is laterally offset from the another row. Other aspects and implementations are disclosed.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 22, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10872572
    Abstract: The embodiments of the present disclosure provide a gate driving circuit and a method for controlling the same, and a display apparatus.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 22, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guangliang Shang, Seungwoo Han, Lijun Yuan, Mingfu Han, Haoliang Zheng, Xing Yao, Zhenyu Zhang
  • Patent number: 10847210
    Abstract: A memory device includes a plurality of memory cells arranged in an array having a plurality of rows and a plurality of columns. A first word line is connected to a first plurality of the memory cells of a first row of the array, and a second word line is connected to a second plurality of the memory cells of the first row of the array. In some examples, the plurality of memory cells are arranged in or on a substrate, and the first word line is formed in a first layer of the substrate and the second word line is formed in a second layer of the substrate.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yangsyu Lin, Chiting Cheng
  • Patent number: 10839890
    Abstract: Systems, apparatuses, and methods related to subrow addressing for electronic memory and/or storage are described. Independent subrow addressing may enable energy consumed by performance of an operation on a particular subset of data values stored by a row to more closely correspond to the size of the particular subset of data values relative to energy consumed by addressing and activating the complete row. For instance, one such apparatus includes a plurality of subrows within a row of memory cells and a controller configured to selectably address and manage an activation state of each subrow of the plurality of subrows. The apparatus further includes subrow driver circuitry coupled to the controller. The subrow driver circuitry is configured to maintain one or more subrows of the plurality in the activation state based at least in part on signaling from the controller.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Richard C. Murphy
  • Patent number: 10838732
    Abstract: Systems, apparatuses and methods for organizing bits in a memory device are described. In a number of embodiments, an apparatus can include an array of memory cells, a data interface, a multiplexer coupled between the array of memory cells and the data interface, and a controller coupled to the array of memory cells, the controller configured to cause the apparatus to latch bits associated with a row of memory cells in the array in a number of sense amplifiers in a prefetch operation and send the bits from the sense amplifiers, through a multiplexer, to a data interface, which may include or be referred to as DQs. The bits may be sent to the DQs in a particular order that may correspond to a particular matrix configuration and may thus facilitate or reduce the complexity of arithmetic operations performed on the data.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Glen E. Hush, Aaron P. Boehm, Fa-Long Luo
  • Patent number: 10838851
    Abstract: A method of operating a memory controller performing activation of a memory device, the method including determining a selection signal for each tile column in a memory block of the memory device by activating respective local word lines, wherein the block selection signal is determined by performing a radix n operation on a vector identifying elements to be read or written.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Philip Jacob, Kyu-Hyoun Kim
  • Patent number: 10832757
    Abstract: A receiver implemented in an integrated circuit device is described. The receiver circuit comprises a first receiver circuit configured to receive first data, wherein the first receiver circuit comprises a first memory element configured to receive the first data in response to a first clock signal; a latency mirror circuit configured to receive second data, wherein the latency mirror circuit comprises a second memory element configured to receive the second data in response to a second clock signal; and a latency control circuit configured to detect a latency in the second data, wherein the latency control circuit adjusts a phase of the first clock signal used to receive the first data in the first receiver circuit.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: November 10, 2020
    Assignee: XILINX, INC.
    Inventors: Paolo Novellini, Giovanni Guasti
  • Patent number: 10818345
    Abstract: An integrated circuit memory device, having: memory cells; a circuit patch configured on an integrated circuit die; a plurality of neighboring patches configured on the integrated circuit die; first connections from the circuit patch to the neighboring patches respectively; a plurality of surrounding patches configured on the integrated circuit die; and second connections from the neighboring patches to the surrounding patches. In determining whether or not to apply an offset voltage to be driven by the neighboring patches and the surrounding patches on non-selected memory cells, to at least partially offset a voltage increase applied by the circuit patch on one or more selected memory cells, the circuit patch communicates with the neighboring patches through the first connections, and communicates with the surrounding patches through the first connections, the neighboring patches, and the second connections.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Nathan Joseph Sirocka, Mingdong Cui
  • Patent number: 10803927
    Abstract: A memory circuit including a plurality of elementary cells distributed in a plurality of arrays, each including N columns, N being an integer greater than or equal to 2, wherein: each column of each array includes a first local bit line directly connected to each of the cells in the column; each column of each array includes a first general bit line coupled to the first local bit line of the column by a first coupling circuit; and the first general bit lines of the columns of same rank j of the different arrays, j being an integer in the range from 0 to M?1, are coupled together.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: October 13, 2020
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Jean-Philippe Noel, Avishek Biswas, Bastien Giraud
  • Patent number: 10797941
    Abstract: A network element includes one or more hardware memory resources of fixed storage capacity for storing data used to configure a plurality of networking features of the network element. A utilization management process runs on the network element to perform operations including obtaining utilization data representing utilization of the one or more hardware memory resources, and analyzing the utilization data of the one or more hardware memory resources to produce summarized utilization data.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 6, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Samar Sharma, Rakesh B. Goudar, Chandrashekarappa Surekha Puttasubbappa, John Andrew Fingerhut
  • Patent number: 10796769
    Abstract: The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Sang Hwan Kim, Min Su Kim, Kyeong Min Chae
  • Patent number: 10788985
    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Shunichi Saito
  • Patent number: 10777258
    Abstract: A semiconductor device is disclosed, which relates to a technology for a sense-amplifier (sense-amp) configured to compensate for mismatch of a sensing bit-line. The semiconductor device includes a sense-amplifier configured to selectively control connection between a pair of bit lines and a pair of sensing bit lines in response to a connection control signal in an offset compensation period, and precharge a pull-down power-supply line with a bit line precharge voltage level in the offset compensation period. The semiconductor device also includes a pull-down voltage controller configured to increase a voltage of the pull-down power-supply line by a predetermined level in response to a pull-down control signal in the offset compensation period.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Sik Won, Jae Jin Lee
  • Patent number: 10777241
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may be configured to output a reset signal, command/address signals and data. The second semiconductor device may be configured to generate internal commands, internal addresses and internal data for performing an initialization operation. The second semiconductor device may be configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventors: Dae Suk Kim, Jae Il Kim, Hong Jung Kim
  • Patent number: 10770132
    Abstract: A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read operation is a normal read operation or a burst mode read operation.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: September 8, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Changho Jung, Keejong Kim, Arun Babu Pallerla, Chulmin Jung