Abstract: A system includes a processing device that determines whether a memory bank is active and adds an activate command for a row of the memory bank accessed by an oldest command for the memory bank to a command scheduler in response to determining the memory bank is not active. The processing device determines whether the row of the memory bank has a corresponding row command in response to determining the memory bank is active. The processing device determines whether a close page mode is enabled or an open row timer has expired on the row and adds a precharge command to the command scheduler in response to determining the close page mode is enabled or the open row timer has expired. The processing device executes a command in the command scheduler based on a priority of commands included in the command scheduler.

Abstract: To provide a display device including a flexible panel that can be handled without seriously damaging a driver circuit or a connecting portion between circuits. The display device includes a bent portion obtained by bending an element substrate. A circuit for driving the display device is provided in the bent portion and a wiring extends from the circuit, whereby the strength of a portion including the circuit for driving the display device is increased and failure of the circuit is reduced. Furthermore, the element substrate is bent in a connecting portion between an external terminal electrode and an external connecting wiring (FPC) so that the element substrate provided with the external terminal electrode fits the external connecting wiring, whereby the strength of the connecting portion is increased.

Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.

Abstract: A memory for an artificial neural network (ANN) accelerator is provided. The memory includes a first bank, a second bank and a bank selector. Each bank includes at least two word lines and a plurality of write word selectors. Each word line stores a plurality of words, and each word has a plurality of bytes. Each write word selector has an input port and a plurality of output ports, is coupled to a corresponding word in each word line, and is configured to select a byte of the corresponding word of a selected word line based on a byte select signal. The bank selector is coupled to the write word selectors of the first bank and the second bank, and configured to select a combination of write word selectors from at least one of the first bank and the second bank based on a bank select signal.

Abstract: A circuit module with improved line load, may comprise a first line, a first switch, a second line, a second switch and a second driver. The first switch may be on and off to conduct and stop conducting between the first line and a first node. The second switch may be on and off to conduct and stop conducting between the second line and the first node. The second driver, coupled to the second line, may be enabled to drive the second line according to a voltage of a second node, and may be disabled to stop driving the second line. The voltage of the second node may be controlled by a voltage of the first node. When the first switch is on, the second switch may be off. When the second switch is off, the second driver may be enabled.

Abstract: Apparatuses, systems, and methods for address based memory performance. A memory array may include a first performance region and a second performance region, each of which may have different performance characteristics from each other. The second region may be distinguished from the first region based on the addresses which are associated with each region. The second performance region may have different performance characteristics based on differences in the layout, components, logic circuits, and combinations thereof. For example, the second region, compared to the first region, may have reduced difference to the data terminals, reduced length of digit lines, a different type of sense amplifier, different refresh address tracking, and combinations thereof. The controller may perform access operations on the memory with different timing based on which region of the memory is accessed.

Abstract: A semiconductor device includes a controller circuit and a signal generating circuit. The controller circuit is coupled to a plurality of memory devices and configured to generate a plurality of chip enable signals. One of the chip enable signals is provided to one of the memory devices, so as to respectively enable the corresponding memory device. The signal generating circuit is disposed outside of the controller circuit and configured to receive the chip enable signals and generate a termination circuit enable signal according to the chip enable signals. The termination circuit enable signal is provided to the memory devices. When a state of any of the chip enable signals is set to an enabled state, a state of the termination circuit enable signal generated by the signal generating circuit is set to an enabled state.

Abstract: A memory controller includes transaction queue circuitry, a first skip event, a second skip event, a third skip event, and scheduler circuitry. The transaction queue circuitry is configured to store a first transaction, a second transaction, and a third transaction. The first transaction received is by the transaction queue circuitry before the second transaction and the third transaction. The second transaction is received by the transaction queue circuitry before the third transaction. The first skip event counter is associated with the first transaction. The second skip event counter is associated with the second transaction. The third skip event counter is associated with the third transaction. The scheduler circuitry is configured to select the third transaction before selecting the first transaction, increase a value of the first skip event counter based on selecting the third transaction before the first transaction, and communicate the third transaction to a memory device.

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

Abstract: A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

Abstract: A system is provided. The system includes a multiply-and-accumulate circuit and a local generator. The multiply-and-accumulate circuit is coupled to a memory array and generates a multiply-and-accumulate signal indicating a computational output of the memory array. The local generator is coupled to the memory array and generates at least one reference signal at a node in response to one of a plurality of global signals that are generated according to a number of the computational output. The local generator is further configured to generate an output signal according to the signal and a summation of the at least one reference signal at the node.

Abstract: A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.

Abstract: An industrial control system module and methods are described for self-destruction or the destruction and/or erasure of sensitive data within the industrial control system module upon an indication of an unauthorized module access event. In an implementation, a secure industrial control system module includes a circuit board including electrical circuitry; a sealed encasement that houses the circuit board, where the sealed encasement includes a housing having a first housing side and a second housing side, where the housing is configured to house the circuit board when the first housing side and the second housing side are coupled together; and a first sensor component integrated with the sealed encasement, where the first sensor component is communicably coupled to the circuit board and electrical circuitry and is configured to provide an indication of an unauthorized access event.

Abstract: A memory device includes at least one memory cell block, a first edge block, a second edge block, multiple first sense amplifiers, and multiple second sense amplifiers. The first edge block is coupled to multiple first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to multiple second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are disposed between the first edge block and the memory cell block. The second sense amplifiers are disposed between the second edge block and the memory cell block.

Abstract: A memory unit with time domain edge delay accumulation for computing-in-memory applications is controlled by a first word line and a second word line. The memory unit includes at least one memory cell, at least one edge-delay cell multiplexor and at least one edge-delay cell. The at least one edge-delay cell includes a weight reader and a driver. The weight reader is configured to receive a weight and a multi-bit analog input voltage and generate a multi-bit voltage according to the weight and the multi-bit analog input voltage. The driver is connected to the weight reader and configured to receive an edge-input signal. The driver is configured to generate an edge-output signal having a delay time according to the edge-input signal and the multi-bit voltage. The delay time of the edge-output signal is positively correlated with the multi-bit analog input voltage multiplied by the weight.

Abstract: Disclosed herein is an apparatus that includes: a semiconductor substrate including first and second source regions coupled to a first power supply line and first and second drain regions coupled to a second power supply line, the first drain region being arranged between the first and second source regions, the second source region being arranged between the first and second drain regions; and gate electrodes including a first gate electrode arranged between the first source region and the first drain region, a second gate electrode arranged between the first drain region and the second source region, and a third gate electrode arranged between the second source region and the second drain region. The first and third gate electrodes are supplied with a first control signal. The second gate electrode is supplied with a second control signal.

Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.

Abstract: A programmable logic circuit includes multiple logic blocks that are connected communicatively, wherein multiple modules are reconfigured in any of the logic blocks, and wherein the modules include a first module that is being executed and a second module that is not being executed, and start of execution of the second module is delayed from a start time point of execution of the first module so as to obtain a state in which a first time at which the first module accesses a memory does not overlap a second time at which the second module accesses the memory.

Abstract: A fast burst program sequence that reduces overall NAND flash programming time is disclosed. The burst program sequence includes maintaining a charge pump in an ON state and not fully discharging the WL/BLs at the conclusion of the programming phase of each program operation. As a result, the fast burst program sequence provides total program time savings over an existing cache program sequence by eliminating the full WL/BL discharge and charge pump reset that conventionally occurs after each program operation, which in turn, allows for the transfer of next page data from the page buffer to the data latches to be hidden within the program time of a prior/current program operation.

Abstract: Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.

Abstract: A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Abstract: To provide a semiconductor device further reduced in size. A semiconductor device including: a multilayer wiring board one surface of which is provided with an external connection terminal; and a plurality of active components that are provided to be stacked inside the multilayer wiring board and are connected to the external connection terminal via a connection via. The plurality of active components include a first active component provided on another surface side that is opposite to the one surface, and a second active component that is provided closer to the one surface than the first active component is and has a smaller planar area than the first active component.

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Abstract: A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area.

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

Abstract: A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.

Abstract: Methods and systems are disclosed for calibrating, by a memory interface system, an interface with dynamic random-access memory (DRAM) using a dynamically changing training clock. Techniques disclosed comprise receiving a system clock having a clock signal at a first pulse rate. Then, during the training of the interface, techniques disclosed comprise generating a training clock from the clock signal at the first pulse rate, the training clock having a clock signal at a second pulse rate, and sending, based on the generated training clock, command signals, including address data, to the DRAM.

Abstract: A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.

Abstract: In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.

Abstract: A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

Abstract: Methods, systems, and devices for edgeless memory clusters are described. Systems, devices, and techniques are described for eliminating gaps between clusters by creating groups (e.g., domains) of clusters that are active at a given time, and using drivers within inactive clusters to perform array termination functions for abutting active clusters. Tiles on the edges of a cluster may have drivers that operate both for the cluster, and for a neighboring cluster, with circuits (e.g., a multiplexers) on the drivers to enable operations for both clusters.

Abstract: An interface circuit, a data transmission circuit and a memory are provided. The interface circuit includes a clock pad, data pads and input buffer circuits, where the clock pad and the data pads are arranged in the first row, and the M data pads are arranged on two sides of the clock pad, half of the M data pads being arranged on each side, where the M input buffer circuits are arranged in the second row and form an axis perpendicular to the first row with the data pads as reference, and the M input buffer circuits are arranged on two sides of the axis, half of the M input buffer circuits being arranged on each side, and where the distance between each input buffer circuit and the axis is smaller than the distance between the data pad corresponding to the input buffer circuit and the axis.

Abstract: A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

Abstract: A pipe latch circuit may include first and second latching circuit groups. The first latching circuit group may control a latching operation and an output operation based on a plurality of pipe input control signals. The second latching circuit group may control a latching operation and an output operation based on the plurality of pipe input control signals and a plurality of pipe output control signals.

Abstract: A processor circuit sends a read request. A clock signal of the processor circuit corresponds to a first counting value. A memory circuit stores data and sends a data strobe signal in response to the read request. The data strobe signal corresponds to a second counting value. The processor circuit includes a selector circuit and a feedback circuit. The selector circuit selects and outputs a flag signal from a plurality of flag control signals according to the second counting value. The feedback circuit generates an enable signal according to a set signal associated with the first counting value, the flag signal associated with the second counting value, and a data strobe gate signal, and generates the data strobe gate signal according to the enable signal and the data strobe signal. The processor circuit reads the data according to the data strobe gate signal.

Abstract: A memory module including a memory array of storage transistors and a control circuit where the control circuit includes a memory interface for providing high bandwidth access to the memory array on serial data lanes. In some embodiments, the control circuit of a memory module includes multiple transceivers for connecting to serial data lanes. In one embodiment, the memory interface of a memory module configures some transceivers for host connection or for upstream connection to an upstream memory module and configures other transceivers for downstream connection to a downstream memory module. In other embodiments, a multi-module memory device is formed using multiple memory modules connected in a cascade configuration or in a star configuration to provide high bandwidth memory access to all memory locations of the multiple memory modules using the given number of serial data lanes of the host connection.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

Abstract: A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.

Abstract: Ranks of one or more memory modules can have variable data widths. As part of initializing a memory architecture, a memory controller can be configured to detect the data width of the ranks in the memory architecture. Based on the detected data widths of the ranks, the memory controller can synchronize the clocks and chip select signals of multiple ranks to thereby cause one or more memory chips in each of the multiple ranks to be connected to the shared data lines at the same time.

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

Abstract: Apparatuses for supplying power to a plurality of memory core chips are described. An example apparatus includes: a substrate, an interface chip on the substrate, and a plurality of memory core chips on the interface chip coupled to the interface chip via a plurality of electrodes. The plurality of memory core chips includes a first memory core chip, a second memory core chip, and a third memory core chip disposed between the second memory core chip and the interface chip. The first memory core chip and the third memory core chip are activated for data access while the second memory core chip disposed between the first memory core chip and the third memory core chip is deactivated for data access.

Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

Abstract: Various embodiments of the present disclosure are directed towards a method for memory repair using a lookup table (LUT)-free dynamic memory allocation process. An array of memory cells having a plurality of rows and a plurality of columns is provided. Further, each memory cell of the array has multiple data states and a permanent state. One or more abnormal memory cells is/are identified in a row of the array and, in response to identifying an abnormal memory cell, the abnormal memory cell is set to the permanent state. The abnormal memory cells include failed memory cells and, in some embodiments, tail memory cells having marginal performance. During a read or write operation on the row, the one or more abnormal memory cells is/are identified by the permanent state and data is read from or written to a remainder of the memory cells while excluding the abnormal memory cell(s).

Abstract: A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.

Abstract: The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

Abstract: Disclosed herein is an apparatus that includes a first group including a plurality of first latch circuits coupled in series and a second group including a plurality of second latch circuits coupled in series. Each of the first latch circuits performs a latch operation in synchronization with a rise trigger signal. Each of the second latch circuits performs a latch operation in synchronization with a fall trigger signal. The rise and fall trigger signals are alternately activated every even clock cycles or every odd clock cycles. In response to a division ratio, first one or more of the first and second latch circuits are bypassed and second one or more of the first and second latch circuits are cyclically coupled.

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.