Possessing Thermal Dissipation Structure (i.e., Heat Sink) Patents (Class 438/122)
  • Patent number: 10684556
    Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
  • Patent number: 10680199
    Abstract: Provided are an encapsulation film, an organic electronic device including the same, and a method of manufacturing the organic electronic device using the same. Particularly, the encapsulation film, which effectively blocks moisture or oxygen entering the organic electronic device from the outside, and has excellent mechanical properties such as handleability and processability, and the organic electronic device including the same are provided.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 9, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyun Suk Kim, Hyun Jee Yoo, Jung Ok Moon, Se Woo Yang
  • Patent number: 10629689
    Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 21, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
  • Patent number: 10418291
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Patent number: 10403601
    Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 3, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Seungwon Im, Oseob Jeon, JoonSeo Son, Mankyo Jong, Olaf Zschieschang
  • Patent number: 10362685
    Abstract: A method for making an electronic assembly includes applying a protective layer including an organosulfur compound to at least a portion of a patterned conductive interconnect circuit, wherein the conductive interconnect circuit overlies at least a portion of a conductive layer on a substrate, and wherein the conductive layer includes nanowires; and engaging an electrical contact of an electronic component with the protective layer to electrically connect the electronic component and the patterned conductive layer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: July 23, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ann M. Gilman, Mikhail L. Pekurovsky, Matthew S. Stay, Shawn C. Dodds, Daniel J. Theis
  • Patent number: 10312194
    Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: General Electric Company
    Inventors: Risto Ilkka Tuominen, Arun Virupaksha Gowda
  • Patent number: 10312111
    Abstract: A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Adventive IPBank
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 10281875
    Abstract: A print head includes a platform with a face whose portion covered with a heat conductor includes a heat release section, which is deformed relative to a substantially flat portion of the face of the platform to be located at a smaller distance from the surface of the chip in a direction normal to the face at a side near to the light emission area in the longitudinal direction of the light source panel than at another side far from the light emission area. Alternatively, the heat conductor, when disconnected from the face of the platform, is thicker at a side near to the light emission area in the longitudinal direction of the light source panel than at another side far from the light emission area.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 7, 2019
    Assignee: KONICA MINOLTA, INC.
    Inventors: Hidenari Tachibe, Akira Taniyama, Takafumi Yuasa
  • Patent number: 10096566
    Abstract: A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 9, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Hata, Shintaro Araki, Takaaki Shirasawa
  • Patent number: 10021784
    Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 10, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Ping-Che Lee, Ying-Tang Chao
  • Patent number: 10002821
    Abstract: The semiconductor chip package comprises first substrate comprising insulator layer, first metallic layer, and second metallic layer; first semiconductor chip disposed on first metallic layer of first substrate; first electrically conductive spacer layer disposed on first semiconductor chip; second substrate comprising insulator layer, first metallic layer, and second metallic layer, wherein second substrate is disposed on first spacer layer; leadframe comprising first lead and second lead, wherein each one of first and second leads comprises upper surface and lower surface, wherein upper surfaces are connected with second metallic layer of second substrate, and lower surfaces are connected with first metallic layer of first substrate; and encapsulant applied to first and second substrates, first semiconductor chip, first spacer layer, and leadframe.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventor: Juergen Hoegerl
  • Patent number: 10002928
    Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 19, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
  • Patent number: 9589864
    Abstract: The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at least one cavity is created through the substrate. Sinterable paste including metal particulates and binder material is then dispensed into the at least one cavity. Next, the sinterable paste is sintered to create a sintered heat spreader, which is characterized by high thermal conductivity. The sintered heat spreader adheres to the inside walls of the at least one cavity, enhancing the overall thermal conductivity of the substrate.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 7, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Tarak A. Railkar
  • Patent number: 9516748
    Abstract: Various embodiments relate to a circuit board, including a base and a heat-conducting layer. The base has a first region and a second region on one side thereof facing the heat-conducting layer, the first region is recessed with respect to the second region, a first insulating layer is accommodated in the first region, a second insulating layer is formed on the second region, and the first insulating layer and the second insulating layer have different thermal conductivities. In addition, various embodiments further relate to an electronic module and an illuminating device including such circuit board. Various embodiments also relate to a method for manufacturing such circuit board.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 6, 2016
    Assignee: OSRAM GMBH
    Inventors: Jianghui Yang, Chuanpeng Zhong, Hao Li, Xiaomian Chen
  • Patent number: 9461238
    Abstract: Provided are a piezoelectric thin film having good piezoelectricity in which a rhombohedral structure and a tetragonal structure are mixed, and a piezoelectric element using the piezoelectric thin film. The piezoelectric thin film includes a perovskite type metal oxide, in which the perovskite type metal oxide is a mixed crystal system of at least a rhombohedral structure and a tetragonal structure, and a ratio between an a-axis lattice parameter and a c-axis lattice parameter of the tetragonal structure satisfies 1.15?c/a?1.30. The piezoelectric element includes on a substrate: the above-mentioned piezoelectric thin film; and a pair of electrodes provided in contact with the piezoelectric thin film.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 4, 2016
    Assignees: CANON KABUSHIKI KAISHA, KYOTO UNIVERSITY
    Inventors: Makoto Kubota, Kenichi Takeda, Jumpei Hayashi, Mikio Shimada, Yuichi Shimakawa, Masaki Azuma, Yoshitaka Nakamura, Masanori Kawai
  • Patent number: 9425171
    Abstract: One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the integrated circuit die to a first substrate via a first plurality of solder bump structures and bonding a second substrate to a second surface of the integrated circuit die. The technique further includes bonding the first substrate to a third substrate via a second plurality of solder bump structures and, after bonding the first substrate to the third substrate, removing the second substrate from the second surface of the integrated circuit die. The technique further includes disposing a heat sink on the second surface of the integrated circuit die.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 23, 2016
    Assignee: NVIDIA Corporation
    Inventors: Joseph Minacapelli, Teckgyu (Terry) Kang
  • Patent number: 9418912
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Patrick Nardi, Kelly P. Lofgreen
  • Patent number: 9412503
    Abstract: In an electronic component, when L0 is a dimension of an electronic component body in a first direction, L1 is a distance between a first outer electrode and a second outer electrode on a first surface in the first direction, and L2 is a dimension of each of the first and second outer electrodes on the first surface in the first direction, 0%<L1/L0<10% and 30%<L2/L0 <50% are satisfied.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: August 9, 2016
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Ota, Masato Kimura, Kota Zenzai
  • Patent number: 9379064
    Abstract: A semiconductor device is made by forming a heat spreader over a carrier. A semiconductor die is mounted over the heat spreader with a first surface oriented toward the heat spreader. A first insulating layer is formed over the semiconductor die and heat spreader. A via is formed in the first insulating layer. A first conductive layer is formed over the first insulating layer and connected to the heat spreader through the via and to contact pads on the semiconductor die. The heat spreader extends from the first surface of the semiconductor die to the via. A second insulating layer is formed over the first conductive layer. A second conductive layer is electrically connected to the first conductive layer. The carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first conductive layer.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 28, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: JiHoon Oh, SinJae Lee, JinGwan Kim
  • Patent number: 9368177
    Abstract: Provided are a magnetic resistance structure, a method of manufacturing the magnetic resistance structure, and an electronic device including the magnetic resistance structure. The method of manufacturing the magnetic resistance structure includes forming a hexagonal boron nitride layer, forming a graphene layer on the boron nitride layer, forming a first magnetic material layer between the boron nitride layer and the graphene layer according to an intercalation process; and forming a second magnetic material layer on the graphene layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: June 14, 2016
    Assignees: Samsung Electronics Co., Ltd., Sungkyunkwan University Foundation for Corporate Colaboration
    Inventors: Hwansoo Suh, Insu Jeon, Min-woo Kim, Young-jae Song, Min Wang, Qinke Wu, Sung-joo Lee, Sung-kyu Jang, Seong-jun Jung
  • Patent number: 9320149
    Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a release layer having a lower release layer surface, an upper release layer surface parallel to the lower release layer surface, and at least one release layer side, the release layer coupled with the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the release layer side and lower release layer surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: April 19, 2016
    Assignee: Intel Corporation
    Inventors: Liwen Jin, Dilan Seneviratne
  • Patent number: 9252068
    Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: February 2, 2016
    Assignee: MEDIATEK INC.
    Inventors: Tai-Yu Chen, Chung-Fa Lee, Wen-Sung Hsu, Shih-Chin Lin
  • Patent number: 9240364
    Abstract: A heat dissipation adhesive film, a semiconductor device including the same, and a method of fabricating the semiconductor device, the heat dissipation adhesive film being placeable between a protective layer encasing a semiconductor element therein and a heat dissipation metal layer on the protective layer to bond the protective layer to the heat dissipation metal layer, wherein an adhesive strength between the heat dissipation adhesive film and the protective layer and an adhesive strength between the heat dissipation adhesive film and the heat dissipation metal layer are each about 3 kgf/25 mm2 or greater.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 19, 2016
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Baek Soung Park, Jae Won Choi, In Hwan Kim, Gyu Seok Song, Su Mi Lim
  • Patent number: 9241423
    Abstract: A heat dissipation device that includes a base plate having a plurality of substantially circular channels which are substantially concentrically arranged; and a fluid distribution structure adjacent the base plate, wherein the fluid distribution structure has a plurality of inlet conduits extending substantially radially from a central area with each of the plurality of inlet conduits having at least one fluid delivery port extending through the fluid distribution structure to at least one base plate circular channel, and wherein the fluid distribution structure has a plurality of outlet zones defined between adjacent inlet conduits with each of the plurality of outlet zones having at least one fluid removal port extending through the fluid distribution structure to at least one base plate circular channel.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: January 19, 2016
    Assignee: Intel Corporation
    Inventor: Chia-Pin Chiu
  • Patent number: 9236549
    Abstract: The present invention provides a heat conducting slug having a multi-step structure, which is installed to an LED package to dissipate heat generated from a light emitting chip to the outside. The heat conducting slug includes a first slug, a second slug formed on the first slug, and a third slug formed on the second slug, wherein the light emitting chip is mounted to the third slug, and the second and third slugs respectively shaped to have edges are arranged to cross each other. In this configuration, heat generated from a light emitting chip follows a heat dissipation path, in which the heat is gathered at edges of one slug and dissipated therefrom and then gathered toward edges of another slug, arranged to cross the one slug. Accordingly, the entire heat dissipation path is not concentrated at a specific region but generally distributed widely, thereby improving a heat dissipation effect of the heat conducting slug.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: January 12, 2016
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Jong Kook Lee, Byoung Ki Pyo, Hyuck Jung Choi, Kyung Nam Kim, Won Cho
  • Patent number: 9214615
    Abstract: In accordance with certain embodiments, semiconductor dies are at least partially coated with a conductive adhesive prior to singulation and subsequently bonded to a substrate having electrical traces thereon.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Cooledge Lighting Inc.
    Inventor: Michael A. Tischler
  • Patent number: 9209330
    Abstract: A method of manufacturing a semiconductor device including a first member including a chip mounting region and a peripheral region, a semiconductor chip mounted in the chip mounting region, and a second member fixed to the first member to cover the semiconductor chip, includes adhering, to the second member, the peripheral region of the first member in a state that the semiconductor chip is mounted in the chip mounting region, using an adhesive, and generating a stress between the first member and the second member, after the adhesive starts to cure, to locally form a gap in at least one of a portion between the first member and the adhesive, and a portion between the second member and the adhesive.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: December 8, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koji Tsuduki, Yasushi Kurihara
  • Patent number: 9178261
    Abstract: In one embodiment, a vertical microcoaxial interconnect includes a dielectric substrate having a top side and a bottom side, an inner conductor extending through the substrate from its top side to its bottom side, an outer conductor that extends through the substrate from its top side to its bottom side, the outer conductor surrounding the inner conductor, a signal line extending to the inner conductor without contacting the outer conductor, and a ground line extending to the outer conductor without contacting the inner conductor or the signal line.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 3, 2015
    Assignee: University of South Florida
    Inventors: Justin Boone, Subramanian Krishnan, Shekhar Bhansali
  • Patent number: 9165716
    Abstract: A high capacitance single layer ceramic capacitor having a ceramic dielectric body containing one or more internal electrodes electrically connected to a metallization layer applied to the side and a top or bottom surface and a metallization pad electrically isolated from the metallization side and the top or bottom surface by a castellation or a via or separated by a dielectric insulating band positioned between the electrodes around the perimeter of the ceramic body and separating the top and bottom surfaces.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 20, 2015
    Assignee: Knowles Capital Formation, Inc.
    Inventors: Ali Moalemi, Euan Patrick Armstrong
  • Patent number: 9159817
    Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater, Anthony K. Stamper
  • Patent number: 9147631
    Abstract: A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: September 29, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Patent number: 9099432
    Abstract: An electronic device for power applications and configured for being mounted on a printed circuit board is disclosed. The electronic device includes a semiconductor chip integrating a power component, and a package. The package comprises an insulating body embedding the semiconductor chip, and exposed electrodes for electrically connecting conductive terminals of the semiconductor chip to external circuitry in the printed circuit board. The electronic device is further configured to be fastened to a heatsink with a back surface of the insulating body in contact with a main surface of the heatsink for removing heat produced by the electronic device during the operation thereof. The insulating body lacks of a fixing portion in which a hole for receiving an insertable fastener element for the fastening of the electronic device to the heatsink is located.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics S.r.l.
    Inventor: Agatino Minotti
  • Patent number: 9090004
    Abstract: A method for enhancing internal layer-layer thermal interface performance and a chip stack of semiconductor chips using the method. The method includes adding a thermosetting polymer to the thermal interface material, dispersing a plurality of nanofibers into the thermal interface material, and un-crosslinking the thermosetting polymer in the thermal interface material. The method further includes extruding the thermal interface material through a die to orient the conductive axis of the nanofibers and polymer chains in the desired direction, and re-crosslinking the thermosetting polymer in the thermal interface material. The chip stack includes a first chip with circuitry on a first side, a second chip coupled to the first chip by a grid of connectors, and a thermal interface material pad between the chips. The thermal interface includes nanofibers and a polymer that allows for optimal alignment of the nanofibers and polymer chains.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Joseph Kuczynski, Amanda E. Mikhail, Arden L. Moore
  • Patent number: 9070656
    Abstract: Heat spreaders for dissipating heat from semiconductor devices comprise a contact surface located within a recess on an underside of the heat spreader, the contact surface being configured to physically and thermally attach to a semiconductor device, and a trench extending into the heat spreader adjacent to the contact surface sized and configured to receive underfill material extending from the semiconductor device into the trench. Related semiconductor device assemblies may include these heat spreaders and methods may include physically and thermally attaching these heat spreaders to semiconductor devices such that underfill material extends from a semiconductor device into the trench.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Andy E. Hooper, Xiao Li, Shijian Luo
  • Patent number: 9059157
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a top insulation layer and a top conductive layer; an inter-react layer on the substrate; an integrated circuit die on the substrate; a package body on the inter-react layer and the integrated circuit die; and a top solder bump on the top conductive layer, the top solder bump in a 3D via formed through the package body, the inter-react layer, and the top insulation layer for exposing the top conductive layer in the 3D via.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 16, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim, JunMo Koo, Jose Alvin Caparas
  • Patent number: 9054118
    Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 9, 2015
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Kuang-Hsiung Chen, Sheng-Ming Wang, Yu-Ying Lee, Hsiang-Ming Feng, Bing-Yun Cheng
  • Publication number: 20150137344
    Abstract: A semiconductor device has a circuit board including an insulation layer, a wiring layer formed on one surface of the insulation layer, and a buffer layer formed on the other surface of the insulation layer, a semiconductor element bonded to the wiring layer, a radiator member bonded to the buffer layer of the circuit board, and a resin member to seal the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board. A method for manufacturing the semiconductor device includes bonding the buffer layer of the circuit board to the radiator member, bonding the semiconductor element to the wiring layer of the circuit board, and sealing the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board with resin after the two bonding steps.
    Type: Application
    Filed: November 17, 2014
    Publication date: May 21, 2015
    Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Shogo MORI, Yuri OTOBE, Shinsuke NISHI
  • Publication number: 20150140740
    Abstract: A method of fabrication, a device structure and a submount comprising high thermal conductivity (HTC) diamond on a HTC metal substrate, for thermal dissipation, are disclosed. The surface roughness of the diamond layer is controlled by depositing diamond on a sacrificial substrate, such as a polished silicon wafer, having a specific surface roughness. Following deposition of the diamond layer, an adhesion layer, e.g. comprising a refractory metal, such as tantalum, and at least one layer of HTC metal is provided. The HTC metal substrate is preferably copper or silver, and may be provided by electroforming metal onto a thin sputtered base layer, and optionally bonding another metal layer. The electrically non-conductive diamond layer has a smooth exposed surface, preferably ?10 nm RMS, suitable for patterning of contact metallization and/or bonding to a semiconductor device. Methods are also disclosed for patterning the diamond on metal substrate to facilitate dicing.
    Type: Application
    Filed: December 15, 2014
    Publication date: May 21, 2015
    Applicant: Advanced Diamond Technologies, Inc.
    Inventors: Nicolaie A. Moldovan, John A. Carlisle, Hongjun Zeng
  • Patent number: 9034695
    Abstract: A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Hsieh, Shang-Yun Hou, Shin-Puu Jeng
  • Publication number: 20150132894
    Abstract: Heat spreading substrate with embedded interconnects. In an embodiment in accordance with the present invention, an apparatus includes a metal parallelepiped comprising a plurality of wires inside the metal parallelepiped. The plurality of wires have a different grain structure than the metal parallelepiped. The plurality of wires are electrically isolated from the metal parallelepiped. The plurality of wires may be electrically isolated from one another.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Applicant: Invensas Corporation
    Inventors: Ilyas Mohammed, Masud Beroz
  • Publication number: 20150130045
    Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.
    Type: Application
    Filed: November 8, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Chun-Hao TSENG, Ying-Hao KUO, Kuo-Chung YEE
  • Publication number: 20150130036
    Abstract: In one implementation, a semiconductor package includes a patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the patterned conductive carrier. The semiconductor package further includes a heat spreading conductive plate situated over a control source of the control FET and over a sync drain of the sync FET so as to couple the control source and the sync drain to a switch node segment of the patterned conductive carrier.
    Type: Application
    Filed: October 24, 2014
    Publication date: May 14, 2015
    Inventors: Eung San Cho, Dan Clavette
  • Publication number: 20150130046
    Abstract: The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip.
    Type: Application
    Filed: October 14, 2014
    Publication date: May 14, 2015
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Publication number: 20150130047
    Abstract: A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer.
    Type: Application
    Filed: November 11, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao TSENG, Ying-Hao KUO, Kuo-Chung YEE
  • Patent number: 9029949
    Abstract: Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Patent number: 9029201
    Abstract: Embodiments of the present invention provide for the dissipation of heat from semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a thermal dissipation layer is deposited on said excavated insulator region. The thermal dissipation layer is thermally conductive and electrically insulating.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: May 12, 2015
    Assignee: Silanna Semiconductor U.S.A., Inc.
    Inventors: Paul A. Nygaard, Stuart B. Molin, Michael A. Stuber
  • Patent number: 9029202
    Abstract: A semiconductor device package (100) includes a heat spreader (503) formed by depositing a first thin film layer (301) of a first metal on a top surface (150) of a die (110) and to exposed portions of a top surface of an encapsulant (208), depositing a second thin film layer (402) of a second metal on a top surface of the first thin film layer, and depositing a third layer (503) of a third metal on a top surface of the second thin film layer.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Patent number: 9029200
    Abstract: A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallization layer is formed on the second surface of the semiconductor substrate. The metallization layer has a thickness which is greater than the device thickness.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Rudolf Zelsacher, Paul Ganitzer
  • Publication number: 20150125998
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO