Possessing Thermal Dissipation Structure (i.e., Heat Sink) Patents (Class 438/122)
  • Patent number: 11895810
    Abstract: A power electronic assembly includes a power electronic module having multiple of power electronic components and a cooling element. The cooling element is attached to a surface of the power electronic module and is arranged to transfer heat from the power electronic assembly to a cooling medium, wherein the assembly comprises multiple of vapour chambers arranged to transfer the heat generated by the multiple of power electronic components.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: February 6, 2024
    Assignee: ABB Schweiz AG
    Inventors: Jorma Manninen, Mika Silvennoinen, Joni Pakarinen
  • Patent number: 11876031
    Abstract: A semiconductor package includes at least one semiconductor device mounted on a first substrate, a thermosetting resin layer on the at least one semiconductor device, the thermosetting resin layer including an irreversible thermochromic pigment, a metal plate on the thermosetting resin layer, and a molding member surrounding the at least one semiconductor device at least in a lateral direction and being in contact with the thermosetting resin layer.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: January 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joungphil Lee, Wonkeun Kim, Mihyae Park
  • Patent number: 11830856
    Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 28, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Erik Nino Tolentino, Vemmond Jeng Hung Ng, Shutesh Krishnan
  • Patent number: 11818869
    Abstract: A heat dissipation structure assembly includes an elastic limiting member, a thermal grease wall, a fitting member, a phase-change metal, and an assembling plate. The elastic limiting member is adapted to be disposed at a periphery of a heat source. The thermal grease wall is adapted to be in contact with the periphery of the heat source. The fitting member is in contact with the thermal grease wall and engaged with the elastic limiting member. The phase-change metal is adapted to be filled into a region among the fitting member, the thermal grease wall, and the heat source. When a temperature of the phase-change metal exceeds a critical temperature, a state of the phase-change metal is changed to a liquid state. The assembling plate is connected to the fitting member, and the assembling plate is in contact with the thermal grease wall.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: November 14, 2023
    Assignees: MICRO-STAR INT'L CO., LIMITED., MSI ELECTRONIC (KUN SHAN) CO., LTD.
    Inventors: Cheng-Lung Chen, Chia-Ming Chang
  • Patent number: 11817786
    Abstract: Voltage converter inlay modules are provided for embedding within a package substrate, and are configured to supply power to a processor, or similar digital circuit, which is mounted to the package substrate. The package substrate is typically mounted to a circuit board, or similar. The circuit board provides high-voltage, low-current power to the voltage converter module which, in turn, provides low-voltage high-current power to the processor. The voltage converter inlay provides largely vertical current conduction from the circuit board to the processor, thereby reducing conduction losses incurred by lateral current conduction. The location of the voltage converter inlay between the circuit board and the microprocessor minimizes radiation of electromagnetic interference. The number of terminals allocated for providing power to the package substrate may be minimized due to the voltage converter inlay inputting fairly low levels of current.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: November 14, 2023
    Assignee: Infineon Technologies AG
    Inventor: Danny Clavette
  • Patent number: 11804452
    Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: October 31, 2023
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Nicholas A Polomoff, Jae Kyu Cho, Mohamed Rabie, Yunyao Jiang, Koushik Ramachandran, Pallabi Das
  • Patent number: 11756929
    Abstract: A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Chen-Cheng Kuo, Hung-Jui Kuo
  • Patent number: 11749575
    Abstract: A package structure is provided. The package structure includes a substrate, a cover element, a semiconductor device, a protruding element, and an adhesive element. The cover element is disposed on the substrate and having a ring portion, a space is surrounded by the ring portion, and a recess is formed on a surface of the ring portion that faces the substrate. The semiconductor device is disposed on the substrate and disposed in the space surrounded by the ring portion, wherein the semiconductor device is spaced apart from the recess by the ring portion. The protruding element extends from the substrate and disposed in the recess. The adhesive element is disposed in the recess, wherein in a top view, the semiconductor device is surrounded by the protruding element.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Ting Lin, Chin-Fu Kao, Chen-Shien Chen
  • Patent number: 11728240
    Abstract: A circuit carrier arrangement includes: a cooling plate (1) which has spacer and fastening elements (3) for connection to a printed circuit board (2) in a spaced-apart manner; a printed circuit board (2) which has bores (4) for receiving spring element sleeves (9); at least one power semiconductor component (10) which is connected by a soldered connection to the printed circuit board (2) and fastening elements (3) in the state in which it is fitted with the cooling plate (1) by means of plug-in connections (11) of spring-action configuration; and at least one spring element (5) having at least two spring element sleeves (9) between which a web (6) that is connected to the spring element sleeves (9) extends, and supporting elements (7) arranged on either side of said web and at least one spring plate (8) being arranged on said web.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: August 15, 2023
    Assignee: VITESCO TECHNOLOGIES GmbH
    Inventors: Jens Reiter, Rico Hartmann, Christian Lammel
  • Patent number: 11722112
    Abstract: A manufacturing method for an electronic component that includes a providing a base member on a first main surface of a first board, sandwiching the base member and a joining member paste between the first main surface of the first board and a transfer main surface of a transfer board, forming a joining member joined with the base member while the joining member paste is sandwiched by the first board and the transfer board, and peeling off the transfer board from the joining member joined with the base member.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 8, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shinsuke Kawamori, Masao Gamo
  • Patent number: 11721612
    Abstract: A semiconductor device A1 includes a semiconductor element 10A having an element obverse face 101 and an element reverse face 102, the element obverse face 101 having an obverse face electrode 11 formed thereon and the element reverse face 102 having a reverse face electrode 12 formed thereon, a conductive substrate 22A including an obverse face 221A opposed to the element reverse face 102, and to which the reverse face electrode 12 is conductively bonded, a conductive substrate 22B including an obverse face 221B and spaced from the conductive substrate 22A in a width direction x, and a lead member 51 extending in the width direction x, and electrically connecting the obverse face electrode 11 and the conductive substrate 22B. The lead member 51 is located ahead of the obverse face 221B in the direction in which the obverse face 221B is oriented, and bonded to the obverse face electrode 11 via a lead bonding layer 32.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: August 8, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Maiko Hatano
  • Patent number: 11710709
    Abstract: A semiconductor device includes a semiconductor chip made of a SiC substrate and having main electrodes on one surface and a rear surface, first and second heat sinks, respectively, disposed adjacent to the one surface and the rear surface, a terminal member interposed between the second heat sink and the semiconductor chip, and a plurality of bonding members disposed between the main electrodes, the first and second heat sinks, and the terminal member. The terminal member includes plural types of metal layers symmetrically layered in the plate thickness direction. The terminal member as a whole has a coefficient of linear expansion at least in a direction orthogonal to the plate thickness direction in a range larger than that of the semiconductor chip and smaller than that of the second heat sink.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: July 25, 2023
    Assignee: DENSO CORPORATION
    Inventors: Ryoichi Kaizu, Takumi Nomura, Tetsuto Yamagishi, Yuki Inaba, Yoshitsugu Sakamoto
  • Patent number: 11670627
    Abstract: Techniques disclosed herein relate generally to integrating photonic integrated circuits and electronic integrated circuits in a same package. A device includes a semiconductor substrate and a die stack on the semiconductor substrate. The die stack includes a photonic integrated circuit (PIC) die and an electronic integrated circuit (EIC) die. The PIC die includes a PIC substrate and a photonic integrated circuit formed on the PIC substrate. The EIC die includes an EIC substrate and an electronic integrated circuit formed on the EIC substrate. The EIC die and the PIC die are bonded such that the PIC substrate and the EIC substrate are disposed on opposing sides of the die stack. The PIC substrate is bonded to the semiconductor substrate. The device also includes a cooling plate bonded to the EIC substrate.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: June 6, 2023
    Assignee: Psiquantum, Corp.
    Inventors: Ramakanth Alapati, Gabriel J. Mendoza
  • Patent number: 11652030
    Abstract: Implementations of semiconductor packages may include a substrate, a first die coupled on the substrate, and a lead frame coupled over the substrate. The lead frame may include a die attach pad. Implementations of semiconductor packages may also include a second die coupled on the die attach pad. The second die may overlap the first die.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 16, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jonghwan Baek, JeongHyuk Park, Seungwon Im, Keunhyuk Lee
  • Patent number: 11652018
    Abstract: A microelectronic package may be fabricated to include a microelectronic substrate, at least one microelectronic device attached to the microelectronic substrate, a heat dissipation device in thermal contact with at least one microelectronic device and having at least one projection attached to the microelectronic substrate, and at least one standoff extending from the at least one projection, wherein the at least one standoff contacts the microelectronic substrate to control the bond line thickness between the heat dissipation device and at least one microelectronic device and/or to control the bond line thickness of a sealant which may be used to attached the at least one projection to the microelectronic substrate.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Dinesh P. R. Thanu, Hemanth K. Dhavaleswarapu, John J. Beatty, Syadwad Jain, Nachiket R. Raravikar
  • Patent number: 11616283
    Abstract: Embodiments include an electronic package that includes a radio frequency (RF) front end. In an embodiment, the RF front end may comprise a package substrate and a first die attached to a first surface of the package substrate. In an embodiment, the first die may include CMOS components. In an embodiment, the RF front end may further comprise a second die attached to the first surface of the package substrate. In an embodiment, the second die may comprise amplification circuitry. In an embodiment, the RF front end may further comprise an antenna attached to a second surface of the package substrate. In an embodiment, the second surface is opposite from the first surface.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, William J. Lambert, Xiaoqian Li, Sidharth Dalmia
  • Patent number: 11594474
    Abstract: In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: February 28, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 11508587
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; and a die embedded in the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts and the second conductive contacts are electrically coupled to conductive pathways in the package substrate.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan
  • Patent number: 11495514
    Abstract: Disclosed embodiments include multiple thermal-interface material at the interface between an integrated heat spreader and a heat sink. A primary thermal-interface material has flow qualities and a secondary thermal-interface material has containment and adhesive qualities. The integrated heat spreader has a basin form factor that contains the primary thermal-interface material.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 8, 2022
    Assignee: Intel Corporation
    Inventors: Chew Ching Lim, Chun Howe Sim
  • Patent number: 11488895
    Abstract: In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of tpress1>tcast1 and tpress2>tcast1, where tpress1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, tpress2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and tcast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: November 1, 2022
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ishino, Hirokazu Sampei
  • Patent number: 11476167
    Abstract: A front surface of a semiconductor wafer is rapidly heated by irradiation of a flash of light. Temperature of the front surface of the semiconductor wafer is measured at predetermined intervals after the irradiation of the flash of light, and is sequentially accumulated to acquire a temperature profile. From the temperature profile, an average value and a standard deviation are each calculated as a characteristic value. It is determined that the semiconductor wafer is cracked when an average value of the temperature profile deviates from the range of ±5? from a total average of temperature profiles of a plurality of semiconductor wafers or when a standard deviation of the temperature profile deviates from the range of 5? from the total average thereof of the plurality of semiconductor wafers.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: October 18, 2022
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Takahiro Kitazawa, Mao Omori, Kazuhiko Fuse
  • Patent number: 11456238
    Abstract: A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: September 27, 2022
    Assignee: DENSO CORPORATION
    Inventors: Kosuke Kamiya, Ryota Tanabe, Tomohisa Sano, Takuo Nagase, Hiroshi Ishino, Shoichiro Omae
  • Patent number: 11367671
    Abstract: An object of the invention is to improve the reliability of a power semiconductor device. The power semiconductor device according to the invention includes a semiconductor element, a first terminal and a second terminal that transmit current to the semiconductor element, a first base and a second base that are disposed to face each other while interposing a part of the first terminal, a part of the second terminal, and the semiconductor element between the first base and the second base, and a sealing material that is provided in a space between the first base and the second base. The second terminal includes an intermediate portion formed in such a way that a distance from the first terminal increases along a direction away from the semiconductor element. The intermediate portion is provided between the first base and the second base and in the sealing material.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 21, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventors: Nobutake Tsuyuno, Hiroshi Houzouji
  • Patent number: 11364496
    Abstract: An apparatus includes a polymer base layer having a surface. A die has a surface that is substantially coplanar with the surface of the polymer base layer. The die includes a fluidic actuator to control fluid flow across the surface of the die. A fluidic channel is coupled to the polymer base layer to provide a fluidic interconnect between the die and a fluidic input/output port.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 21, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Michael W. Cumbie, Viktor Shkolnikov
  • Patent number: 11328979
    Abstract: A device package and a method of forming a device package are described. The device package includes a plurality of posts disposed on a substrate. Each post has a top surface and a bottom surface that is opposite from the top surface. The device package also has one or more dies disposed on the substrate. The dies are adjacent to the plurality of posts on the substrate. The device package further includes a lid disposed above the plurality of posts and the one or more dies on the substrate. The lid has a top surface and a bottom surface that is opposite from the top surface. Lastly, an adhesive layer attaches the top surfaces of the plurality of posts and the bottom surface of the lid. The device package may also include one or more thermal interface materials (TIMs) disposed on the dies.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Feras Eid, Dinesh Padmanabhan Ramalekshmi Thanu, Sergio Chan Arguedas, Johanna M. Swan, John J. Beatty
  • Patent number: 11239134
    Abstract: A structure includes a circuit substrate, a device, a metal layer, a lid and a thermal interface material layer. The device is disposed on and electrically connected to the circuit substrate. The device includes at least one semiconductor die laterally encapsulated by an insulating encapsulation. The metal layer is covering a back surface of the at least one semiconductor die and the insulating encapsulation. The lid is disposed on the circuit substrate, and the lid is adhered to the metal layer through the thermal interface material layer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11239136
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die. The TIM is disposed on the first die, the second die, and the underfill layer. The adhesive pattern is disposed between the underfill layer and the TIM to separate the underfill layer from the TIM.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11175592
    Abstract: A method for determining an overlay metric is disclosed including obtaining angle resolved distribution spectrum data relating to a measurement of a target structure including a symmetrical component. An overlay dependent contour of a feature of the target structure is determined from the angle resolved distribution spectrum data, from which an overlay metric is determined. The method includes exposing an exposed feature onto a masked layer including a mask which defines masked and unmasked areas of the layer, such that a first portion of the exposed feature is exposed on a masked area of the layer and a second portion of the exposed feature is exposed on a non-masked area of the layer, the size of the first portion with respect to the second portion being overlay dependent; and performing an etch step to define an etched feature, the etched feature corresponding to the second portion of the exposed feature.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: November 16, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Elie Badr, Shawn Shakahwat Millat, Giacomo Miceli, Alok Verma
  • Patent number: 11127685
    Abstract: A power semiconductor module includes an insulating substrate with a top metallization layer; a semiconductor chip bonded to the top metallization layer; and a terminal welded with a foot to the top metallization layer and electrically interconnected to the semiconductor chip. At least one of the top metallization layer and a bottom metallization layer of the substrate provided opposite to the top metallization layer comprises a plurality of dimples, which are distributed in a connection region below and/or around the welded foot.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: September 21, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Milad Maleki, Fabian Fischer, Dominik Trüssel, Remi-Alain Guillemin, Daniel Schneider
  • Patent number: 11081572
    Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
  • Patent number: 11025032
    Abstract: A laser diode device includes: a first heat sink including a first mounting layer, in which the first mounting layer includes at least two mounting pads electrically isolated from one another; a second heat sink including a second mounting layer, in which the second mounting layer includes at least two mounting pads electrically isolated from one another; and a laser diode bar between the first heat sink and the second heat sink, in which a bottom electrical contact of the laser diode bar is mounted to the first mounting layer, and a top electrical contact of the laser diode bar is mounted to the second mounting layer.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: June 1, 2021
    Assignee: Trumpf Photonics, Inc.
    Inventors: Thilo Vethake, Stefan Heinemann
  • Patent number: 11004773
    Abstract: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10957622
    Abstract: A semiconductor device that includes a semiconductor substrate having a surface, the surface having several regions having different thermal and/or mechanical requirements; and a composite thermal interface material including several spatially localized thermal interface materials placed on the surface, each of the several thermal interface materials tailored to the different thermal and/or mechanical requirements of each of the regions. Also disclosed is a method of forming the composite thermal interface material.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan R. Fry, Michael Rizzolo, Tuhin Sinha
  • Patent number: 10684556
    Abstract: The present disclosure provides a method. The method includes patterning a substrate by a patterning tool; collecting a plurality of overlay errors from a plurality of fields on the substrate; identifying noise from the plurality of overlay errors by applying a first filtering operation and a second filtering operation that is different from the first filtering operation. The method further includes grouping the plurality of overlay errors that are not identified as noise into a set of filtered overlay errors; calculating an overlay compensation based on the set of filtered overlay errors; and performing a compensation process to the patterning tool according to the overlay compensation.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Weimin Hu, Yang-Hung Chang, Kai-Hsiung Chen, Chun-Ming Hu, Chih-Ming Ke
  • Patent number: 10680199
    Abstract: Provided are an encapsulation film, an organic electronic device including the same, and a method of manufacturing the organic electronic device using the same. Particularly, the encapsulation film, which effectively blocks moisture or oxygen entering the organic electronic device from the outside, and has excellent mechanical properties such as handleability and processability, and the organic electronic device including the same are provided.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 9, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Hyun Suk Kim, Hyun Jee Yoo, Jung Ok Moon, Se Woo Yang
  • Patent number: 10629689
    Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: April 21, 2020
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
  • Patent number: 10418291
    Abstract: Particular embodiments described herein provide for a silicon layer, where the silicon layer includes a profile and a thermal conductor coupled to the silicon layer, where the thermal conductor includes one or more residual stresses. The thermal conductor is modified based on the one or more residual stress such that when pressure is applied to the thermal conductor, a profile of the thermal conductor at least approximately matches the profile of the silicon layer. In an example, the thermal conductor is modified by removing material from one or more areas of the thermal conductor and the thermal conductor is coupled to the silicon layer by one or more pressure inducing mechanisms.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jerrod Peterson, David Pidwerbecki
  • Patent number: 10403601
    Abstract: Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: September 3, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Seungwon Im, Oseob Jeon, JoonSeo Son, Mankyo Jong, Olaf Zschieschang
  • Patent number: 10362685
    Abstract: A method for making an electronic assembly includes applying a protective layer including an organosulfur compound to at least a portion of a patterned conductive interconnect circuit, wherein the conductive interconnect circuit overlies at least a portion of a conductive layer on a substrate, and wherein the conductive layer includes nanowires; and engaging an electrical contact of an electronic component with the protective layer to electrically connect the electronic component and the patterned conductive layer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: July 23, 2019
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Ann M. Gilman, Mikhail L. Pekurovsky, Matthew S. Stay, Shawn C. Dodds, Daniel J. Theis
  • Patent number: 10312194
    Abstract: An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 4, 2019
    Assignee: General Electric Company
    Inventors: Risto Ilkka Tuominen, Arun Virupaksha Gowda
  • Patent number: 10312111
    Abstract: A method is disclosed of fabricating a power package which includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Adventive IPBank
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 10281875
    Abstract: A print head includes a platform with a face whose portion covered with a heat conductor includes a heat release section, which is deformed relative to a substantially flat portion of the face of the platform to be located at a smaller distance from the surface of the chip in a direction normal to the face at a side near to the light emission area in the longitudinal direction of the light source panel than at another side far from the light emission area. Alternatively, the heat conductor, when disconnected from the face of the platform, is thicker at a side near to the light emission area in the longitudinal direction of the light source panel than at another side far from the light emission area.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 7, 2019
    Assignee: KONICA MINOLTA, INC.
    Inventors: Hidenari Tachibe, Akira Taniyama, Takafumi Yuasa
  • Patent number: 10096566
    Abstract: A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: October 9, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Hata, Shintaro Araki, Takaaki Shirasawa
  • Patent number: 10021784
    Abstract: An electronic device and an electronic circuit board thereof is disclosed. In the electronic circuit board an insulation substrate is provided with conductive pads, first conductive vias, second conductive vias, third conductive vias, first conductive traces, second conductive traces, and third conductive traces. The conductive pads are arranged in two rows. Each row includes biasing pads and signal pads. The second conductive vias and the third conductive vias are respectively arranged inside and outside the first conductive vias. Each of the signal pads arranged in a row nearest the second conductive vias electrically connects with one second conductive via through a first conductive trace. Each of the signal pads arranged in a row nearest the third conductive vias electrically connects with one third conductive via through a second conductive trace. The third conductive traces embedded in the insulation substrate are extended to positions vertically under the signal pads.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 10, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Ping-Che Lee, Ying-Tang Chao
  • Patent number: 10002928
    Abstract: A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 19, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Melvin McLaurin, Alexander Sztein, Po Shan Hsu
  • Patent number: 10002821
    Abstract: The semiconductor chip package comprises first substrate comprising insulator layer, first metallic layer, and second metallic layer; first semiconductor chip disposed on first metallic layer of first substrate; first electrically conductive spacer layer disposed on first semiconductor chip; second substrate comprising insulator layer, first metallic layer, and second metallic layer, wherein second substrate is disposed on first spacer layer; leadframe comprising first lead and second lead, wherein each one of first and second leads comprises upper surface and lower surface, wherein upper surfaces are connected with second metallic layer of second substrate, and lower surfaces are connected with first metallic layer of first substrate; and encapsulant applied to first and second substrates, first semiconductor chip, first spacer layer, and leadframe.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 19, 2018
    Assignee: Infineon Technologies AG
    Inventor: Juergen Hoegerl
  • Patent number: 9589864
    Abstract: The present disclosure relates to a substrate with an embedded sintered heat spreader and a process for making the same. According to an exemplary process, at least one cavity is created through the substrate. Sinterable paste including metal particulates and binder material is then dispensed into the at least one cavity. Next, the sinterable paste is sintered to create a sintered heat spreader, which is characterized by high thermal conductivity. The sintered heat spreader adheres to the inside walls of the at least one cavity, enhancing the overall thermal conductivity of the substrate.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: March 7, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Tarak A. Railkar
  • Patent number: 9516748
    Abstract: Various embodiments relate to a circuit board, including a base and a heat-conducting layer. The base has a first region and a second region on one side thereof facing the heat-conducting layer, the first region is recessed with respect to the second region, a first insulating layer is accommodated in the first region, a second insulating layer is formed on the second region, and the first insulating layer and the second insulating layer have different thermal conductivities. In addition, various embodiments further relate to an electronic module and an illuminating device including such circuit board. Various embodiments also relate to a method for manufacturing such circuit board.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 6, 2016
    Assignee: OSRAM GMBH
    Inventors: Jianghui Yang, Chuanpeng Zhong, Hao Li, Xiaomian Chen
  • Patent number: 9461238
    Abstract: Provided are a piezoelectric thin film having good piezoelectricity in which a rhombohedral structure and a tetragonal structure are mixed, and a piezoelectric element using the piezoelectric thin film. The piezoelectric thin film includes a perovskite type metal oxide, in which the perovskite type metal oxide is a mixed crystal system of at least a rhombohedral structure and a tetragonal structure, and a ratio between an a-axis lattice parameter and a c-axis lattice parameter of the tetragonal structure satisfies 1.15?c/a?1.30. The piezoelectric element includes on a substrate: the above-mentioned piezoelectric thin film; and a pair of electrodes provided in contact with the piezoelectric thin film.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 4, 2016
    Assignees: CANON KABUSHIKI KAISHA, KYOTO UNIVERSITY
    Inventors: Makoto Kubota, Kenichi Takeda, Jumpei Hayashi, Mikio Shimada, Yuichi Shimakawa, Masaki Azuma, Yoshitaka Nakamura, Masanori Kawai
  • Patent number: 9425171
    Abstract: One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the integrated circuit die to a first substrate via a first plurality of solder bump structures and bonding a second substrate to a second surface of the integrated circuit die. The technique further includes bonding the first substrate to a third substrate via a second plurality of solder bump structures and, after bonding the first substrate to the third substrate, removing the second substrate from the second surface of the integrated circuit die. The technique further includes disposing a heat sink on the second surface of the integrated circuit die.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 23, 2016
    Assignee: NVIDIA Corporation
    Inventors: Joseph Minacapelli, Teckgyu (Terry) Kang