METHOD FOR FORMING PLATING LAYER OF PRINTED CIRCUIT BOARD

Abstract

Disclosed herein is a method for forming a plating layer of a printed circuit board. A deviation in plating thickness of a copper plating layer filled in a circuit pattern part and a through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume may be reduced. To this end, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.

Description

CROSS REFERENCE(S) TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. Section 119 of Korean Patent Application Serial No. 10-2010-0087125, entitled “Method For Forming Plating Layer Of Printed Circuit Board” filed on Sep. 6, 2010, which is hereby incorporated by reference in its entirety into this application.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a method for forming a plating layer of a printed circuit board, and more particularly, to a method for forming a plating layer of a printed circuit board in which a copper plating layer having a uniform thickness is formed in a circuit pattern part and a through-hole part of a substrate.

2. Description of the Related Art

In accordance with the trend toward a small-sized and multi-function electronic device, a printed circuit board having various functions has been demanded. Particularly, in the case of a system-in-package (SIP), excellent thermal and electrical characteristics have been demanded. In order to enhance these thermal and electrical characteristics, an attempt to change an existing hole processed as a micro via hole into a through-hole has increased. However, in the case filling-plating of the through-hole for the SIP, there are many plating limitations due to restrictions such a narrow pitch, a wide hole size, and the like. Particularly, since the plating needs to be performed at a high current density in order to fill the wide through-hole, a deviation in plating thickness between a circuit pattern part and a through-hole is increased, such that uniformity of the plating thickness is not satisfied.

A method for plating a through-hole for a SIP according to the related art will be described with reference to FIGS. 1A to 1F.

FIGS. 1A to 1F are views showing a method for plating a through-hole for a SIP according to the related art.

A through-hole for interlayer connection of a circuit is formed in a copper clad lamination (hereinafter, referred to as a ‘CCL’) 10 using a mechanical method (a computerized numerical control (CNC) method, a laser processing method, or the like) (See FIG. 1B), and a seed plating layer 20 made of a copper clad is formed on the CCL 10 using an electroless or electro plating method (See FIG. 1C). A resist 40 is stacked on the seed plating layer 20, exposed and developed (See FIG. 1D), and a copper plating layer 60 is then formed using an electro plating method (See FIG. 1E). Here, when the copper plating layer 60 is formed, it is formed to have a high current density in the through-hole 11 part, and the through-hole 11 has a narrow pitch, such that the copper layer 60 is not uniform between a circuit pattern 61 part and the through-hole 11 part.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a method capable of overcoming a difference in plating thickness and more stably performing plating by sequentially performing primary plating and secondary plating at the time of manufacturing of a printed circuit board.

According to an exemplary embodiment of the present invention, there is provided a method for forming a plating layer of a printed circuit board, the method including: processing a though-hole in a copper clad lamination (CCL); forming a seed plating layer in the through hole; applying a resist on the CCL and the seed plating layer and exposing and developing the resist; forming a primary plating layer on the seed plating layer; forming a copper plating layer on the primary plating layer; and removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.

The through-hole may be formed by a mechanical method and a chemical method.

The mechanical method may be a drill and laser processing method, and the chemical method may be an etching method.

The primary plating layer may have a thickness of 3 to 5 μm.

The primary plating layer may be plated with a low current having a current density of 0.5 A/dm² to 1.0 A/dm² or less.

The copper plating layer may be formed on the primary plating layer so as to have a thickness of 20 to 25 μm.

The copper plating layer may be plated with a high current having a current density of 1.5 A/dm² to 2.0 A/dm² or more.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing a method for plating a copper clad lamination (CCL) including a through-hole according to the related art;

FIGS. 2A and 2B are comparison views of copper plating layers between a via hole and a through-hole;

FIGS. 3A to 3G are flow charts showing a process for forming a copper plating layer including a through-hole according to an exemplary embodiment of the present invention;

FIG. 4 is a graph comparing a plating method according to the related art and a plating method according to an exemplary embodiment of the present invention with each other; and

FIG. 5 is an enlarged view comparing a copper plating layer formed by a plating method according to the related art and a copper plating layer formed by a plating method according to an exemplary embodiment of the present invention with each other.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The acting effects and technical configuration with respect to the objects of a method for forming a plating layer of a printed circuit board according to the present invention will be clearly understood by the following description in which exemplary embodiments of the present invention are described with reference to the accompanying drawings.

However, the present invention may be modified in many different forms and it should not be limited to the embodiments set forth herein. Rather, these embodiments may be provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

Referring to FIGS. 2A and 2B, when a via hole 12 is formed in a copper clad lamination (CCL) 10 as shown in FIG. 2A, a resin residual remains in a lower surface of the via hole 12 due to a difference in diameter between upper and lower surfaces of the via hole 12, such that reliability is deteriorated. On the other hand, when a through-hole 11 is formed in the CCL 10, a problem that resin residual remains in an inner side of the through-hole 11 is not generated. Therefore, a structure in which the through-hole 11 is formed in the CCL 10 has been used in a printed circuit board in accordance with the trend toward a small-sized and multi-function electronic device.

A method for forming a plating layer of a printed circuit board according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

A method for forming a plating layer of a printed circuit board according to an exemplary embodiment of the present invention is configured to include processing a though-hole 11 in a copper clad lamination (CCL) 10, forming a seed plating layer 20 on the CCL 10 and in the through-hole 11, applying a resist 40 on the seed plating layer 20, exposing and developing the resist 40, forming a primary plating layer 50 on the seed plating layer 20, forming a copper plating layer 60 on the primary plating layer 50, and removing the resist 40 remaining on the primary plating layer 50 and the seed plating layer 20.

Here, the copper clad lamination (hereinafter, referred to as the ‘CCL’) 10 may include a copper clad layer having a thickness of 2 to 3 μm, wherein the copper clad layer is made of epoxy or modified epoxy, polyimide, polyethylene terephthalate (PET), cyanide ester, or the like.

As a method for forming the through-hole 11 in the CCL 10, a drill, a laser, or the like, which are a mechanical processing method, may be used. In addition, the through-hole 11 may also be formed by a chemical etching method. However, the present invention is not limited thereto. The through-hole 11 may also be formed by several methods (See FIG. 3A).

As a method for forming the seed plating layer 20 on the CCL 10 and in the through-hole 11, an electroless and electro plating method may be used. However, the present invention is not limited thereto. The seed plating layer 20 may also be formed by several methods.

In the applying of the resist 40 on the seed plating layer 20, several kinds of resists may be used. However, a dry film, which is most generally used as the resist, is applied on the seed plating layer 20 (See FIG. 3B).

In order to form circuit patterns 61 in a state in which the resist 40 is applied on the seed plating layer 20, the resist 40 is exposed using a mask 30. Unlike a subtractive method, in the case of the exposure, portions except for portions in which the circuit patterns 61 are formed are exposed to light. The portions exposed to the light are polymerized (See FIG. 3C).

In a development process, the portions of the resist 40 exposed to the light are dissolved and removed by a development solution (sodium carbonate) (See FIG. 3D).

In the forming of the primary plating layer 50 on the seed plating layer 20, the primary plating layer 50 having 3 to 5 μm is formed by applying a low current having a current density of 0.5 A/dm² to 1.0 A/dm² to the CCL 10 on which the seed plating layer 50 is formed. The primary plating layer 50 is formed, thereby making it possible to reduce a difference in thickness of the copper plating layer between the circuit pattern 61 part and the through-hole 11 part (See FIG. 3E).

In the forming of the copper plating layer 60 on the primary copper plating layer 50, the copper plating layer 60 having 25 μm is formed by applying a high current having a current density of 1.5 A/dm² to 2.0 A/dm² to the CCL 10 on which the primary plating layer 50 having the thickness of 3 to 5 μm is formed by applying the low current thereto (See FIG. 3F).

Since the primary plating layer 50 is secured in the through-hole 11 by the low current, a speed at which the copper plating layer 60 is filled in the through-hole 11 is more rapid in comparison with the circuit pattern 61, such that the plating in an area in the vicinity of the through-hole 11 is formed to be relatively lower as compared with an existing plating method. Therefore, a step of the copper plating layer 60 between the circuit pattern 61 part and the through-hole 11 is reduced.

In the removing of the resist 40 remaining on the primary plating layer 50 and the seed plating layer 20, the resist 40 is removed using a sodium hydroxide solution.

The resist 40 remaining on the primary plating layer 50 and the seed layer 20 are removed using an etching solution. As the etching solution, a copper chloride solution, an iron chloride solution, or an agent such as sulfuric acid, peroxosulfuric acid is mainly used (See FIG. 3G).

FIGS. 4 and 5 are comparison views between a plating method according to the related art and a plating method according to an exemplary embodiment of the present invention.

FIG. 4 is a graph comparing a plating method according to the related art and a plating method according to an exemplary embodiment of the present invention with each other.

FIG. 4 shows a thickness of the copper plating layer 60 when a maximum step of the copper plating layer 60 between the circuit pattern 61 and the through-hole 11 is 10 μm or less. In the case of the plating method according to the related art, the copper plating layer 60 has an average thickness of about 40 μm. On the other hand, in the case of the plating method according to the exemplary embodiment of the present invention, the copper plating layer 60 may have an average thickness of about 34 μm. As a result, even though a thickness of the copper plating layer 60 is reduced by about 5 μm, the copper plating layer 60 may be formed.

FIG. 5 is an enlarged view comparing a copper plating layer formed by a plating method according to the related art and a copper plating layer formed by a plating method according to an exemplary embodiment of the present invention with each other.

In the case of the plating method according to the related art, the copper plating layer 60 is plated to have a high height in an area in the vicinity of the through-hole 11 at the time of formation of the copper plating layer 60. This phenomenon is further intensified when the copper plating layer 60 is formed by applying a current having a high current density in the through-hole 11 having a narrow pitch. On the other hand, in the case of the plating method according to the exemplary embodiment of the present invention, it may be appreciated that the copper plating layer 60 does not have a high height in an area in the vicinity of the through-hole 11.

With the method for forming a plating layer of a printed circuit board according to the embodiment of the present invention, primary plating and secondary plating are performed, thereby making it possible to reduce a deviation in plating thickness of the copper plating layer filled in the circuit pattern part and the through-hole part in a SIP product group having a narrow through-hole pitch and a large through-hole volume.

Hereinabove, although the method for forming a plating layer of a printed circuit according to the present invention has been described with reference to the exemplary embodiment, it is obvious to those skilled in the art that various modifications, alterations, and changes may be made without departing from the spirit of the present invention.

Claims

1. A method for forming a plating layer of a printed circuit board, the method comprising:

processing a though-hole in a copper clad lamination (CCL);

forming a seed plating layer in the through hole;

applying a resist on the CCL and the seed plating layer and exposing and developing the resist;

forming a primary plating layer on the seed plating layer;

forming a copper plating layer on the primary plating layer; and

removing the resist remaining on the primary plating layer and the seed plating layer to thereby form patterns.

2. The method according to claim 1, wherein the through-hole is formed by a mechanical method and a chemical method.

3. The method according to claim 2, wherein the mechanical method is a drill and laser processing method, and the chemical method is an etching method.

4. The method according to claim 1, wherein the primary plating layer has a thickness of 3 to 5 μm.

5. The method according to claim 4, wherein the primary plating layer is plated with a low current having a current density of 0.5 A/dm2 to 1.0 A/dm2 or less.

6. The method according to claim 1, wherein the copper plating layer is formed on the primary plating layer so as to have a thickness of 20 to 25 μm.

7. The method according to claim 6, wherein the copper plating layer is plated with a high current having a current density of 1.5 A/dm2 to 2.0 A/dm2 or more.