TEST MASK SET AND MASK SET

Abstract

A test mask set includes a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns. The gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width. The active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width

Description

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2010-0128460, filed on Dec. 15, 2010, in the Korean Intellectual Property Office, and entitled: “Test Mask Set and Mask Set,” is incorporated by reference herein in its entirety.

BACKGROUND

1. Field

The present embodiments relate to a test mask set and a mask set.

2. Description of the Related Art

A semiconductor device can be manufactured by a patterning process using photolithography. In the photolithography, it may be desirable to control the pattern dimension because a slight change in the pattern dimension may greatly affect the performance of a semiconductor device. It also may be desirable to establish the design rule for the pattern dimension to allow the semiconductor device to demonstrate performance as desired.

SUMMARY

According to an embodiment, there is provided a test mask set including a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns, and a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns, wherein the gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width, and the active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width.

The gate pattern areas may be disposed in parallel with each other in a first direction. The active pattern areas may be disposed in parallel with each other in a second direction.

The first direction and the second direction may be perpendicular to each other.

The plurality of gate pattern areas and the plurality of active pattern areas may be disposed to overlap each other in a grid configuration.

The gate width may be in a range of about 0.03 μm to about 10 μm.

The active width may be in a range of about 0.06 μm to about 10 μm.

The gate patterns may be configured to form a gate electrode using a CMP process.

The gate patterns may be configured to define an area where the gate electrode is to be formed by etching an interlayer dielectric film.

Densities of the gate patterns formed in different gate pattern areas may differ from each other.

The test mask set may further include a third test mask having an area with a booster and an area without a booster.

According to an embodiment, there is provided a test mask set including a first test mask having a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern formed therein, the first gate pattern having a first gate spacing and a first gate width, the second gate pattern having the first gate spacing and a second gate width, the second gate width being different from the first gate width, the third gate pattern having a second gate spacing, the second gate spacing being different from the first gate spacing, and the first gate width, and the fourth gate pattern having the second gate spacing and the second gate width, and a second test mask having a first active pattern, a second active pattern, a third active pattern and a fourth active pattern formed therein, the first active pattern having a first active spacing and a first active width, the second active pattern having the first active spacing and a second active width, the second active width being different from the first active width, the third active pattern having a second active spacing, the second active spacing being different from the first active spacing, and the first active width, and the fourth active pattern having the second active spacing and the second active width.

The first to fourth gate patterns and the first to fourth active patterns may be disposed to overlap each other in a grid configuration.

The test mask set may further include a third test mask having an area with a booster disposed therein and an area without a booster.

According to an embodiment, there is provided a mask set including a first mask having a first pattern area and a first test area disposed therein, and a second mask having a second pattern area and a second test area disposed therein. The first test area may have a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns formed therein, the gate patterns formed in different areas among the plurality of gate pattern areas differing in at least one of a gate spacing or a gate width. The second test area may have a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns formed therein, the active patterns formed in different areas among the plurality of active pattern areas differing in at least one of an active spacing or an active width.

The gate pattern areas may be disposed in parallel with each other in a first direction. The active pattern areas may be disposed in parallel with each other in a second direction.

The first direction and the second direction may be perpendicular to each other.

The plurality of gate pattern areas and the plurality of active pattern areas may be disposed to overlap each other in a grid configuration.

The gate patterns may be configured to form a gate electrode using a CMP process.

Densities of the gate patterns formed in different gate pattern areas may differ from each other.

The mask set may further include a third test mask having an area with a booster and an area without a booster.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:

FIG. 1 illustrates a perspective view of a test mask set according to an embodiment;

FIG. 2 illustrates a cross-sectional view of a semiconductor device manufactured using the test mask set shown in FIG. 1;

FIGS. 3 and 4 illustrate pattern dimensions determined by the test mask set shown in FIG. 1;

FIG. 5 illustrates a plan view depicting the test mask sets shown in FIG. 1 being disposed to overlap each other;

FIGS. 6 and 7 illustrate variations in the pattern dimensions determined by the test mask set shown in FIG. 1;

FIG. 8 illustrates a perspective view of a test mask set according to another embodiment;

FIG. 9 illustrates a view depicting pattern dimensions determined by the test mask set shown in FIG. 8;

FIG. 10 illustrates a plan view depicting test mask sets each shown in FIG. 8 are disposed to overlap each other;

FIG. 11 illustrates a perspective view of a mask set according to an embodiment; and

FIG. 12 illustrates a perspective view of a mask set according to another embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. Like reference numerals refer to like elements throughout.

Unless otherwise defined, all terms (including technical and scientific terms) used herein may have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, a test mask set according to an embodiment will be described with reference to FIGS. 1 to 7. FIG. 1 is a perspective view of a test mask set according to an embodiment, FIG. 2 is a cross-sectional view of a semiconductor device manufactured using the test mask set shown in FIG. 1, FIGS. 3 and 4 are views illustrating pattern dimensions determined by the test mask set shown in FIG. 1, FIG. 5 is a plan view illustrating test mask sets shown in FIG. 1 being disposed to overlap each other, and FIGS. 6 and 7 are views illustrating a variation in the pattern dimensions determined by the test mask set shown in FIG. 1.

Referring first to FIG. 1, the test mask set may include a first test mask 100 having a plurality of gate pattern areas a1 to a4 disposed therein, and a second test mask 200 having a plurality of active pattern areas b1 to b4 disposed therein.

As shown in FIG. 1, the plurality of gate pattern areas a1 to a4 may be disposed in the first test mask 100, and each of the gate pattern areas a1 to a4 may have one or more gate patterns (not shown). The gate patterns may be used to form a gate electrode 97 of a semiconductor device (for example, a transistor) shown in FIG. 2, which will be described below in more detail.

In addition, as shown in FIG. 1, the plurality of active pattern areas b1 to b4 may be disposed in the first test mask 100, and each of the active pattern areas b1 to b4 may have one or more active patterns (not shown). The active patterns may be used to form an active area 20 of the semiconductor device (for example, a transistor) shown in FIG. 2, which will be described below in more detail.

The plurality of gate pattern areas a1 to a4 disposed in the first test mask 100 may be disposed in parallel with each other in a first direction (e.g., in a transverse direction), as shown in FIG. 1, and the plurality of active pattern areas b1 to b4 may be disposed in parallel with each other in a second direction (e.g., in a longitudinal direction). The first direction (e.g., the transverse direction) and the second direction (e.g., the longitudinal direction) may be perpendicular to each other. The first test mask 100 and the second test mask 200 may overlap with each other such that the plurality of gate pattern areas a1 to a4 and the plurality of active pattern areas b1 to b4 overlap each other. In the test mask set according to the illustrated embodiment, by overlapping the first test mask 100 and the second test mask 200, the plurality of gate pattern areas a1 to a4 and the plurality of active pattern areas b1 to b4 may be disposed to overlap each other in a grid configuration, as shown in FIG. 5.

Although FIG. 1 illustrates that the plurality of gate pattern areas a1 to a4 disposed in the first test mask 100 are parallel with each other in the first direction (e.g., in the transverse direction), and the plurality of active pattern areas b1 to b4 disposed in the second test mask 200 are parallel with each other in the second direction (e.g., in the longitudinal direction), the disposition may vary from the disposition illustrated in FIG. 1. As described above, when the first test mask 100 and the second test mask 200 are disposed to overlap each other, a disposition varying from than that illustrated in FIG. 1 may be used, as long as the gate pattern areas a1 to a4 and the active pattern areas b1 to b4 are all disposed to be overlap each other.

As mentioned above, the active pattern (not shown) formed in each of the active pattern areas b1 to b4 disposed in the second test mask 200 may be used to form the active area 20 of the semiconductor device (for example, a transistor) shown in FIG. 2. In detail, referring to FIGS. 1 and 3, the active pattern (not shown) formed in each of the active pattern areas b1 to b4 may have intrinsic active spacing AS and an intrinsic active width AW. The active patterns formed in different active pattern areas b1 to b4 may be different in view of at least one of the active spacing AS and active width AW.

For example, an active pattern (not shown) having a relatively small active spacing AS and a relatively small active width AW may be formed in a first active pattern area b1, an active pattern (not shown) having a relatively large active spacing AS and a relatively small active width AW may be formed in a second active pattern area b2, an active pattern (not shown) having a relatively small active spacing AS and a relatively large active width AW may be formed in a third active pattern area b3, and an active pattern (not shown) having a relatively large active spacing AS and a relatively large active width AW may be formed in a fourth active pattern area b4. Active pitches AP corresponding to a sum of the active spacing AS and the active width AW may be the same as or different from each other.

When the active area 20 and a device isolation area 30 are defined and formed on a semiconductor substrate 10 using the second test mask 200, it is possible to form the active area 20 having various active widths AW and the device isolation area 30 having various active spacings AS for each of the active pattern areas b1 to b4. In the illustrated embodiment, the active widths AW may vary in a range of about 0.06 μm to about 10 μm.

Likewise, as stated above, the gate patterns (not shown) may be used to form the gate electrode 97 of the semiconductor device (for example, a transistor) shown in FIG. 2. In detail, referring to FIGS. 1 and 4, the gate pattern (not shown) formed in each of the gate pattern areas a1 to a4 may have intrinsic gate spacing GS and an intrinsic gate width GW. The gate patterns formed in different gate pattern areas a1 to a4 may be different in view of at least one of the gate spacing GS and gate width GW.

For example, a gate pattern (not shown) having a relatively small gate spacing GS and a relatively small gate width GW may be formed in a first gate pattern area a1, a gate pattern (not shown) having a relatively large gate spacing GS and a relatively small gate width GW may be formed in a second gate pattern area a2, a gate pattern (not shown) having a relatively small gate spacing GS and a relatively large gate width GW may be formed in a third gate pattern area a3, and a gate pattern (not shown) having a relatively large gate spacing GS and a relatively large gate width GW may be formed in a fourth gate pattern area a4. Gate pitches GP corresponding to a sum of the gate spacing GS and the gate width GW may be the same as or different from each other, like the active pitches AP.

The forming of the gate electrode (97 of FIG. 2) on the semiconductor substrate 10 using the first test mask 100 will now be described in more detail, As shown in FIG. 4, a dummy gate (40 of FIG. 9) of the semiconductor substrate 10, having an interlayer dielectric film 80 deposited thereon, and the interlayer dielectric film 80 may be etched using the first test mask 100 to form an etching portion 90, thereby defining a potential area where a gate electrode is to be formed. Thus, when the etching portion 90 is formed using the first test mask 100, it may be possible to form the etching portion 90 having various gate spacings GS and various gate widths GW for each of the gate pattern areas a1 to a4. Additionally, in order to complete the gate electrode 97, a gate insulation film (95 of FIG. 2), may be formed in an area where the thus defined gate electrode is to be formed, that is, in the etching portion 90, and a conductive material (not shown) may be coated on the etching portion 90 having the gate insulation film 95 and the interlayer dielectric film 80, followed by planarizing using a chemical mechanical polishing (CMP) process, thereby completing the gate electrode 97 shown in FIG. 2. The gate pattern (not shown) disposed in the first test mask 100 may be used to form the gate electrode 97 using a damascene process.

As described above, it is possible to form the etching portion 90 having various gate spacings GS and various gate widths GW for each of the gate pattern areas a1 to a4 when the area where the gate electrode 97 is to be formed, that is, the etching portion 90, is formed on the semiconductor substrate 10 using the first test mask 100. Thereby, the gate electrode having various gate spacings GS and various gate widths GW may be formed. In the illustrated embodiment, the gate widths GW may vary in a range of, for example, about 0.03 μm to about 10 μm.

The forming of the active area 20 and the device isolation area 30 on the semiconductor substrate 10 by overlapping the first test mask 100 and the second test mask 200 and the forming of the gate electrode 97 will now be described.

When the first test mask 100 and the second test mask 200 are overlapped with each other, the plurality of gate pattern areas a1 to a4 and the plurality of active pattern areas b1 to b4 may be disposed to overlap each other in a grid configuration, as shown in FIG. 5. In the semiconductor device (e.g., a transistor) defined by a 1-1 area (a1, b1), the active area 20 may have a relatively small active spacing AS and a relatively small active width AW, and the gate electrode 97 may have a relatively small gate spacing GS and a relatively small gate width GW. In the semiconductor device (e.g., a transistor) defined by a 4-4 area (a4, b4), the active area 20 may have a relatively large active spacing AS and a relatively large active width AW, and the gate electrode 97 may have a relatively large gate spacing GS and a relatively large gate width GW. When a semiconductor device (e.g., a transistor shown in FIG. 2) is formed by overlapping the first test mask 100 and the second test mask 200 with each other, the formed semiconductor device may have various active spacings AS, various active widths AW, various gate spacings GS and various gate widths GW.

In the thus formed semiconductor device having various active spacings AS, various active widths AW, various gate spacings GS and various gate widths GW, the gate electrode (97 of FIG. 2) may have different heights for the following reason.

First, a manufacturing process of a semiconductor device that may be manufactured using the test mask set according an embodiment, for example, a transistor, will be described with reference to FIGS. 2 to 4 and FIG. 9.

Referring to FIG. 2, the active area 20 and the device isolation area 30 may be formed on the semiconductor substrate 10 using the second test mask 200. For example, a predetermined area of the semiconductor substrate 10 may be etched to form the device isolation area 30, and the device isolation area 30 is then filled with a filled oxide film (not shown) to define the active area 20 and the device isolation area 30.

Next, a dummy gate (40 of FIG. 9) may be formed on the active area 20, and an upper portion of the active area 20 without a dummy gate may be etched. Then, a functional layer 50, a source 60 and a drain 70 may be formed using an ion implantation process and an epitaxial growth process. The functional layer 50, the source 60 and the drain 70, which will r be described below, may serve as boosters for the semiconductor device (e.g., a transistor). For example, the functional layer 50 may be an eSiGe layer, and the source 60 and the drain 70 may be an elevated source 60 and an elevated drain 70.

Next, the interlayer dielectric film 80 may be formed on the semiconductor substrate 10 having the dummy gate (40 of FIG. 9) and the boosters 50, 60 and 70. Then, the interlayer dielectric film 80 may be planarized using a CMP process until the dummy gate 40 is exposed. When the dummy gate 40 is exposed, the interlayer dielectric film 80 in the area where the gate electrode 97 is to be formed and the dummy gate 40 may be etched using the first test mask 100 to form the etching portion 90, as shown in FIG. 4. As described above, a conductive material may be formed on the etching portion 90 having the gate insulation film 95 and the interlayer dielectric film 80 and then may be planarized using a CMP process, thereby completing the gate electrode 97 shown in FIG. 2.

Referring to FIG. 3, a field oxide film (not shown) may generally be formed in the device isolation area 30. Accordingly, a step difference between the field oxide film formed in the device isolation area 30 and the semiconductor substrate 10 forming the active area 20 may vary according to the active spacing AS and the active width AW. As described above, the step difference may affect the planarized amount of the interlayer dielectric film 80 in the CMP process for forming the gate electrode 97, thereby making heights of the gate electrode 97 different according to variations in the active spacing AS and the active width AW.

Referring to FIG. 4, the gate spacing GS and the gate width GW may also affect the planarized amount of the interlayer dielectric film 80 in the CMP process for forming the gate electrode 97. Accordingly, heights of the gate electrode 97 may be made different according to variations in the active spacing AS and the active width AW.

Therefore, as shown in FIG. 5, a semiconductor device, for example, a transistor shown in FIG. 2, having the gate electrode 97 having various heights may be manufactured by overlapping the first test mask 100 and the second test mask 200 with each other. The heights of the gate electrode 97 affect the performance of a semiconductor device, for example, a transistor. Accordingly, it is desirable to control variations in the pattern dimension determining the heights of the gate electrode 97, including an active spacing AS, an active width AW, a gate spacing GW, a gate width GW, and so on, and it is desirable to establish the design rule.

If the processing parameters, including the active spacing AS, the active width AW, the gate spacing GS and the gate width GW, are varied by each predetermined amount, as shown in FIG. 6, by the first to fourth gate pattern areas a1 to a4 of the first test mask 100 and the first to fourth active pattern areas b1 to b4 of the second test mask 200, it may be possible to analyze the effects that the processing parameters exert on the overall process. In addition, it may be possible to analyze effects that the processing parameters, including the height of a gate electrode, exert on the performance of a semiconductor device (e.g., a transistor). Accordingly, it may be possible to control the processing parameters for a semiconductor device (e.g., a transistor) to demonstrate the maximum performance while maintaining appropriate processing conditions. In addition, ideal design rules may be easily established by forming the semiconductor device in various manners by overlapping the first test mask 100 and the second test mask 200 with each other.

Although FIG. 6 illustrates that the processing parameters may varied in predetermined amounts, the embodiments other than the illustrated example may be used. If desired, the processing parameters can be varied randomly. As shown in FIG. 7, which depicts a test mask set according to a modified embodiment, variations of the processing parameters may be adjusted by randomized amounts in an intended manner. In a case where the processing parameters are varied by random amounts, a semiconductor device (e.g., a transistor) can be manufactured under various processing conditions and a change in the performance of the semiconductor device can be checked accordingly.

Although the embodiments have been described above with regard to the processing parameters, including the active spacing AS, the active width AW, the gate spacing GS and the gate width GW by way of example, it is also possible to analyze and control the other processing parameters and the relationships between processing conditions, including a planarized amount in a CMP process) and the performance of a semiconductor device (e.g., a transistor). For example, referring to FIG. 5, since a 1-1 area (a1, b1) has a relatively small gate width GW and a relatively small active width AW, the gate pattern density thereof may be greater than that of a 4-4 area (a4, b4) having a relatively large gate width GW and a relatively large active width AW. Since various areas shown in FIG. 5 may have different gate pattern densities, the gate pattern density and the relationship between the processing conditions, including a planarized amount in a CMP process) and the performance of a semiconductor device (e.g., a transistor) may also be analyzed and controlled, thereby ultimately establishing the design rule for the semiconductor device to demonstrate the performance as desired.

Finally, although FIG. 1 illustrates the first test mask 100 having the first to fourth gate pattern areas a1 to a4 disposed therein and the second test mask 200 having the first to fourth active pattern areas b1 to b4 disposed therein, the numbers of the gate pattern areas and the active pattern areas may be varied from what is illustrated in FIG. 1, as desired.

Hereinafter, a test mask set according to another embodiment will be described with reference to FIGS. 8 to 10.

FIG. 8 is a perspective view of a test mask set according to another embodiment,

FIG. 9 is a view illustrating pattern dimensions determined by the test mask set shown in FIG. 8, and FIG. 10 is a plan view illustrating the test mask sets shown in FIG. 8 being disposed to overlap each other.

Descriptions relating to the test mask set according to the previous embodiment will not be repeated below and the following description will focus on differences.

Referring to FIG. 8, the test mask set may further include a third test mask 300 having an area c1 with a booster, and an area c2 without a booster. The areas c1 and c2 may be referred to as a booster area and a non-booster area, respectively, for brevity.

Referring to FIG. 10 together with FIG. 8, as described above, the booster area c1 may be an area where boosters, including the functional layer 50, such as an eSiGe layer, and the source 60 and the drain 70, which are elevated, are formed. The non-booster area c2 may be an area where the boosters are not formed.

If the first to third test masks 100, 200 and 300 are overlapped with each other, as shown in FIG. 10, in addition to the above-described processing parameters, it also may be possible to analyze and control the relationship between the processing conditions, including, for example, a planarized amount in a CMP process, depending on the presence of additionally formed boosters, and the performance of a semiconductor device (e.g., a transistor), including, for example, heights of a gate electrode. Accordingly, it may be possible to establish the design rule for the semiconductor to demonstrate the performance as desired, a detailed description of which can be fully deduced from the description of the test mask set according to the previous embodiment, and will not be repeated here.

Hereinafter, a mask set according to an embodiment, and a mask set according to another embodiment will be described with reference to FIGS. 11 and 12.

FIG. 11 is a perspective view of a mask set according to an embodiment, and FIG. 12 is a perspective view of a mask set according to another embodiment.

Referring to FIG. 11, the mask set according to an embodiment may include a first mask 500 having a first pattern area P1 and a first test area T1 disposed therein, and a second mask 600 having a second pattern area P2 and a second test area T2 disposed therein.

A pattern for forming a semiconductor device (e.g., a transistor) may be formed on a semiconductor substrate (10 of FIG. 2) in the first and second pattern areas P1 and P2, and various test patterns that have been described above in the test mask set according to the previous embodiment may be formed in the first and second test areas T1 and T2. For example, a plurality of gate pattern areas (a1 to a4 of FIG. 1) may be disposed in the first test area T1, and one or more gate patterns (not shown) formed in different areas among the respective gate pattern areas a1 to a4 may be differ in at least one of a gate spacing or a gate width. A plurality of active pattern areas (b1 to b4 of FIG. 1) may be disposed in the second test area T2, and one or more active patterns (not shown) formed in different areas among the respective active pattern areas b1 to b4 may be different in view of at least one of an active spacing or an active width.

In such a manner, various test patterns may be formed on a predetermined area of the semiconductor substrate (10 of FIG. 2) and analyzed using the first and second test areas T1 and T2 of the first and second masks 500 and 600, thereby allowing the state of a semiconductor device (e.g., a transistor) as manufactured using the first and second pattern areas P1 and P2 to be checked.

Referring to FIG. 12, the mask set according to another embodiment may further include a third mask 700 having a third pattern area P3 and a third test area T3 disposed therein.

As in the previous embodiment, a pattern for forming a semiconductor device (e.g., a transistor) may be formed on a semiconductor substrate (10 of FIG. 2) in the third pattern area P3. A booster area (c1 of FIG. 8) and a non-booster area (c2 of FIG. 8) may be disposed in the third test area T3.

Various test patterns that have been described above in the test mask set according to the previous embodiment can be formed in a predetermined area of the semiconductor substrate 10 formed and analyzed using the third test area T3, thereby allowing the state of a semiconductor device (e.g., a transistor) as manufactured using the first to third pattern areas P1, P2 and P3 to be checked.

By way of summation and review, embodiments disclosed herein provide a test mask set such that variations between various processing parameters including a pattern dimension in the manufacture of a semiconductor device may be controlled and such that the design rule may be easily established.

The present embodiments also provide a mask set such that variations between various processing parameters including a pattern dimension in the manufacture of a semiconductor device may be controlled and such that the design rule may be easily established.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.

Claims

1. A test mask set comprising:

a first test mask having a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns; and

a second test mask having a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns,

wherein the gate patterns formed in different areas among the plurality of gate pattern areas differ in at least one of a gate spacing or a gate width, and

the active patterns formed in different areas among the plurality of active pattern areas differ in at least one of an active spacing or an active width.

2. The test mask set as claimed in claim 1, wherein:

the gate pattern areas are disposed in parallel with each other in a first direction, and

the active pattern areas are disposed in parallel with each other in a second direction.

3. The test mask set as claimed in claim 2, wherein the first direction and the second direction are perpendicular to each other.

4. The test mask set as claimed in claim 2, wherein the plurality of gate pattern areas and the plurality of active pattern areas are disposed to overlap each other in a grid configuration.

5. The test mask set as claimed in claim 1, wherein the gate width is in a range of about 0.03 μm to about 10 μm.

6. The test mask set as claimed in claim 5, wherein the active width is in a range of about 0.06 μm to about 10 μm.

7. The test mask set as claimed in claim 1, wherein the gate patterns are configured to form a gate electrode using a CMP process.

8. The test mask set as claimed in claim 7, wherein the gate patterns are configured to define an area where the gate electrode is to be formed by etching an interlayer dielectric film.

9. The test mask set as claimed in claim 1, wherein densities of the gate patterns formed in different gate pattern areas differ from each other.

10. The test mask set as claimed in claim 1, further comprising a third test mask having an area with a booster disposed therein and an area without a booster.

11. A test mask set comprising:

a first test mask having a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern formed therein, the first gate pattern having a first gate spacing and a first gate width, the second gate pattern having the first gate spacing and a second gate width, the second gate width being different from the first gate width, the third gate pattern having a second gate spacing, the second gate spacing being different from the first gate spacing, and the first gate width, and the fourth gate pattern having the second gate spacing and the second gate width; and

a second test mask having a first active pattern, a second active pattern, a third active pattern and a fourth active pattern formed therein, the first active pattern having a first active spacing and a first active width, the second active pattern having the first active spacing and a second active width, the second active width being different from the first active width, the third active pattern having a second active spacing, the second active spacing being different from the first active spacing, and the first active width, and the fourth active pattern having the second active spacing and the second active width.

12. The test mask set as claimed in claim 11, wherein the first to fourth gate patterns and the first to fourth active patterns are disposed to overlap each other in a grid configuration.

13. The test mask set as claimed in claim 11, further comprising a third test mask having an area with a booster and an area without a booster.

14. A mask set comprising:

a first mask having a first pattern area and a first test area disposed therein; and

a second mask having a second pattern area and a second test area disposed therein,

wherein:

the first test area has a plurality of gate pattern areas disposed therein, each of the plurality of gate pattern areas having one or more gate patterns formed therein, the gate patterns formed in different areas among the plurality of gate pattern areas differing in at least one of a gate spacing or a gate width; and

the second test area has a plurality of active pattern areas disposed therein, each of the plurality of active pattern areas having one or more active patterns formed therein, the active patterns formed in different areas among the plurality of active pattern areas differing in at least one of an active spacing or an active width.

15. The mask set as claimed in claim 14, wherein:

the gate pattern areas are disposed in parallel with each other in a first direction, and

the active pattern areas are disposed in parallel with each other in a second direction.

16. The mask set as claimed in claim 15, wherein the first direction and the second direction are perpendicular to each other.

17. The mask set as claimed in claim 15, wherein the plurality of gate pattern areas and the plurality of active pattern areas are disposed to overlap each other in a grid configuration.

18. The mask set as claimed in claim 14, wherein the gate patterns are configured to form a gate electrode using a CMP process.

19. The mask set as claimed in claim 14, wherein densities of the gate patterns formed in different gate pattern areas differ from each other.

20. The mask set as claimed in claim 14, further comprising a third test mask having an area with a booster and an area without a booster.