STACK PACKAGES HAVING FASTENING ELEMENT AND HALOGEN-FREE INTER-PACKAGE CONNECTOR
A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.
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This application claims priority from and the benefit under 35 U.S.C. §119 of Korean Patent Application No. 10-2011-0041563, filed on May 2, 2011, in the Korean Intellectual Property Office (KIPO), the disclosure of which is hereby incorporated by reference.
BACKGROUND1. Field
Exemplary embodiments of the present general inventive concept relate to a stack package including a fastening element and a halogen-free inter-package connector; an electronic system; and a method of manufacturing a stack package.
2. Discussion of the Background
A package stack structure has been suggested to enhance integration density of a semiconductor device and miniaturize an electronic system.
SUMMARYExemplary embodiments of the present general inventive concept provide a stack package.
Additional aspects and advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
Exemplary embodiments of the present general inventive concept provide a stack package having a fastening element and a halogen-free inter-package connector.
Exemplary embodiments of the present general inventive concept further provide fastening elements with various shapes.
Exemplary embodiments of the present general inventive concept also provide halogen-free inter-package connectors with various shapes.
Exemplary embodiments of the present general inventive concept also provide an electronic system including a stack package.
Exemplary embodiments of the present general inventive concept also provide a method of fabricating a stack package.
Exemplary embodiments of the present general inventive concept also provide a method of forming various fastening elements.
Exemplary embodiments of the present general inventive concept also provide a method of forming various inter-package connectors.
Exemplary embodiments of the present general inventive concept also provide a stack package including a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector to connect the lower package substrate and the upper package substrate.
The package may further include an air space disposed between the fastening element and the inter-package connector.
The fastening element may be in direct contact with the top surface of the lower semiconductor chip and the bottom surface of the upper package substrate.
The fastening element may include a thermosetting resin.
The lower semiconductor package may include a lower molding material surrounding a side surface of the lower semiconductor chip and a side surface of the inter-package connector.
The lower molding material may cover the top surface of the lower semiconductor chip.
The lower molding material may expose a part of the top surface of the lower semiconductor chip.
The fastening element may be disposed on a part of the top surface of the lower semiconductor chip and a top surface of the lower molding material.
The lower molding material may surround a lower side surface of the inter-package connector, and expose an upper side surface of the inter-package connector.
The halogen-free inter-package connector may include a solder material.
The halogen-free inter-package connector may include a lower inter-package connector and an upper inter-package connector.
The lower inter-package connector may have a smaller volume than the upper inter-package connector.
The halogen-free inter-package connector may include an intermediate inter-package connector disposed between the lower inter-package connector and the upper inter-package connector.
The intermediate inter-package connector may include a conductive particle and an insulating resin.
Exemplary embodiments of the present general inventive concept also provide a stack package including a lower package including a lower package substrate, a first lower land disposed on a top surface of the lower package substrate, a second lower land disposed on a bottom surface of the lower package substrate, a lower semiconductor chip disposed on the top surface of the lower package substrate, and a lower molding material surrounding a side surface of the lower semiconductor chip, an upper package including an upper package substrate, a first upper land disposed on a top surface of the upper package substrate, a second upper land disposed on a bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the top surface of the upper package substrate, an adhesive fastening element disposed between the lower semiconductor chip and the upper package substrate, a halogen-free inter-package connector separated from the fastening element and electrically connecting the first lower land to the second upper land. An air space may exist between the lower molding material, the upper package substrate, the fastening element and the inter-package connector.
Exemplary embodiments of the present general inventive concept also provide a method including preparing an upper package in which an upper semiconductor chip is disposed on an upper package substrate, preparing a lower package in which a lower semiconductor chip is disposed on a lower package substrate, forming a fastening element between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and forming a halogen-free inter-package connector between the upper package substrate and the lower package substrate.
The halogen-free inter-package connector may include tin, silver, and copper.
The upper package substrate may include a first upper land disposed on its top surface, a second upper land disposed on its bottom, and an upper substrate interconnection electrically connecting the first upper land to the second upper land. The lower package substrate may include a first lower land disposed on its top surface, a second lower land disposed on its bottom, and a lower substrate interconnection electrically connecting the first lower land to the second lower land, and the halogen-free inter-package connector may electrically connect the second upper land to the first lower land.
Forming the halogen-free inter-package connector may include forming an upper inter-package connector in contact with the second upper land, forming a lower inter-package connector in contact with the first lower land, and heating the upper inter-package connector and the lower inter-package connector in a gas atmosphere containing hydrogen to electrically connect the upper inter-package connector to the lower inter-package connector.
The gas containing hydrogen may be hydrogen gas or formic acid gas.
Heating the upper inter-package connector and the lower inter-package connector may be performed at a temperature of 230 to 245° C.
Forming the halogen-free inter-package connector may include forming an intermediate inter-package connector between the upper inter-package connector and the lower inter-package connector.
Forming the halogen-free inter-package connector may include heating surfaces of the upper inter-package connector and the lower inter-package connector without being in contact with a flux containing halogen.
Forming the fastening element may include providing a fastening element that is not hardened on the top surface of the lower semiconductor chip, and hardening the fastening element that is not hardened.
Hardening the fastening element may include heating the fastening element at a temperature between 125° C. and 175° C.
The fastening element may include an adhesive epoxy resin.
Forming the fastening element may include forming an air space between a side surface of the fastening element and the inter-package connector.
Forming the fastening element may include forming a lower molding material covering a side surface of the lower semiconductor chip and exposing a top surface thereof and forming the fastening element on a top surface of the lower molding material.
Exemplary embodiments of the present general inventive concept also provide a method including preparing an upper package including an upper package substrate which includes a first upper land disposed on its top surface and a second upper land disposed on its bottom and an upper semiconductor chip disposed on the top surface of the upper package substrate, preparing a lower package including a lower package substrate which includes a first lower land disposed on its top surface and a second lower land disposed on its bottom, a lower semiconductor chip disposed on the top surface of the lower package substrate, and a lower molding material surrounding a side surface of the lower semiconductor chip, forming a fastening element between the top surface of the lower semiconductor chip and the bottom surface of the upper package substrate, and forming an inter-package connector penetrating the lower molding material to be formed between the second upper land and the first lower land, and spaced apart from the fastening element.
The upper semiconductor chip may include an input/output unit electrically connected to the first upper land via a wire, and the lower semiconductor chip may be disposed in a flip-chip manner using chip bumps and include an air space formed between the fastening element and the inter-package connector.
Details of other exemplary embodiments of the present general inventive concept are included in the detailed description and the drawings.
These and/or other features and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the inventive concept.
Relative terms such as “above” or “below” or “upper” or “lower” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this disclosure and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
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The lower package 10 may include a lower semiconductor chip 13 mounted on a lower package substrate 11. The lower package substrate 11 may be formed of a rigid printed circuit board, a flexible printed circuit board, or a rigid-flexible printed circuit board. The lower package substrate 11 may include first lower lands 12A, second lower lands 12B, and lower substrate interconnections 17. The first lower lands 12A may be electrically connected to the second lower lands 12B by the lower substrate interconnections 17.
The lower semiconductor chip 13 may include a logic semiconductor device, such as a microprocessor, a semiconductor memory chip, or the like. The lower semiconductor chip 13 may be connected in a flip chip manner using chip bumps 14 on the lower package substrate 11. The chip bumps 14 may include a mesa-type metal pad or a solder material. A lower underfill material 18 surrounding the chip bumps 14 may be filled between the lower package substrate 11 and the lower semiconductor chip 13. The lower underfill material 18 may include an adhesive resin. For example, the resin may include a rosin resin, an epoxy resin, or other various synthetic resins. The lower semiconductor chip 13 may be mounted on the lower package substrate 11 to be electrically connected thereto using an anisotropic conductive film or an anisotropic conductive paste such that the lower underfill material 18 may be omitted. The lower underfill material 18 may be replaced with an anisotropic conductive film or an anisotropic conductive paste.
The lower package 10 may further include a lower molding material 19 formed on the lower package substrate 11 and at least partially or completely surrounding side surfaces of the lower semiconductor chip 13. The lower molding material 19 may not be formed on the top surface of the lower semiconductor chip 13. That is, a surface of the lower semiconductor chip 13 may be exposed through the lower molding material 19. The lower molding material 19 may include an epoxy resin.
Board connection solders 16 may be formed on the bottom surface of the lower package substrate 11. The board connection solders 16 may be electrically connected to the halogen-free inter-package connectors 40 through the first and second lower lands 12A and 12B and the lower substrate interconnections 17.
The upper package 30A may include an upper semiconductor chip 33 mounted on an upper package substrate 31. The upper package substrate 31 may be formed of a rigid printed circuit board, a flexible printed circuit board or a rigid-flexible printed circuit board. The upper package substrate 31 may include first upper lands 32A, second upper lands 32B, and upper substrate interconnections 37. The upper semiconductor chip 33 may include a memory semiconductor device, a semiconductor memory chip, or the like. The upper semiconductor chip 33 may be bonded to the upper package substrate 31 through a chip bonding material 38, such as a die attach film (DAF). The upper semiconductor chip 33 may include input/output units 34. The input/output units 34 may be electrically connected to the first upper lands 32A of the upper package substrate 31 through wires 36. The first upper lands 32A may be electrically connected to the second upper lands 32B via the upper substrate interconnections 37. The upper package 30A may further include an upper molding material 39 formed on the upper package substrate 31 and surrounding top and side surfaces of the lower semiconductor chip 33. The upper molding material 39 may be formed of an epoxy resin.
The fastening element 20 may be directly formed between the top surface of the lower semiconductor chip 13 and the bottom surface of the upper package substrate 31. The fastening element 20 may be formed of a thermosetting resin exhibiting adhesion properties. For example, the fastening element 20 may be formed of a polymer resin, such as an epoxy resin. The fastening element 20 may further include a filler and/or a thermal conductive particle. The fastening element 20 may physically bond or fix the lower semiconductor chip 13 to the upper package substrate 31. The fastening element 20 may decrease, prevent, or alleviate warpage of the packages due to the coefficient of thermal expansion of the lower package substrate 11, the lower semiconductor chip 13, the lower molding material 19, the upper package substrate 31, the upper semiconductor chip 33, and/or the upper molding material 39, so that a physical connection between the halogen-free inter-package connectors 40, the chip bumps 14, and/or the board connection solders 16 may be maintained and stabilized. An air space 26 may be formed outside of the side surface of the fastening element 20. More specifically, the air space 26 may exist between the fastening element 20 and the halogen-free inter-package connectors 40. Further, the lower molding material 19 may surround lower side surfaces of the halogen-free inter-package connectors 40 and expose the upper side surfaces of the halogen-free inter-package connectors 40. In the drawing, the side surface of the fastening element 20 is illustrated to be vertically arranged with the side surface of the lower semiconductor chip 13, however, aspects are not limited thereto such that the fastening element 20 may expose at least a portion of the top surface of the lower semiconductor chip 13, and may be formed to extend toward a top surface of the lower molding material 19, which will be described hereinafter in association with other drawings of the specification.
The halogen-free inter-package connectors 40 may be disposed between the second upper land 32B and the first lower land 12A. The halogen-free inter-package connectors 40 may include lower inter-package connectors 41 and upper inter-package connectors 46. The upper inter-package connectors 46 may be formed to have a greater size or volume than the lower inter-package connectors 41. However, aspects need not be limited thereto such that the halogen-free inter-package connectors 40 may be any of various or similar shapes, at least some of which will described hereinafter.
The halogen-free inter-package connectors 40 may not include halogen group elements, such as fluorine, chlorine, bromine, and/or iodine. Halogen-free may be understood to denote not substantially containing halogen elements or being substantially free or completely free of halogen elements.
Halogen elements may be carcinogens, and may emit dioxin during combustion, and thus have been known to be harmful to the environment. The halogen-free inter-package connectors 40 do not substantially contain a halogen element, and thus are environment-friendly components. Further, the halogen-free inter-package connectors 40 may contain a small amount of a halogen element in compliance with the international environmental standard. Further description thereof will be provided below.
The halogen-free inter-package connectors 40 may include a solder material. For example, the halogen-free inter-package connectors 40 may include tin (Sn), silver (Ag), and copper (Cu). The halogen-free inter-package connectors 40 may further include nickel (Ni).
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Hydrogen or HCOOH gas washes surfaces of the lower inter-package connector 41 and the upper inter-package connector 46 to accelerate reflow. That is, oxide may be removed from the surfaces of the lower inter-package connector 41 and the upper inter-package connector 46 without using halogen group elements, and thus integration or connection of the lower inter-package connector 41 with the upper inter-package connector 46 may be accelerated. That is, the second annealing process may be a type of a solder joint process or include a solder joint process. When surface pollution of the lower inter-package connector 41 and the upper inter-package connector 46 is not cleaned, the likelihood of the integration of the lower inter-package connector 41 with the upper inter-package connector 46 is decreased, and even if the lower inter-package connector 41 and the upper inter-package connector 46 are integrated with each other, sufficient electrical conductivity may not be ensured. Therefore, the surfaces of the lower inter-package connector 41 and the upper inter-package connector 46 are cleaned.
The processes of cleaning surfaces of solders using a halogen group element may include immersing the solders in a liquid-phase surfactant containing a halogen group element. Alternatively, the processes may include contacting a vapor-phase surfactant with the surfaces of the solders. A solder flux may be a surfactant containing a halogen group element. Cleaning the surfaces of the solders using hydrogen or HCOOH gas may exhibit deteriorated cleaning abilities compared with cleaning the surfaces of the solders using the halogen group element. That is, the solder joint process of reflowing solders and integrating them exhibits insufficient efficiency. Therefore, the temperature of the second annealing process, i.e., the temperature of the solder joint process using hydrogen or HCOOH gas may be higher than that of the solder joint process using the halogen group element. When the surfaces of the solders are cleaned using the halogen group element, the solder joint process is performed at a temperature lower than the temperature range of the second annealing process. For example, the solder joint process may be performed at a temperature below 230° C. When the temperature of the second annealing process is increased, the likelihood of thermal deformation of the lower package substrate 11 or the upper package substrate 31 is increased. For example, probability of distortion or warpage of the substrate may increase. When the lower package substrate 11 or the upper package substrate 31 is distorted, the process of integrating the lower inter-package connector 41 with the upper inter-package connector 46 may be unstable. For example, they may not be sufficiently integrated. That is, solder joint reliability (SJR) may be degraded. However, existence of the fastening element 20 according to various exemplary embodiments of the present general inventive concept may alleviate distortion or warpage of the lower package substrate 11 and/or the upper package substrate 31. That is, degraded reliability of the solder joint caused by heat stress of the solder joint process may be decreased, and productivity may be increased. Therefore, the features and utilities of the present general inventive concept provide environment-friendly stack packages having excellent solder joint reliability.
A cooling process may be added between the first and second annealing processes. The cooling process may include storing the stack package 100 at room temperature for several minutes to several hours.
The stack packages 100A to 100G according to various exemplary embodiments illustrated in
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As the intermediate inter-package connector 43′ includes a large amount of a volatile solvent, the completed intermediate inter-package connector 43 exhibits reduced volume, so that its middle may be slender. For example, the completed intermediate inter-package connector 43 may be formed as illustrated in
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The power supply 2130 is supplied with a predetermined voltage from an external battery, divides the voltage into a required voltage level, and supplies the divided voltage to the microprocessor unit 2120, the functional unit 2140 and the display controller unit 2150. The microprocessor unit 2120 may be supplied with a voltage from the power supply 2130 to control the functional unit 2140 and the display unit 2160. The functional unit 2140 may perform various functions of the electronic system 2100. For example, when the electronic device 2100 is a mobile electronic appliance, such as a cellular phone, the functional unit 2140 may include various components capable of functioning as a cellular phone function including outputting an image on the display unit 2160 and outputting voice through a speaker by dialing or communication with an external apparatus 2170. Furthermore, when the external apparatus 2170 includes a camera, the functional unit 2140 may function as an image processor.
In other applied embodiments, when the electronic system 2100 may be connected to a memory card for capacity expansion, the functional unit 2140 may be a memory card controller. The functional unit 2140 may transmit/receive a signal to/from the external apparatus 2170 via a wired or wireless communication unit 2180. Moreover, when the electronic system 2100 requires a universal serial bus (USB) for function expansion, the functional unit 2140 may function as an interface controller.
The stack packages described in various embodiments according to the inventive concept may be included in at least one of the microprocessor unit 2120, power supply 2130, the functional unit 2140, and the display controller unit 2150.
According to various exemplary embodiments of the present general inventive concept, a fastening element and an air space can be formed between an upper package and a lower package. A halogen-free inter-package connector can be formed between the upper package and the lower package. Features and utilities of the present general inventive concept provide environment-friendly electronic products. Features and utilities of the present general inventive concept improves reliability of a solder joint. Features and utilities of the present general inventive concept can implement a thinner stack package. According features and utilities of the present general inventive concept, a process that does not require a flux is provided. For example, in lieu of a flux that is used for removing an oxide layer on surface of solder balls, hydrogen or a gas containing hydrogen is used, or a process that does not require a solder reflow process or requires minimum use of a flux is suggested. Since the flux includes a halogen element for removing the oxide layer, it is a material that has a negative effect on the environment. The inventive features and utilities of the present general concept provides an eco-friendly process of fabricating a semiconductor package
The components whose reference numerals are not indicated, or components with only reference numerals indicated may be easily understood with reference to the names and functions in the other drawings and descriptions thereof in the specification. Also, only representative exemplary embodiments are described in a limited manner in the specification, it will be fully understood that any feature in any exemplary embodiment may be modified, combined, and/or implemented in any other exemplary embodiment.
Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
Claims
1. A stack package, comprising:
- a lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate;
- an upper package comprising an upper package substrate and an upper semiconductor chip disposed on the upper package substrate;
- a fastening element disposed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate; and
- a halogen-free inter-package connector to connect a top surface of the lower package substrate to the bottom surface of the upper package substrate.
2. The package of claim 1, further comprising an air space disposed between the fastening element and the inter-package connector.
3. The package of claim 1, wherein the fastening element is in direct contact with the top surface of the lower semiconductor chip and the bottom surface of the upper package substrate.
4. The package of claim 1, wherein the fastening element comprises a thermosetting resin.
5. The package of claim 1, wherein the lower semiconductor package comprises a lower molding material surrounding a side surface of the lower semiconductor chip and a side surface of the inter-package connector.
6. The package of claim 5, wherein the lower molding material covers a part of the top surface of the lower semiconductor chip.
7. The package of claim 6, wherein the lower molding material exposes a part of the top surface of the lower semiconductor chip.
8. The package of claim 5, wherein the fastening element is disposed on a part of the top surface of the lower semiconductor chip and a part of a top surface of the lower molding material.
9. The package of claim 5, wherein the lower molding material surrounds a lower side surface of the inter-package connector, and exposes an upper side surface of the inter-package connector.
10. The package of claim 1, wherein the halogen-free inter-package connector comprises a solder material.
11. The package of claim 1, wherein the halogen-free inter-package connector comprises a pot shape in which a volume of an upper part is greater than a volume of the lower part.
12. The package of claim 1, wherein the halogen-free inter-package connector comprises a lower inter-package connector and an upper inter-package connector.
13. The package of claim 12, wherein the lower inter-package connector has a smaller volume than the upper inter-package connector.
14. The package of claim 12, wherein the halogen-free inter-package connector further comprises an intermediate inter-package connector disposed between the lower inter-package connector and the upper inter-package connector.
15. The package of claim 14, wherein the intermediate inter-package connector comprises a conductive particle and an insulating resin.
16. The package of claim 15, wherein the intermediate inter-package connector further comprises an anisotropic conductive paste.
17. The package of claim 14, wherein the intermediate inter-package connector comprises a middle portion that is narrower than end portions thereof.
18. The package of claim 14, wherein the intermediate inter-package connector comprises a smaller volume than each of the lower inter-package connector and the upper inter-package connector.
19. A stack package comprising:
- a lower package comprising a lower package substrate, a first lower land disposed on a top surface of the lower package substrate, a second lower land disposed on a bottom surface of the lower package substrate, a lower semiconductor chip disposed on the top surface of the lower package substrate, and a lower molding material surrounding a side surface of the lower semiconductor chip;
- an upper package comprising an upper package substrate, a first upper land disposed on a top surface of the upper package substrate, a second upper land disposed on a bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the top surface of the upper package substrate;
- an adhesive fastening element disposed between the lower semiconductor chip and the upper package substrate; and
- a halogen-free inter-package connector separated from the fastening element and electrically connecting the first lower land to the second upper land,
- wherein an air space exists between the lower molding material, the upper package substrate, the fastening element, and the inter-package connector.
20. A stack package comprising:
- a lower package comprising a lower package substrate and a lower semiconductor chip disposed on the lower package substrate;
- an upper package comprising an upper package substrate and an upper semiconductor chip disposed on the upper package substrate;
- a fastening element disposed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, wherein the fastening element physically bonds and fixes the lower semiconductor chip to the upper package substrate; and
- an inter-package connector to connect a top surface of the lower package substrate to the bottom surface of the upper package substrate, wherein the inter-package connector has an hourglass shape.
Type: Application
Filed: Apr 30, 2012
Publication Date: Nov 8, 2012
Applicant: Samsung Electronics Co., Ltd (Suwon-si)
Inventors: Heung-Kyu Kwon (Seongnam-si), Jae-Wook Yoo (Suwon-si), Hyon-Chol Kim (Hwaseong-si), Su-Chang Lee (Seoul), Min-Ok Na (Bucheon-si)
Application Number: 13/459,843
International Classification: H01L 23/52 (20060101);