SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A MASK MATERIAL
A method for fabricating semiconductor device structures includes forming a non-conformal mask over a surface of a substrate. Non-conformal mask material with a planar or substantially planar upper surface is formed on the surface of the substrate. The planarity or substantial planarity of the non-conformal material eliminates or substantially eliminates distortion in a “mask” formed thereover and, thus, eliminates or substantially eliminates distortion in any mask that is subsequently formed using the pattern of the mask. In some embodiments, mask material of the non-conformal mask does not extend into recesses in the upper surface of the substrate; instead it “bridges” the recesses. Semiconductor device structures that include non-conformal masks and semiconductor device structures that have been fabricated with non-conformal masks are also disclosed.
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This application is a divisional of U.S. patent application Ser. No. 12/477,551, filed Jun. 3, 2009, pending, the disclosure of which is hereby incorporated herein by this reference in its entirety.
TECHNICAL FIELDIn various embodiments, the present invention relates generally to non-conformal masks. In more specific embodiments, the present invention relates to masks with substantially planar upper surfaces. In some embodiments, a non-conformal mask may bridge recesses in underlying semiconductor device structures. The substantially planarity of the upper surfaces of such masks enables the precise and accurate transfer of patterns from the masks into one or more material layers of the semiconductor device structures.
BACKGROUNDAdvances in semiconductor device technologies have included the development of a number of complex, intricate structures. Examples of such structures include cross-hair cells, which may be used in dynamic random access memory (DRAM) devices, the epi-diodes of phase-change random access memory (PCRAM) devices, and pseudo silicon-on-insulator (PSOI) structures. Fabrication of these and other structures typically requires the use of two or more masks, through which material is removed to define the desired structure or structures.
Once material has been removed through a first mask, the upper, or “active,” surface of the substrate typically includes a number of recesses. As a consequence of the presence of these recesses, one of two undesirable results will occur when conventional conformal mask fabrication processes are used to form a subsequent mask: (1) the recesses must be filled with a sacrificial material before the layer of mask material is applied and the subsequent mask is formed therefrom; or (2) a layer of mask material, such as a photoresist, that will be used to define the subsequent mask will conform to the topography of the semiconductor device structure. When the recesses are not filled before mask material is applied, mask material enters the recesses, resulting in a layer of mask material with a nonplanar surface. The degree of nonplanarity corresponds to the size and/or density of recesses, with the nonplanarity being more pronounced when a substrate includes larger and/or more densely arranged recesses.
When a conformal mask is formed, different regions of the layer of mask material are located at different elevations. When a layer of photoresist is applied to the layer of mask material, it too will have different regions that are located at different elevations. Unfortunately, the tools that are used to expose the photoresist have a narrow focal plane, which may not coincide with all areas of the photoresist, causing some areas to be exposed to a blurred radiation pattern. When the exposing radiation is blurred, the precision with which mask features (e.g., solid edges, apertures, etc.) may be formed through the photoresist is reduced, as is the precision with which these features may be transferred into the mask material from which the subsequent mask will be defined.
When the recesses are filled before the mask material is applied, the semiconductor device structure must be subjected to a number of additional processes, including material deposition, planarization, and material removal processes, all of which undesirably add to the overall cost of fabrication, as well as increase the probability that the resulting semiconductor devices will be damaged.
In the drawings:
In some embodiments, a semiconductor substrate 12 upon which a mask is to be fabricated carries one or more materials 14 on its upper surface 13. In the depicted embodiment, recesses 18 extend into an upper surface 16 of substrate 10; i.e., into an upper surface of an uppermost material 14. In some embodiments, recesses 18 define semiconductor device features 14′ from one or more materials 14. In more specific embodiments, recesses 18 may be part of a first pattern 19 that has been defined in substrate 10 or from materials 14.
As shown in
Non-conformal film 20 may be formed by processes that impart it with an upper surface 22 that is, at least, more planar than the upper surface 16 over which non-conformal film 20 has been formed. In some embodiments, upper surface 22 of non-conformal film 20 may be substantially planar or even planar. The planarity or substantial planarity of upper surface 22 may be achieved solely by way of the process by which non-conformal film 20 is formed, without any further processing (e.g., planarization, polishing, etching, etc.) of upper surface 22. In a specific embodiment, a non-conformal film 20 with an upper surface 22 that is substantially planar may result from embodiments of processes where transparent carbon is deposited by low temperature plasma-enhanced chemical vapor deposition (PECVD) processes. Other processes may, of course, also be used to form a non-conformal film 20 with a substantially planar surface, including processes for forming non-conformal film 20 from materials other than transparent carbon.
Some embodiments of processes that are used to form non-conformal film 20 may result in a structure that “bridges” one or more recesses 18, covering an opening of each covered recess 18 without completely lining, or substantially entering, that covered recess 18. In such embodiments, the processes that are used to form non-conformal film 20 and the material from which non-conformal film 20 is formed are considered in conjunction with the lateral dimensions (e.g., distance across, diameter, etc.) of recesses 18, and tailored to minimize or prevent sagging of portions of non-conformal film 20 that bridge recesses 18 and to impart non-conformal film 20 with a planar or substantially planar upper surface 22. In embodiments where non-conformal film 20 is formed from transparent carbon, the transparent carbon may be deposited by known low temperature PECVD processes. In even more specific embodiments, PECVD may be used to deposit transparent carbon in such a way that it will bridge recesses 18 that are about 70 nm wide, about 100 nm wide, or even about 120 nm wide, and that are spaced about the same distance apart from one another (i.e., have about the same pitch). Of course, other embodiments of processes for forming a non-conformal film 20 that will bridge recesses 18 without substantially entering into the recesses 18, including processes for forming non-conformal film 20 from materials other than transparent carbon, are also within the scope of the present invention.
In some embodiments, a dielectric anti-reflective coating (DARC) film 24 of a known type may be formed on upper surface 22 of non-conformal film 20, as illustrated by
Once non-conformal film 20 and DARC film 24, if any, have been formed, a “soft” mask material 26 may be applied to or over upper surface 22 of non-conformal film 20, as depicted by
As depicted by
In some embodiments, where mask material 26 (
In other embodiments, the planar or substantially planar upper surface 2′7U (
Appropriate nanoimprint lithography techniques may be effected in a manner known in the art to define mask 28 from mask material 26. In more specific embodiments, known photo nanoimprint lithography techniques may be used to form a mask 28 from a mask material 26 that comprises an uncured photoresist, known thermoplastic nanoimprint lithography techniques may be used to form a mask 28 from a mask material 26 that comprises a thermoplastic material, known electro-chemical nanoimprint lithography techniques may be used to form a mask 28 from a mask material 26 that comprises a metal, and guided self-assembly processes may be used to form a mask 28 from monolayers of appropriate mask materials 26.
The masks 28 that result from these or other suitable processes may be used in conjunction with a suitable material removal process, as shown in
Mask 30 may, in some embodiments, lack distortion, other than minimal distortion that may occur as an artifact of the process used to form mask 28 (
In other embodiments, mask 30 may substantially lack distortion. Stated another way, distortion in mask 30 may be limited to minimal distortion, such as that resulting from the process by which mask 28 is formed, and nonplanarities that may occur in one or both of mask material 26 and non-conformal film 20.
As depicted by
In some embodiments, material of substrate 10 may be removed through mask 30 to directly pattern substrate 10, as depicted by
In other embodiments, such as that shown in
Like mask 30, reduced-pitch mask 50 may include apertures 52 that overlap, or “cross,” and communicate with recesses 18 in upper surface 16 of substrate 10. Thus, in some embodiments, reduced-pitch mask 50 may be used to define a second pattern 39 in upper surface 16 that crosses a previously defined first pattern 19 in upper surface 16.
A mask 30 according to embodiments of the present invention may be useful for fabricating a variety of structures, including structures that have conventionally been fabricated using two or more sequential mask-and-removal processes, as well as structures that include relatively deep trenches or other recesses. Various embodiments of structures that may be fabricated in accordance with embodiments of the present invention include, but are not limited to, PSOI structures, epi-diodes for phase change random access memory (PCRAM) devices, cross-hair cell (CHC) type memory devices, NAND Flash memory devices, and other high-voltage devices. Embodiments of the present invention may also be used to fabricate structures in the back-end-of-line (BEOL) processing of semiconductor devices.
A specific embodiment of use of the process depicted by
Once mask 30 has been formed, as shown in
Thereafter, as shown in
Any conductive material 61 that remains on upper surface 16 of dielectric 14″ may then be removed from upper surface 16 to electrically isolate adjacent conductive lines 64 from one another, as shown in
Although the foregoing description contains many specifics, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some embodiments. Similarly, other embodiments that are within the scope of the invention may also be devised. Features from different embodiments may be employed in combination. The scope of the invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein which fall within the meaning and scope of the claims are to be embraced thereby.
Claims
1. A semiconductor device structure comprising a mask material on an upper surface of a substrate, the mask material bridging at least one recess in the upper surface of substrate.
2. The semiconductor device structure of claim 1, wherein the mask material has a substantially planar upper surface.
3. The semiconductor device structure of claim 1, further comprising a mask over the mask material and comprising a pattern to be transferred into the mask material.
4. The semiconductor device structure of claim 1, wherein the mask material comprises a pattern to be transferred into a portion of the substrate.
5. The semiconductor device structure of claim 1, wherein the at least one recess in the substrate comprises a first pattern in a portion of the substrate.
6. The semiconductor device structure of claim 5, further comprising a mask over the mask material and comprising a second pattern to be transferred into the mask material, the second pattern oriented so as to cross at least a portion of the first pattern.
7. The semiconductor device structure of claim 5, wherein the mask material comprises a second pattern to be transferred into a portion of the substrate, the second pattern oriented so as to cross at least a portion of the first pattern.
8. A semiconductor device structure, comprising:
- a substrate;
- a first pattern of open recesses defined in a surface of the substrate;
- a second pattern of open recesses defined in the surface of the substrate and at least partially crossing and intersecting with the first pattern of open recesses; and
- a mask on the surface of the substrate and defining apertures corresponding to the second pattern of open recesses, the mask covering the first pattern of open recesses without substantially extending into the first pattern of open recesses.
9. The semiconductor device structure of claim 8, wherein the mask comprises transparent carbon.
10. The semiconductor device structure of claim 8, wherein the first pattern of open recesses and the second pattern of open recesses at least partially define at least one of a cross-hair cell of a memory device, a diode of a phase-change memory device, or a pseudo silicon-on-insulator structure.
11. The semiconductor device structure of claim 1, wherein the mask material bridges the at least one recess without substantially extending into the at least one recess.
12. The semiconductor device structure of claim 1, wherein the mask material comprises transparent carbon.
13. The semiconductor device structure of claim 1, wherein the mask material comprises silicon nitride doped with hydrogen.
14. The semiconductor device structure of claim 1, wherein the mask material comprises amorphous carbon.
15. The semiconductor device structure of claim 1, wherein the at least one recess has a width within a range of from about 70 nanometers to about 120 nanometers.
16. A semiconductor device structure, comprising:
- a substrate comprising a plurality of undercut structures defining a plurality of recesses; and
- a non-conformal film on the plurality of undercut structures and bridging at least a portion of the plurality of recesses.
17. The semiconductor device structure of claim 16, wherein the plurality of undercut structures comprises a plurality of pseudo silicon-on-insulator structures.
18. The semiconductor device structure of claim 17, wherein the plurality of recesses a first pattern of recesses crossing and communicating with a second pattern of recesses.
19. The semiconductor device structure of claim 16, wherein the non-conformal film has a thickness of about 2000 Angstroms.
Type: Application
Filed: Aug 6, 2012
Publication Date: Dec 20, 2012
Applicant: MICRON TECHNOLOGY, INC. (Boise, ID)
Inventor: David H. Wells (Boise, ID)
Application Number: 13/567,741
International Classification: H01L 23/58 (20060101);