Details Not Otherwise Provided For, E.g., Protection Against Moisture (epo) Patents (Class 257/E23.002)
  • Patent number: 10737930
    Abstract: A micromechanical device and a corresponding manufacturing method. The micromechanical device includes: a spring element which is moveably coupleable or is moveably coupled to a frame unit at at least one connecting point of the spring element, the spring element including at least one web, which extends outward from the at least one connecting point; and the at least one web being structured in such a way that it includes at least one first section as well as at least one widening section for reducing a non-linearity of the spring element, which is widened compared to the first section.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: August 11, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Helmut Grutzeck, Frederic Njikam Njimonzie, Hendrik Specht, Joerg Muchow, Massimiliano Putignano, Odd-Axel Pruetz
  • Patent number: 10710192
    Abstract: A method includes steps a) providing the first structure successively including a first substrate, a first layer made from a metal base and a first metal-based metal oxide, b) providing the second structure successively including a second substrate, a second layer made from a second material and a second metal-based metal oxide, the first and second metal oxides presenting a standard free enthalpy of formation ?G°, the second material being chosen so that it has an oxide presenting a standard free enthalpy of formation strictly less than ?G°, c) bonding the first structure and second structure by direct adhesion, d) activating diffusion of the oxygen atoms of the first and second metal oxides to the second layer so as to form the oxide of the second material.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 14, 2020
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Bruno Imbert, Lamine Benaissa, Paul Gondcharton
  • Patent number: 10685912
    Abstract: An integrated circuit includes a substrate; an interconnect portion disposed over the substrate, the interconnect portion comprising multiple metallization levels separated by an insulating region; and an antifuse structure coated with a portion of the insulating region, the antifuse structure comprising a beam held at two different points by two arms, a body, and an antifuse insulating zone, the beam, the body and the arms being metal and located within a same metallization level, the body and the beam mutually making contact via the antifuse insulating zone, the antifuse insulating zone configured to undergo breakdown in the presence of a breakdown potential difference between the body and the beam.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 10388615
    Abstract: Embodiments of the present invention provide integrated circuits and methods for activating reactions in integrated circuits. In one embodiment, an integrated circuit is provided having reactive material capable of being activated by electrical discharge, without requiring a battery or similar external power source, to produce an exothermic reaction that erases and/or destroys one or more semiconductor devices on the integrated circuit.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Gregory M. Fritz, Conal E. Murray, Kenneth P. Rodbell
  • Patent number: 10126260
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy
  • Patent number: 9818695
    Abstract: A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 9780009
    Abstract: A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Hsien-Wei Chen, Tsung-Fu Tsai, Wen-Hsiung Lu, Yian-Liang Kuo
  • Patent number: 9660186
    Abstract: Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinhye Bae, Wonjun Lee, Yoonsung Han, Hoon Han, Kyu-Man Hwang, Yongsun Ko
  • Patent number: 9507199
    Abstract: A black matrix is formed to an edge of a counter substrate. Then, a BM slit, which is an area where the black matrix is not present, is formed in the periphery of a seal material in order to prevent water or moisture from penetrating from the interface between the counter substrate and the black matrix. Then, a light shielding metal is formed in a layer other than a lead line layer, on the side of a TFT substrate, in order to prevent light from leaking from the BM slit. With this structure, it is possible to prevent the light from leaking from the BM slit around a screen. As a result, the degradation of the contrast can be prevented in the periphery of the screen.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: November 29, 2016
    Assignee: Japan Display Inc.
    Inventor: Syou Yanagisawa
  • Patent number: 9463998
    Abstract: A method for manufacturing a film-coated glass film includes heating a cylindrical body made of glass or ceramic with a heater provided in an interior of the cylindrical body, heating a glass film by feeding the glass film over the heated cylindrical body, and forming a film made of an oxide, a nitride, or a metal on the glass film while the film is on and being heated by the cylindrical body.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: October 11, 2016
    Assignee: NIPPON ELECTRIC GLASS CO., LTD.
    Inventor: Takayoshi Saitoh
  • Patent number: 9455232
    Abstract: A semiconductor structure includes a semiconductor substrate, one or more interconnect layers provided over the substrate and a circuit. The circuit includes a plurality of circuit elements formed at the substrate and a plurality of electrical connections provided in the one or more interconnect layers. A die seal is provided in the one or more interconnect layers. A die seal leakage detection material is arranged in the one or more interconnect layers between the die seal and the plurality of electrical connections. The die seal provides a protection of the die seal leakage detection material from moisture if the die seal is intact. The die seal leakage detection material is adapted for providing a detectable modification of the circuit after an exposure of the die seal leakage detection material to moisture.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Oliver Aubel
  • Patent number: 9013001
    Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Jing Wang
  • Patent number: 8994022
    Abstract: Embodiments of the disclosure relate to a method of evaluating a semiconductor wafer dicing process, comprising providing evaluation lines extending in at least one scribe line of the wafer, dicing the wafer in the scribe line, evaluating the length of the evaluation lines, providing an information about their length, and using the information to evaluate the dicing process.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: March 31, 2015
    Assignee: STMicroelectronics Rousset SAS
    Inventor: Francois Tailliet
  • Patent number: 8963293
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Patent number: 8951814
    Abstract: A device and method for providing access to a signal of a flip chip semiconductor die. A hole is bored into a semiconductor die to a test probe point. The hole is backfilled with a conductive material, electrically coupling the test probe point to a signal redistribution layer. A conductive bump of the signal redistribution layer is electrically coupled to a conductive contact of a package substrate. An external access point of the package substrate is electrically coupled to the conductive contact, such that signals of the flip chip semiconductor die are accessible for measurement at the external access point.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: February 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brian S. Schieck, Howard Lee Marks
  • Patent number: 8937380
    Abstract: A semiconductor package includes a lead spaced apart from a semiconductor die. The die includes a diaphragm disposed at a first side of the die and is configured to change an electrical parameter responsive to a pressure difference across the diaphragm. The die further includes a second side opposite the first side, a lateral edge extending between the first and second sides and a terminal at the first side. An electrical conductor connects the terminal to the lead. An encapsulant is disposed along the lateral edge of the die so that the terminal and the electrical conductor are spaced apart from the encapsulant. The encapsulant has an elastic modulus of less 10 MPa at room temperature. A molding compound covers and contacts the lead, the electrical conductor, the encapsulant, the terminal and part of the first side of the die so that the diaphragm is uncovered by the molding compound.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Vaupel, Uwe Fritzsche Schindler
  • Patent number: 8937310
    Abstract: Integrated circuit layers to be stacked on top of each other are formed with a plurality of inspection rectifier device units, respectively. The inspection rectifier device units including rectifier devices are connected between a plurality of connection terminals and a positive power supply lead and a grounding lead and emit light in response to a current. After electrically connecting the plurality of connection terminals to each other, a bias voltage is applied between the positive power supply lead and the grounding lead, and the connection state between the connection terminals is inspected according to a light emission of the inspection rectifier device unit. This makes it possible to inspect, in a short time every time a layer is stacked, whether or not an interlayer connection failure exists in a semiconductor integrated circuit device constructed by stacking a plurality of integrated circuit layers in their thickness direction.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: January 20, 2015
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Tomonori Nakamura
  • Patent number: 8933541
    Abstract: A semiconductor device has a semiconductor substrate with a semiconductor layer, a first element region formed on the semiconductor layer and on which are formed first semiconductor elements sensitive to stress, and a second element region formed on the semiconductor layer and on which are formed second semiconductor elements less sensitive to stress than the first semiconductor elements. The first and second element regions are formed in the semiconductor layer at preselected depths from a surface of the semiconductor layer. A buffer region for suppressing stress generated in the first element region is formed of a trench filled with a filler material and extending into the semiconductor layer so that a depth of the trench from the surface of the semiconductor layer is greater than the preselected depths, and so that a portion of the semiconductor layer exists under the filled trench of the buffer region.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 13, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Shinjiro Kato, Jun Osanai
  • Patent number: 8921982
    Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: December 30, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Tomita
  • Patent number: 8916768
    Abstract: The surface recombination velocity of a silicon sample is reduced by deposition of a thin hydrogenated amorphous silicon or hydrogenated amorphous silicon carbide film, followed by deposition of a thin hydrogenated silicon nitride film. The surface recombination velocity is further decreased by a subsequent anneal. Silicon solar cell structures using this new method for efficient reduction of the surface recombination velocity is claimed.
    Type: Grant
    Filed: April 12, 2006
    Date of Patent: December 23, 2014
    Assignees: Rec Solar Pte. Ltd., Universitetet I Oslo, Instititt for Energiteknikk
    Inventors: Alexander Ulyashin, Andreas Bentzen, Bengt Svensson, Arve Holt, Erik Sauar
  • Patent number: 8895981
    Abstract: A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of connections ordinarily used to provide connectivity between the dice. Defective connections are discovered through testing after MCM assembly and avoided, with signals being rerouted through good (e.g., not defective) redundant connections. The testing can be done at assembly time and the results stored in nonvolatile memory. Alternatively, the MCM can perform the testing itself dynamically, e.g., at power up, and use the test results to configure the inter-die I/O connections.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 25, 2014
    Assignee: Altera Corporation
    Inventor: David Lewis
  • Patent number: 8890318
    Abstract: A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Qinghuang Lin, Ying Zhang
  • Patent number: 8878183
    Abstract: A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 4, 2014
    Assignee: Microchip Technology Incorporated
    Inventor: Randy Yach
  • Patent number: 8861728
    Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gregory M. Fritz, Harold J. Hovel, Young-Hee Kim, Dirk Pfeiffer, Kenneth P. Rodbell
  • Patent number: 8835194
    Abstract: A method of testing a semiconductor substrate having through substrate vias for current leakage which includes: forming a current leakage measurement structure that includes substrate contacts, sensing circuits to sense current leakage from the through substrate vias, the sensing circuits connected to the through substrate vias and to the substrate contacts so that there is a one-to-one correspondence of a substrate contact and sensing circuit to each through substrate via, and a built-in self test (BIST) engine to sense one of the through substrate vias for current leakage. A reference current is applied to the sensing circuits to set a current leakage threshold for the through substrate vias. A through substrate via is selected for sensing for current leakage. The sensing circuit senses the selected through substrate via to determine whether there is current leakage from the selected through substrate via.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bhavana Bhoovaraghan, Mukta G. Farooq, Emily R. Kinser, Sudesh Saroop
  • Patent number: 8836096
    Abstract: An image sensor unit includes a fixed substrate, a movable substrate, an actuate section including an actuator for moving the movable substrate against the fixed substrate, an image sensor having an imaging surface on a front surface of the image sensor, and at least, a part of a rear surface of the image sensor being directly fixed onto the movable substrate, an external electrical connecting member for conducting a transmission and reception of signals between the actuate section and the image sensor and an outside of the image sensor unit, and an internal electrical connecting member electrically connects the actuate section, the image sensor and the external connection wiring, wherein the actuate section, the image sensor, the internal connection wiring and a part of the external connection wiring are sealed into the same space.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Konica Minolta Opto, Inc.
    Inventors: Akira Kosaka, Masataka Hamada, Satoshi Yokota, Yoshihiro Hara, Yasutaka Tanimura
  • Patent number: 8829660
    Abstract: A resin-sealed semiconductor device includes a semiconductor chip including a silicon substrate; a die pad on which the semiconductor chip is secured via a solder layer; a sealing resin layer sealing the semiconductor chip; and lead terminals connected electrically with the semiconductor chip. One end portion of the lead terminals is covered by the sealing resin layer. The die pad and the lead terminals are formed of copper and a copper alloy, and the die pad is formed with a thickness larger than a thickness of the lead terminals, which is a thickness of 0.25 mm or more.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yasumasa Kasuya, Motoharu Haga, Shoji Yasunaga
  • Patent number: 8823136
    Abstract: A set of metal line structures including a signal transmission metal line and a capacitively-grounded inductively-signal-coupled metal line is embedded in a dielectric material layer. A capacitor is serially connected between the capacitively-grounded inductively-signal-coupled metal line and a local electrical ground, which may be on the input side or on the output side. The set of metal line structures and the capacitor collective provide a frequency dependent inductor. The Q factor of the frequency dependent inductor has multiple peaks that enable the operation of the frequency dependent inductor at multiple frequencies. Multiple capacitively-grounded inductively-signal-coupled metal lines may be provided in the frequency-dependent inductor, each of which is connected to the local electrical ground through a capacitor. By selecting different capacitance values for the capacitors, multiple values of the Q-factor may be obtained in the frequency dependent inductor at different signal frequencies.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hanyi Ding, Wayne H. Woods
  • Patent number: 8803238
    Abstract: To increase the integration degree of a semiconductor device, the semiconductor device having a Plasma-Induced Damage (PID) protective diode includes a well, at least a first transistor region formed over the well, a gate electrode formed over the first transistor region, a well guard disposed to include an open region while surrounding the first transistor region, a diode disposed in the open region, and a metal line configured to electrically connect the gate electrode and the diode. A space between transistor regions may be efficiently reduced, thus increasing the integration degree of a semiconductor device.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: August 12, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Ho Kim
  • Patent number: 8803295
    Abstract: A manufacturing method of a circuit structure is provided. A metal layer having an upper surface is provided. A surface passivation layer is formed on the metal layer. The surface passivation layer exposes a portion of the upper surface of the metal layer, and a material of the metal layer is different from a material of the surface passivation layer. A covering layer is formed on the surface passivation layer, and the covering layer covers the surface passivation layer.
    Type: Grant
    Filed: February 12, 2012
    Date of Patent: August 12, 2014
    Assignee: Subtron Technology Co., Ltd.
    Inventor: Ching-Sheng Chen
  • Patent number: 8786084
    Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-François Sauty
  • Patent number: 8786092
    Abstract: A semiconductor integrated circuit device includes: a rectangular shaped semiconductor substrate; a metal wiring layer formed on or over the semiconductor substrate; and a passivation layer covering the metal wiring layer. A corner non-wiring region where no portion of the metal wiring layer is formed is disposed in a corner of the semiconductor substrate. A slit is formed in a portion of the metal wiring layer which is close to the corner of the semiconductor substrate. The passivation layer includes a first passivation layer which is formed on the metal wiring layer and a second passivation layer which is formed on the first passivation layer. The first passivation layer is formed of a material that is softer than a material of the second passivation layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 22, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Mitsuru Okazaki, Youichi Kajiwara, Naoki Takahashi, Akira Shimizu
  • Patent number: 8779535
    Abstract: Integrated devices and methods for packaging the same can include an external housing, an internal housing positioned within the external housing, and an external cavity formed between the external housing and the internal housing. An integrated device die can be positioned within the external cavity in fluid communication with an internal cavity formed by the internal lid. An air way can extend through the external cavity to the internal cavity, and can further extend from the internal cavity to the external cavity. The air way can provide fluid communication between the package exterior and the integrated device die, while reducing contamination of the integrated device die.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 15, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Thomas M. Goida, Jicheng Yang
  • Patent number: 8766412
    Abstract: A semiconductor chip has devices formed on a first principal plane of a semiconductor substrate, wherein a second principal plane of the semiconductor substrate is planarized, and an organic film having plus charges on an outer side is provided on the second principal plane.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Manabu Matsumoto
  • Patent number: 8749031
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor device body and an insulating adhesive layer. The semiconductor device body is formed with a square plate shape and has an element portion provided on a first major surface. The insulating adhesive layer is provided to cover a second major surface of the semiconductor device body and one or two of four side faces of the semiconductor device body.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: June 10, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Matsushima
  • Patent number: 8750031
    Abstract: Test structures, methods of manufacturing thereof, test methods, and magnetic random access memory (MRAM) arrays are disclosed. In one embodiment, a test structure is disclosed. The test structure includes an MRAM cell having a magnetic tunnel junction (MTJ) and a transistor coupled to the MTJ. The test structure includes a test node coupled between the MTJ and the transistor, and a contact pad coupled to the test node.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Chen Kao, Tien-Wei Chiang, Chun-Jung Lin
  • Patent number: 8741739
    Abstract: A semiconductor structure and a method of forming the same. In one embodiment, a method of forming a silicon-on-insulator (SOI) wafer substrate includes: providing a handle substrate; forming a high resistivity material layer over the handle substrate, the high resistivity material layer including one of an amorphous silicon carbide (SiC), a polycrystalline SiC, an amorphous diamond, or a polycrystalline diamond; forming an insulator layer over the high resistivity material layer; and bonding a donor wafer to a top surface of the insulator layer to form the SOI wafer substrate.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Mark D. Jaffe, Alvin J. Joseph
  • Patent number: 8728905
    Abstract: A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huilong Zhu, Jing Wang
  • Patent number: 8723291
    Abstract: A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: May 13, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Yonezu, Takeshi Iwamoto, Shigeki Obayashi, Masashi Arakawa, Kazushi Kono
  • Publication number: 20140117468
    Abstract: An integrated circuit package for sensing fluid properties includes: a substrate made of semiconductor material; a fluid property measurement circuit formed on the substrate; and a sensor circuit coupled to the fluid property measurement circuit within a same integrated circuit package. The sensor circuit is configured to generate a field that interacts with the fluid. The fluid property measurement circuit is configured to determine a change in a property of the sensor circuit as results from the field interacting with the fluid and is further configured to determine a property of the fluid based on the change in the property of the sensor circuit.
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: PATRICE M. PARRIS, MD M. HOQUE
  • Publication number: 20140117529
    Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
    Type: Application
    Filed: October 25, 2012
    Publication date: May 1, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Kyle Armstrong, Michael D. Hyatt, Michael Dean Van Patten, David A. Kewley, Ming-Chuan Yang
  • Patent number: 8710595
    Abstract: A seal ring structure is formed through a multilayer structure of a plurality of dielectric films in a peripheral part of a chip region to surround the chip region. A dual damascene interconnect in which an interconnect and a plug connected to the interconnect are integrated is formed in at least one of the dielectric films in the chip region. Part of the seal ring structure formed in the dielectric film in which the dual damascene interconnect is formed is continuous. A protection film formed on the multilayer structure has an opening on the seal ring. A cap layer connected to the seal ring is formed in the opening.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Makoto Tsutsue, Masaki Utsumi
  • Publication number: 20140103532
    Abstract: An electronic apparatus includes a semiconductor substrate, a device structure supported by the semiconductor substrate, and a guard ring surrounding the device structure. The guard ring includes a plurality of conductive structures spaced apart from one another, supported by the semiconductor substrate, and coupled to a voltage source to establish an operating voltage for the guard ring.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Inventors: Jenn Hwa Huang, Jose L. Suarez, Yun Wei
  • Patent number: 8698139
    Abstract: Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: April 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Seyfollah Seyfollahi Bazarjani, Reza Jalilizeinali
  • Publication number: 20140097469
    Abstract: Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device and methods of fabrication thereof are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD).
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Inventors: Helmut Hagleitner, Zoltan Ring
  • Patent number: 8692246
    Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bhavana Bhoovaraghan, Mukta G. Farooq, Emily R. Kinser, Sudesh Saroop
  • Publication number: 20140091440
    Abstract: Electronic assemblies and their manufacture are described. One assembly includes a coreless substrate comprising a plurality of dielectric layers and electrically conductive pathways, the coreless substrate including a first side and a second side opposite the first side. The assembly includes a first die embedded in the coreless substrate, the first die comprising an RF die, the first die positioned in a dielectric layer that extends to the first side of the coreless substrate. The assembly includes a second die positioned on first side, the second die positioned on the first die. In another aspect, a molding material may be positioned on the die side, wherein the first die and the second die are covered by the molding material. In another aspect, an electrical shielding layer may be positioned over the first side. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2012
    Publication date: April 3, 2014
    Inventors: Vijay K. NAIR, John S. GUZEK, Johanna M. SWAN
  • Patent number: 8686533
    Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Chun Wang, Tzu-Hsuan Hsu
  • Publication number: 20140084373
    Abstract: A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.
    Type: Application
    Filed: September 21, 2012
    Publication date: March 27, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chien-Fu Huang
  • Patent number: 8680524
    Abstract: A method of arranging pads in a semiconductor memory device, the semiconductor memory device using the method, and a processing system having mounted therein the semiconductor memory device. The method includes classifying pads provided in a memory chip of the semiconductor memory device into monitoring pads configured for a memory chip test on a wafer, a package pads configured for wire connection in a package, and common pads configured for both the memory chip test on the wafer and wire connection in the package and arranging the monitoring pads and the package pads separately in columns on the memory chip.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chi-sung Oh